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Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.

Browse Source 
opcodes/
	PR binutils/20196
	* ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
	opcodes for E6500.

gas/
	PR binutils/20196
	* gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx,
	stbcx., sthcx., stwcx., stdcx.>: Add tests.
	* gas/testsuite/gas/ppc/e6500.d: Likewise.
	* gas/testsuite/gas/ppc/power8.s: Likewise.
	* gas/testsuite/gas/ppc/power8.d: Likewise.
	* gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx.,
	stdcx.>: Add tests.
	* gas/testsuite/gas/ppc/power4.d: Likewise.
This commit is contained in:
Peter Bergner
2016-06-03 18:38:02 -05:00
parent 07f5af7d3c
commit 026122a670
9 changed files with 137 additions and 5 deletions

12
gas/ChangeLog

@ -1,3 +1,15 @@
2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
PR binutils/20196
* gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx,
stbcx., sthcx., stwcx., stdcx.>: Add tests.
* gas/testsuite/gas/ppc/e6500.d: Likewise.
* gas/testsuite/gas/ppc/power8.s: Likewise.
* gas/testsuite/gas/ppc/power8.d: Likewise.
* gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx.,
stdcx.>: Add tests.
* gas/testsuite/gas/ppc/power4.d: Likewise.
2016-06-03 H.J. Lu <hongjiu.lu@intel.com> 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
PR binutis/18386 PR binutis/18386

17
gas/testsuite/gas/ppc/e6500.d

@ -73,3 +73,20 @@ Disassembly of section \.text:
fc: (7c 43 09 8d|8d 09 43 7c) icblq. 2,r3,r1 fc: (7c 43 09 8d|8d 09 43 7c) icblq. 2,r3,r1
100: (7c 10 02 dc|dc 02 10 7c) mftmr r0,16 100: (7c 10 02 dc|dc 02 10 7c) mftmr r0,16
104: (7c 10 03 dc|dc 03 10 7c) mttmr 16,r0 104: (7c 10 03 dc|dc 03 10 7c) mttmr 16,r0
.*: (7e 80 38 68|68 38 80 7e) lbarx r20,0,r7
.*: (7e 81 38 68|68 38 81 7e) lbarx r20,r1,r7
.*: (7e a0 40 e8|e8 40 a0 7e) lharx r21,0,r8
.*: (7e a1 40 e8|e8 40 a1 7e) lharx r21,r1,r8
.*: (7e c0 48 28|28 48 c0 7e) lwarx r22,0,r9
.*: (7e c1 48 28|28 48 c1 7e) lwarx r22,r1,r9
.*: (7e e0 50 a8|a8 50 e0 7e) ldarx r23,0,r10
.*: (7e e1 50 a8|a8 50 e1 7e) ldarx r23,r1,r10
.*: (7d 40 3d 6d|6d 3d 40 7d) stbcx\. r10,0,r7
.*: (7d 41 3d 6d|6d 3d 41 7d) stbcx\. r10,r1,r7
.*: (7d 60 45 ad|ad 45 60 7d) sthcx\. r11,0,r8
.*: (7d 61 45 ad|ad 45 61 7d) sthcx\. r11,r1,r8
.*: (7d 80 49 2d|2d 49 80 7d) stwcx\. r12,0,r9
.*: (7d 81 49 2d|2d 49 81 7d) stwcx\. r12,r1,r9
.*: (7d a0 51 ad|ad 51 a0 7d) stdcx\. r13,0,r10
.*: (7d a1 51 ad|ad 51 a1 7d) stdcx\. r13,r1,r10
#pass

16
gas/testsuite/gas/ppc/e6500.s

@ -67,3 +67,19 @@ start:
icblq. 2,3,1 icblq. 2,3,1
mftmr 0,16 mftmr 0,16
mttmr 16,0 mttmr 16,0
lbarx 20,0,7
lbarx 20,1,7
lharx 21,0,8
lharx 21,1,8
lwarx 22,0,9
lwarx 22,1,9
ldarx 23,0,10
ldarx 23,1,10
stbcx. 10,0,7
stbcx. 10,1,7
sthcx. 11,0,8
sthcx. 11,1,8
stwcx. 12,0,9
stwcx. 12,1,9
stdcx. 13,0,10
stdcx. 13,1,10

11
gas/testsuite/gas/ppc/power4.d

@ -10,7 +10,7 @@ start address 0x0+
Sections: Sections:
Idx Name +Size +VMA +LMA +File off +Algn Idx Name +Size +VMA +LMA +File off +Algn
+0 \.text +0+e8 +0+ +0+ +.* +0 \.text +0+108 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+1 \.data +0+20 +0+ +0+ +.* +1 \.data +0+20 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, DATA +CONTENTS, ALLOC, LOAD, DATA
@ -106,3 +106,12 @@ Disassembly of section \.text:
.*: (7c 20 04 ac|ac 04 20 7c) lwsync .*: (7c 20 04 ac|ac 04 20 7c) lwsync
.*: (7c 40 04 ac|ac 04 40 7c) ptesync .*: (7c 40 04 ac|ac 04 40 7c) ptesync
.*: (7c 40 04 ac|ac 04 40 7c) ptesync .*: (7c 40 04 ac|ac 04 40 7c) ptesync
.*: (7e 80 30 28|28 30 80 7e) lwarx r20,0,r6
.*: (7e 81 30 28|28 30 81 7e) lwarx r20,r1,r6
.*: (7e a0 38 a8|a8 38 a0 7e) ldarx r21,0,r7
.*: (7e a1 38 a8|a8 38 a1 7e) ldarx r21,r1,r7
.*: (7e c0 41 2d|2d 41 c0 7e) stwcx\. r22,0,r8
.*: (7e c1 41 2d|2d 41 c1 7e) stwcx\. r22,r1,r8
.*: (7e e0 49 ad|ad 49 e0 7e) stdcx\. r23,0,r9
.*: (7e e1 49 ad|ad 49 e1 7e) stdcx\. r23,r1,r9
#pass

8
gas/testsuite/gas/ppc/power4.s

@ -79,6 +79,14 @@ dsym1:
sync 1 sync 1
ptesync ptesync
sync 2 sync 2
lwarx 20,0,6
lwarx 20,1,6
ldarx 21,0,7
ldarx 21,1,7
stwcx. 22,0,8
stwcx. 22,1,8
stdcx. 23,0,9
stdcx. 23,1,9
.section ".data" .section ".data"
usym0: .llong 0xcafebabe usym0: .llong 0xcafebabe

32
gas/testsuite/gas/ppc/power8.d

@ -160,4 +160,36 @@ Disassembly of section \.text:
.*: (7d 20 3f 99|99 3f 20 7d) stxvd2x vs41,0,r7 .*: (7d 20 3f 99|99 3f 20 7d) stxvd2x vs41,0,r7
.*: (7d 75 47 98|98 47 75 7d) stxvd2x vs11,r21,r8 .*: (7d 75 47 98|98 47 75 7d) stxvd2x vs11,r21,r8
.*: (7d 75 47 98|98 47 75 7d) stxvd2x vs11,r21,r8 .*: (7d 75 47 98|98 47 75 7d) stxvd2x vs11,r21,r8
.*: (7e 80 38 68|68 38 80 7e) lbarx r20,0,r7
.*: (7e 80 38 68|68 38 80 7e) lbarx r20,0,r7
.*: (7e 80 38 69|69 38 80 7e) lbarx r20,0,r7,1
.*: (7e 81 38 68|68 38 81 7e) lbarx r20,r1,r7
.*: (7e 81 38 68|68 38 81 7e) lbarx r20,r1,r7
.*: (7e 81 38 69|69 38 81 7e) lbarx r20,r1,r7,1
.*: (7e a0 40 a8|a8 40 a0 7e) ldarx r21,0,r8
.*: (7e a0 40 a8|a8 40 a0 7e) ldarx r21,0,r8
.*: (7e a0 40 a9|a9 40 a0 7e) ldarx r21,0,r8,1
.*: (7e a1 40 a8|a8 40 a1 7e) ldarx r21,r1,r8
.*: (7e a1 40 a8|a8 40 a1 7e) ldarx r21,r1,r8
.*: (7e a1 40 a9|a9 40 a1 7e) ldarx r21,r1,r8,1
.*: (7e c0 48 e8|e8 48 c0 7e) lharx r22,0,r9
.*: (7e c0 48 e8|e8 48 c0 7e) lharx r22,0,r9
.*: (7e c0 48 e9|e9 48 c0 7e) lharx r22,0,r9,1
.*: (7e c1 48 e8|e8 48 c1 7e) lharx r22,r1,r9
.*: (7e c1 48 e8|e8 48 c1 7e) lharx r22,r1,r9
.*: (7e c1 48 e9|e9 48 c1 7e) lharx r22,r1,r9,1
.*: (7e e0 50 28|28 50 e0 7e) lwarx r23,0,r10
.*: (7e e0 50 28|28 50 e0 7e) lwarx r23,0,r10
.*: (7e e0 50 29|29 50 e0 7e) lwarx r23,0,r10,1
.*: (7e e1 50 28|28 50 e1 7e) lwarx r23,r1,r10
.*: (7e e1 50 28|28 50 e1 7e) lwarx r23,r1,r10
.*: (7e e1 50 29|29 50 e1 7e) lwarx r23,r1,r10,1
.*: (7d 40 3d 6d|6d 3d 40 7d) stbcx\. r10,0,r7
.*: (7d 41 3d 6d|6d 3d 41 7d) stbcx\. r10,r1,r7
.*: (7d 60 45 ad|ad 45 60 7d) sthcx\. r11,0,r8
.*: (7d 61 45 ad|ad 45 61 7d) sthcx\. r11,r1,r8
.*: (7d 80 49 2d|2d 49 80 7d) stwcx\. r12,0,r9
.*: (7d 81 49 2d|2d 49 81 7d) stwcx\. r12,r1,r9
.*: (7d a0 51 ad|ad 51 a0 7d) stdcx\. r13,0,r10
.*: (7d a1 51 ad|ad 51 a1 7d) stdcx\. r13,r1,r10
#pass #pass

32
gas/testsuite/gas/ppc/power8.s

@ -152,3 +152,35 @@ power8:
stxvd2x 41,0,7 stxvd2x 41,0,7
stxvx 11,21,8 stxvx 11,21,8
stxvd2x 11,21,8 stxvd2x 11,21,8
lbarx 20,0,7
lbarx 20,0,7,0
lbarx 20,0,7,1
lbarx 20,1,7
lbarx 20,1,7,0
lbarx 20,1,7,1
ldarx 21,0,8
ldarx 21,0,8,0
ldarx 21,0,8,1
ldarx 21,1,8
ldarx 21,1,8,0
ldarx 21,1,8,1
lharx 22,0,9
lharx 22,0,9,0
lharx 22,0,9,1
lharx 22,1,9
lharx 22,1,9,0
lharx 22,1,9,1
lwarx 23,0,10
lwarx 23,0,10,0
lwarx 23,0,10,1
lwarx 23,1,10
lwarx 23,1,10,0
lwarx 23,1,10,1
stbcx. 10,0,7
stbcx. 10,1,7
sthcx. 11,0,8
sthcx. 11,1,8
stwcx. 12,0,9
stwcx. 12,1,9
stdcx. 13,0,10
stdcx. 13,1,10

6
opcodes/ChangeLog

@ -1,3 +1,9 @@
2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
PR binutils/20196
* ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
opcodes for E6500.
2016-06-03 H.J. Lu <hongjiu.lu@intel.com> 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
PR binutis/18386 PR binutis/18386

8
opcodes/ppc-opc.c

@ -4824,7 +4824,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}}, {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
{"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}}, {"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
{"lbarx", X(31,52), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, {"lbarx", X(31,52), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
{"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}}, {"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
@ -4904,7 +4904,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}}, {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}}, {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}},
{"lharx", X(31,116), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, {"lharx", X(31,116), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}}, {"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
@ -5954,7 +5954,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE, {0}}, {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE, {0}},
{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, PPCNONE, {HTM_A}}, {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, PPCNONE, {HTM_A}},
{"stbcx.", XRC(31,694,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}}, {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}},
{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
@ -5986,7 +5986,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}}, {"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}},
{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}}, {"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
{"sthcx.", XRC(31,726,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}}, {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}},
{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},