espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-19 09:14:14 +08:00
Code Issues Packages Projects Releases Wiki Activity

RISC-V: Add T-Head Int vendor extension

Browse Source 
This patch adds the XTheadInt extension, which provides interrupt
stack management instructions.

The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
  https://github.com/riscv-non-isa/riscv-toolchain-conventions

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Christoph Müllner
2022-11-13 16:59:21 +01:00
committed by Nelson Chu
parent 4a3bc79bf4
commit 01804a098d
8 changed files with 38 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
include/opcode/riscv-opc.h
View File

@ -2213,6 +2213,11 @@
#define MASK_TH_FMV_HW_X 0xfff0707f
#define MATCH_TH_FMV_X_HW 0x5000100b
#define MASK_TH_FMV_X_HW 0xfff0707f
/* Vendor-specific (T-Head) XTheadInt instructions. */
#define MATCH_TH_IPOP 0x0050000b
#define MASK_TH_IPOP 0xffffffff
#define MATCH_TH_IPUSH 0x0040000b
#define MASK_TH_IPUSH 0xffffffff
/* Vendor-specific (T-Head) XTheadMac instructions. */
#define MATCH_TH_MULA 0x2000100b
#define MASK_TH_MULA 0xfe00707f
@ -3130,6 +3135,9 @@ DECLARE_INSN(th_fsurw, MATCH_TH_FSURW, MASK_TH_FSURW)
/* Vendor-specific (T-Head) XTheadFmv instructions. */
DECLARE_INSN(th_fmv_hw_x, MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X)
DECLARE_INSN(th_fmv_x_hw, MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW)
/* Vendor-specific (T-Head) XTheadInt instructions. */
DECLARE_INSN(th_ipop, MATCH_TH_IPOP, MASK_TH_IPOP)
DECLARE_INSN(th_ipush, MATCH_TH_IPUSH, MASK_TH_IPUSH)
/* Vendor-specific (T-Head) XTheadMac instructions. */
DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA)
DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH)