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RISC-V: Add Zcmt instructions and csr.

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This patch supports Zcmt[1] instruction 'cm.jt' and 'cm.jalt'.
Add new CSR jvt for tablejump using. Since 'cm.jt' and 'cm.jalt'
have the same instructiong encoding, use 'match_cm_jt' and 'match_cm_jalt'
check the 'zcmt_index' field to distinguish them.

[1] https://github.com/riscvarchive/riscv-code-size-reduction/releases

Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): New extension.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): New CSR.
	(riscv_csr_address): Ditto.
	(validate_riscv_insn): New operand.
	(riscv_ip): Ditto.
	* testsuite/gas/riscv/csr-version-1p10.d: New CSR.
	* testsuite/gas/riscv/csr-version-1p10.l: Ditto.
	* testsuite/gas/riscv/csr-version-1p11.d: Ditto.
	* testsuite/gas/riscv/csr-version-1p11.l: Ditto.
	* testsuite/gas/riscv/csr-version-1p12.d: Ditto.
	* testsuite/gas/riscv/csr-version-1p12.l: Ditto.
	* testsuite/gas/riscv/csr.s: Ditto.
	* testsuite/gas/riscv/march-help.l: New extension.
	* testsuite/gas/riscv/zcmt-fail.d: New test.
	* testsuite/gas/riscv/zcmt-fail.l: New test.
	* testsuite/gas/riscv/zcmt-fail.s: New test.
	* testsuite/gas/riscv/zcmt.d: New test.
	* testsuite/gas/riscv/zcmt.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_CM_JT): New opcode.
	(MASK_CM_JT): New mask.
	(MATCH_CM_JALT): New opcode.
	(MASK_CM_JALT): New mask.
	(CSR_JVT): New CSR.
	(DECLARE_INSN): New declaration.
	(DECLARE_CSR): Ditto.
	* opcode/riscv.h (EXTRACT_ZCMT_INDEX): New marco.
	(ENCODE_ZCMT_INDEX): Ditto.
	(enum riscv_insn_class): New class.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): New operand.
	* riscv-opc.c (match_cm_jt): New function.
	(match_cm_jalt): Ditto.
This commit is contained in:
Jiawei
2024-10-29 20:44:23 +08:00
committed by Nelson Chu
parent 46e64f7387
commit 00ef37e860
19 changed files with 144 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
include/opcode/riscv-opc.h
View File

@@ -2305,6 +2305,11 @@
#define MASK_CM_MVA01S 0xfc63
#define MATCH_CM_MVSA01 0xac22
#define MASK_CM_MVSA01 0xfc63
/* Zcmt instructions. */
#define MATCH_CM_JT 0xa002
#define MASK_CM_JT 0xfc03
#define MATCH_CM_JALT 0xa002
#define MASK_CM_JALT 0xfc03
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -4190,6 +4195,8 @@
#define CSR_MSCONTEXT 0x7aa
/* Unprivileged Scalar Crypto CSR addresses. */
#define CSR_SEED 0x015
/* Unprivileged Zcmt CSR addresses. */
#define CSR_JVT 0x017
/* Unprivileged Vector CSR addresses. */
#define CSR_VSTART 0x008
#define CSR_VXSAT 0x009
@@ -4731,6 +4738,9 @@ DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET)
DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ)
DECLARE_INSN(cm_mvsa01, MATCH_CM_MVSA01, MASK_CM_MVSA01)
DECLARE_INSN(cm_mva01s, MATCH_CM_MVA01S, MASK_CM_MVA01S)
/* Zcmt instructions. */
DECLARE_INSN(cm_jt, MATCH_CM_JT, MASK_CM_JT)
DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
@@ -5304,6 +5314,8 @@ DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_
DECLARE_CSR(mscontext, CSR_MSCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
/* Unprivileged Scalar Crypto CSRs. */
DECLARE_CSR(seed, CSR_SEED, CSR_CLASS_ZKR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
/* Unprivileged Zcmt CSRs. */
DECLARE_CSR(jvt, CSR_JVT, CSR_CLASS_ZCMT, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
/* Unprivileged Vector CSRs. */
DECLARE_CSR(vstart, CSR_VSTART, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)

5
include/opcode/riscv.h
View File

@@ -115,6 +115,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 5, 1) << 1)
#define EXTRACT_ZCMP_SPIMM(x) \
(RV_X(x, 2, 2) << 4)
#define EXTRACT_ZCMT_INDEX(x) \
(RV_X(x, 2, 8))
/* Vendor-specific (CORE-V) extract macros. */
#define EXTRACT_CV_IS2_UIMM5(x) \
(RV_X(x, 20, 5))
@@ -183,6 +185,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 1, 1) << 5)
#define ENCODE_ZCMP_SPIMM(x) \
(RV_X(x, 4, 2) << 2)
#define ENCODE_ZCMT_INDEX(x) \
(RV_X(x, 0, 8) << 2)
/* Vendor-specific (CORE-V) encode macros. */
#define ENCODE_CV_IS2_UIMM5(x) \
(RV_X(x, 0, 5) << 20)
@@ -517,6 +521,7 @@ enum riscv_insn_class
INSN_CLASS_ZCB_AND_ZMMUL,
INSN_CLASS_ZCMOP,
INSN_CLASS_ZCMP,
INSN_CLASS_ZCMT,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,