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Correct disassembly of dot product instructions.

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Dot products deviate from the normal disassembly rules for lane indexed
instruction. Their canonical representation is in the form of:

v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote
that these instructions select 4x 1 byte elements instead of a single 1 byte
element.

Previously we were disassembling them following the normal rules, this patch
corrects the disassembly.

gas/

	PR gas/22559
	* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B.
	* gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly.

include/

	PR gas/22559
	* aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B.

opcodes/

	PR gas/22559
	* aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
	AARCH64_OPND_QLF_S_4B
	* aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
	AARCH64_OPND_QLF_S_4B
	* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
	* aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
This commit is contained in:
Tamar Christina
2017-12-19 12:05:20 +00:00
parent a3b3345ae6
commit 00c2093f69
10 changed files with 471 additions and 438 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
include/opcode/aarch64.h
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@ -396,6 +396,11 @@ enum aarch64_opnd_qualifier
AARCH64_OPND_QLF_S_S,
AARCH64_OPND_QLF_S_D,
AARCH64_OPND_QLF_S_Q,
/* This type qualifier has a special meaning in that it means that 4 x 1 byte
are selected by the instruction. Other than that it has no difference
with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
reasons and is an exception from normal AArch64 disassembly scheme. */
AARCH64_OPND_QLF_S_4B,
/* Qualifying an operand which is a SIMD vector register or a SIMD vector
register list; indicating register shape.