#include "xil_types.h"
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/outbyte.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/outbyte.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/outbyte.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/outbyte.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/print.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/print.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c
index 31d7b19890..74d70ee4a1 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/print.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c
@@ -24,7 +24,7 @@ void print(const char8 *ptr)
#ifdef STDOUT_BASEADDRESS
while (*ptr != (char8)0) {
outbyte (*ptr);
- *ptr++;
+ ptr++;
}
#else
(void)ptr;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/putnum.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/putnum.c
similarity index 96%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/putnum.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/putnum.c
index 86d3a74e82..aaf9edee7e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/putnum.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/putnum.c
@@ -27,7 +27,7 @@ void putnum(u32 num);
void putnum(u32 num)
{
char8 buf[9];
- u32 cnt;
+ s32 cnt;
s32 i;
char8 *ptr;
u32 digit;
@@ -36,7 +36,7 @@ void putnum(u32 num)
}
ptr = buf;
- for (cnt = 7U ; cnt >= 0U ; cnt--) {
+ for (cnt = 7 ; cnt >= 0 ; cnt--) {
digit = (num >> (cnt * 4U)) & 0x0000000fU;
if ((digit <= 9U) && (ptr != NULL)) {
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/read.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/read.c
similarity index 78%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/read.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/read.c
index 90fb250298..7f7b7d2615 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/read.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/read.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -29,15 +29,12 @@
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
-/* Use toolchain function for openamp applications*/
-
-#ifndef UNDEFINE_FILE_OPS
/* read.c -- read bytes from a input device.
*/
-
-#include "xparameters.h"
+#ifndef UNDEFINE_FILE_OPS
#include "xil_printf.h"
+#include "xparameters.h"
#ifdef __cplusplus
extern "C" {
@@ -54,25 +51,21 @@ read (s32 fd, char8* buf, s32 nbytes)
{
#ifdef STDIN_BASEADDRESS
s32 i;
+ s32 numbytes = 0;
char8* LocalBuf = buf;
(void)fd;
- for (i = 0; i < nbytes; i++) {
- if(LocalBuf != NULL) {
- LocalBuf += i;
- }
- if(LocalBuf != NULL) {
- *LocalBuf = inbyte();
- if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
- break;
+ if(LocalBuf != NULL) {
+ for (i = 0; i < nbytes; i++) {
+ numbytes++;
+ *(LocalBuf + i) = inbyte();
+ if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+ break;
}
}
- if(LocalBuf != NULL) {
- LocalBuf -= i;
- }
}
- return (i + 1);
+ return numbytes;
#else
(void)fd;
(void)buf;
@@ -86,25 +79,21 @@ _read (s32 fd, char8* buf, s32 nbytes)
{
#ifdef STDIN_BASEADDRESS
s32 i;
+ s32 numbytes = 0;
char8* LocalBuf = buf;
(void)fd;
- for (i = 0; i < nbytes; i++) {
- if(LocalBuf != NULL) {
- LocalBuf += i;
- }
- if(LocalBuf != NULL) {
- *LocalBuf = inbyte();
- if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
- break;
+ if(LocalBuf != NULL) {
+ for (i = 0; i < nbytes; i++) {
+ numbytes++;
+ *(LocalBuf + i) = inbyte();
+ if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+ break;
}
}
- if(LocalBuf != NULL) {
- LocalBuf -= i;
- }
}
- return (i + 1);
+ return numbytes;
#else
(void)fd;
(void)buf;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sbrk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sbrk.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c
index 7f94fabb42..64d5156afd 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sbrk.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c
similarity index 96%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c
index 508b30f617..74c7ec215e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -49,6 +49,7 @@
* disabling the interrupt
* 5.04 pkp 03/11/16 Compare the counter value to previously read value
* to detect the overflow for TTC3
+* 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899.
*
*
******************************************************************************/
@@ -79,7 +80,7 @@
*
****************************************************************************/
-s32 sleep(u32 seconds)
+unsigned sleep(unsigned int seconds)
{
#ifdef SLEEP_TIMER_BASEADDR
u64 tEnd;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h
similarity index 92%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h
index 9b49173c62..27add66057 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -29,18 +29,19 @@
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
+
#ifndef SLEEP_H
#define SLEEP_H
+#include "xil_types.h"
+#include "xil_io.h"
+
#ifdef __cplusplus
extern "C" {
#endif
-#include "xil_types.h"
-#include "xil_io.h"
-
-s32 usleep(u32 useconds);
-s32 sleep(u32 seconds);
+int usleep(unsigned long useconds);
+unsigned sleep(unsigned int seconds);
#ifdef __cplusplus
}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/uart.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/uart.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/uart.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/uart.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/unlink.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c
similarity index 96%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/unlink.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c
index 0c9f0f78e1..84e44a47c5 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/unlink.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/usleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c
similarity index 96%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/usleep.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c
index afc9414bb3..ff01dfd73a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/usleep.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -50,6 +50,7 @@
* disabling the interrupt
* 5.04 pkp 03/11/16 Compare the counter value to previously read value
* to detect the overflow for TTC3
+* 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899.
*
*
******************************************************************************/
@@ -83,7 +84,7 @@
*
****************************************************************************/
-s32 usleep(u32 useconds)
+int usleep(unsigned long useconds)
{
#ifdef SLEEP_TIMER_BASEADDR
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.c
similarity index 73%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.c
index 73162672ff..0a3616328f 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,14 +33,17 @@
/**
* @file vectors.c
*
-* This file contains the C level vectors for the ARM Cortex R5 core.
+* This file contains the C level vectors for the ARM Cortex A9 core.
*
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 02/20/14 First release
+* 1.00a ecm 10/20/09 Initial version, moved over from bsp area
+* 6.0 mus 27/07/16 Consolidated vectors for a53,a9 and r5 processor
+* and added UndefinedException for a53 32 bit and r5
+* processor
*
*
* @note
@@ -71,7 +74,6 @@ extern XExc_VectorTableEntry XExc_VectorTable[];
/************************** Function Prototypes ******************************/
-
/*****************************************************************************/
/**
*
@@ -110,6 +112,26 @@ void IRQInterrupt(void)
XIL_EXCEPTION_ID_IRQ_INT].Data);
}
+#if !defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Undefined exception called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void UndefinedException(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
+}
+
/*****************************************************************************/
/**
*
@@ -166,3 +188,44 @@ void PrefetchAbortInterrupt(void)
XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
}
+#else
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void SynchronousInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_SYNC_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SError Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void SErrorInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
+}
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.h
similarity index 87%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.h
index ad4d8ece36..bb599b5602 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -33,14 +33,15 @@
/**
* @file vectors.h
*
-* This file contains the C level vector prototypes for the ARM Cortex R5 core.
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
*
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 02/20/14 First release
+* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
+* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
*
*
* @note
@@ -49,8 +50,8 @@
*
******************************************************************************/
-#ifndef VECTORS_H_
-#define VECTORS_H_
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
/***************************** Include Files *********************************/
@@ -67,12 +68,18 @@ extern "C" {
/************************** Constant Definitions *****************************/
/************************** Function Prototypes ******************************/
+
void FIQInterrupt(void);
void IRQInterrupt(void);
+#if !defined (__aarch64__)
void SWInterrupt(void);
void DataAbortInterrupt(void);
void PrefetchAbortInterrupt(void);
-
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
#ifdef __cplusplus
}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/write.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c
similarity index 89%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/write.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c
index 4ae96c29f4..aaa879e737 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/write.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -30,19 +30,15 @@
*
******************************************************************************/
-/* Use toolchain function for openamp applications*/
-
-#ifndef UNDEFINE_FILE_OPS
-
/* write.c -- write bytes to an output device.
*/
-
-#include "xparameters.h"
+#ifndef UNDEFINE_FILE_OPS
#include "xil_printf.h"
+#include "xparameters.h"
#ifdef __cplusplus
extern "C" {
- __attribute__((weak)) s32 _write (s32 fd, char8* buf, s32 nbytes);
+ __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
}
#endif
@@ -51,8 +47,8 @@ extern "C" {
* stdout and stderr are the same. Since we have no filesystem,
* open will only return an error.
*/
-__attribute__((weak)) s32
-write (s32 fd, char8* buf, s32 nbytes)
+__attribute__((weak)) sint32
+write (sint32 fd, char8* buf, sint32 nbytes)
{
#ifdef STDOUT_BASEADDRESS
@@ -83,8 +79,8 @@ write (s32 fd, char8* buf, s32 nbytes)
#endif
}
-__attribute__((weak)) s32
-_write (s32 fd, char8* buf, s32 nbytes)
+__attribute__((weak)) sint32
+_write (sint32 fd, char8* buf, sint32 nbytes)
{
#ifdef STDOUT_BASEADDRESS
s32 i;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xbasic_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xbasic_types.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xbasic_types.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xbasic_types.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xdebug.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xdebug.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xdebug.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xdebug.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv_standalone.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv_standalone.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv_standalone.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil-crt0.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S
similarity index 86%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil-crt0.S
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S
index cca2f0d699..6715a6ce51 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil-crt0.S
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S
@@ -70,11 +70,30 @@
.Lstack:
.long __stack
+.set RPU_0_PWRCTL, 0xFF9A0108
+.set RPU_1_PWRCTL, 0xFF9A0208
+.set MPIDR_AFF0, 0xFF
+.set PWRCTL_MASK, 0x1
.globl _startup
_startup:
bl __cpu_init /* Initialize the CPU first (BSP provides this) */
+ mrc p15, 0, r0, c0, c0, 5 /* Read MPIDR register */
+ ands r0, r0, #MPIDR_AFF0 /* Get affinity level 0 */
+ bne core1
+ ldr r10, =RPU_0_PWRCTL /* Load PWRCTRL address for core 0 */
+ b test_boot_status
+
+core1:
+ ldr r10, =RPU_1_PWRCTL /* Load PWRCTRL address for core 1 */
+
+test_boot_status:
+ ldr r11, [r10] /* Read PWRCTRL register */
+ ands r11, r11, #PWRCTL_MASK /* Extract and test core's PWRCTRL */
+
+ /* if warm reset, skip the clearing of BSS and SBSS */
+ bne .Lenclbss
mov r0, #0
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c
index 42db07deb9..3087fe80fb 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -42,6 +42,7 @@
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 Initial release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
*
*
******************************************************************************/
@@ -71,7 +72,7 @@ u32 Xil_AssertStatus;
* such that it does not wait infinitely. Use the debugger to disable the
* waiting during testing of asserts.
*/
-/*s32 Xil_AssertWait = 1*/
+s32 Xil_AssertWait = 1;
/* The callback function to be invoked when an assert is taken */
static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
@@ -95,7 +96,6 @@ static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
******************************************************************************/
void Xil_Assert(const char8 *File, s32 Line)
{
- s32 Xil_AssertWait = 1;
/* if the callback has been set then invoke it */
if (Xil_AssertCallbackRoutine != 0) {
(*Xil_AssertCallbackRoutine)(File, Line);
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h
index 7034bc9ad1..1e3c17b506 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -42,6 +42,7 @@
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
*
*
******************************************************************************/
@@ -66,6 +67,7 @@ extern "C" {
#define XNULL NULL
extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
extern void Xil_Assert(const char8 *File, s32 Line);
void XNullHandler(void *NullParameter);
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c
similarity index 60%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c
index f41976eec7..66f722d925 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -34,7 +34,7 @@
*
* @file xil_exception.c
*
-* This file contains low-level driver functions for the Cortex R5 exception
+* This file contains low-level driver functions for the Cortex A53,A9,R5 exception
* Handler.
*
*
@@ -42,8 +42,10 @@
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 02/20/14 First release
-*
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5
+* processors and added Xil_UndefinedExceptionHandler
+* for a53 32 bit and r5 as well.
*
*
*****************************************************************************/
@@ -72,16 +74,34 @@ static void Xil_ExceptionNullHandler(void *Data);
/*
* Exception vector table to store handlers for each exception vector.
*/
+#if defined (__aarch64__)
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_SyncAbortHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_SErrorAbortHandler, NULL},
+
+};
+#else
XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
{
{Xil_ExceptionNullHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
+ {Xil_UndefinedExceptionHandler, NULL},
{Xil_ExceptionNullHandler, NULL},
{Xil_PrefetchAbortHandler, NULL},
{Xil_DataAbortHandler, NULL},
{Xil_ExceptionNullHandler, NULL},
{Xil_ExceptionNullHandler, NULL},
};
+#endif
+#if !defined (__aarch64__)
+u32 DataAbortAddr; /* Address of instruction causing data abort */
+u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */
+u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined
+ exception */
+#endif
/*****************************************************************************/
@@ -109,9 +129,12 @@ DieLoop: goto DieLoop;
/****************************************************************************/
/**
* The function is a common API used to initialize exception handlers across all
-* processors supported. For ARM CortexR5, the exception handlers are being
+* processors supported. For ARM CortexA53,R5,A9, the exception handlers are being
* initialized statically and hence this function does not do anything.
-*
+* However, it is still present to avoid any compilation issues in case an
+* application uses this API and also to take care of backward compatibility
+* issues (in earlier versions of BSPs, this API was being used to initialize
+* exception handlers).
*
* @param None.
*
@@ -174,12 +197,55 @@ void Xil_ExceptionRemoveHandler(u32 Exception_id)
Xil_ExceptionNullHandler,
NULL);
}
+
+#if defined (__aarch64__)
/*****************************************************************************/
/**
*
-* Default Data abort handler which prints a debug message on console if
+* Default Synchronous abort handler which prints a debug message on console if
* Debug flag is enabled
*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+
+void Xil_SyncAbortHandler(void *CallBackRef){
+ xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+ while(1) {
+ ;
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* Default SError abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_SErrorAbortHandler(void *CallBackRef){
+ xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+ while(1) {
+ ;
+ }
+}
+#else
+/*****************************************************************************/
+/**
+*
+* Default Data abort handler which prints data fault status register through
+* which information about data fault can be acquired
+*
* @param None
*
* @return None.
@@ -189,8 +255,21 @@ void Xil_ExceptionRemoveHandler(u32 Exception_id)
****************************************************************************/
void Xil_DataAbortHandler(void *CallBackRef){
+#ifdef DEBUG
+ u32 FaultStatus;
- xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
+ xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
+ #ifdef __GNUC__
+ FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
+ #elif defined (__ICCARM__)
+ mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
+ #else
+ { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
+ FaultStatus = Reg; }
+ #endif
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %x\n",FaultStatus);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Data abort %x\n",DataAbortAddr);
+#endif
while(1) {
;
}
@@ -199,8 +278,8 @@ void Xil_DataAbortHandler(void *CallBackRef){
/*****************************************************************************/
/**
*
-* Default Prefetch abort handler which printsa debug message on console if
-* Debug flag is enabled
+* Default Prefetch abort handler which prints prefetch fault status register through
+* which information about instruction prefetch fault can be acquired
*
* @param None
*
@@ -210,9 +289,43 @@ void Xil_DataAbortHandler(void *CallBackRef){
*
****************************************************************************/
void Xil_PrefetchAbortHandler(void *CallBackRef){
+#ifdef DEBUG
+ u32 FaultStatus;
- xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
+ xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
+ #ifdef __GNUC__
+ FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
+ #elif defined (__ICCARM__)
+ mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
+ #else
+ { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
+ FaultStatus = Reg; }
+ #endif
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %x\n",FaultStatus);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Prefetch abort %x\n",PrefetchAbortAddr);
+#endif
while(1) {
;
}
}
+/*****************************************************************************/
+/**
+*
+* Default undefined exception handler which prints address of the undefined
+* instruction if debug prints are enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_UndefinedExceptionHandler(void *CallBackRef){
+
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %x\n",UndefinedExceptionAddr);
+ while(1) {
+ ;
+ }
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h
similarity index 85%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h
index 9d903175cf..434ef2a6a5 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -34,7 +34,7 @@
*
* @file xil_exception.h
*
-* This header file contains ARM Cortex R5 specific exception related APIs.
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
* For exception related functions that can be used across all Xilinx supported
* processors, please use xil_exception.h.
*
@@ -43,7 +43,8 @@
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 02/20/14 First release
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
*
*
******************************************************************************/
@@ -67,6 +68,13 @@ extern "C" {
#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
#define XIL_EXCEPTION_ID_FIRST 0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT 1U
+#define XIL_EXCEPTION_ID_IRQ_INT 2U
+#define XIL_EXCEPTION_ID_FIQ_INT 3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_LAST 5U
+#else
#define XIL_EXCEPTION_ID_RESET 0U
#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
#define XIL_EXCEPTION_ID_SWI_INT 2U
@@ -75,6 +83,7 @@ extern "C" {
#define XIL_EXCEPTION_ID_IRQ_INT 5U
#define XIL_EXCEPTION_ID_FIQ_INT 6U
#define XIL_EXCEPTION_ID_LAST 6U
+#endif
/*
* XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
@@ -103,10 +112,16 @@ typedef void (*Xil_InterruptHandler)(void *data);
* C-Style signature: void Xil_ExceptionEnableMask(Mask)
*
******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
#define Xil_ExceptionEnableMask(Mask) \
mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-
-
+#else
+#define Xil_ExceptionEnableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+ }
+#endif
/****************************************************************************/
/**
* Enable the IRQ exception.
@@ -131,9 +146,16 @@ typedef void (*Xil_InterruptHandler)(void *data);
* C-Style signature: Xil_ExceptionDisableMask(Mask)
*
******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
#define Xil_ExceptionDisableMask(Mask) \
mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-
+#else
+#define Xil_ExceptionDisableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+ }
+#endif
/****************************************************************************/
/**
* Disable the IRQ exception.
@@ -146,6 +168,7 @@ typedef void (*Xil_InterruptHandler)(void *data);
#define Xil_ExceptionDisable() \
Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+#if !defined (__aarch64__) && !defined (ARMA53_32)
/****************************************************************************/
/**
* Enable nested interrupts by clearing the I and F bits it CPSR
@@ -166,6 +189,7 @@ typedef void (*Xil_InterruptHandler)(void *data);
* eventual crash (all the stack space getting consumed).
******************************************************************************/
#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
__asm__ __volatile__ ("mrs lr, spsr"); \
__asm__ __volatile__ ("stmfd sp!, {lr}"); \
__asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
@@ -190,8 +214,10 @@ typedef void (*Xil_InterruptHandler)(void *data);
__asm__ __volatile__ ("ldmfd sp!, {lr}"); \
__asm__ __volatile__ ("msr cpsr_c, #0x92"); \
__asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr spsr_cxsf, lr");
+ __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+#endif
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
@@ -203,10 +229,14 @@ extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
extern void Xil_ExceptionInit(void);
-
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
extern void Xil_DataAbortHandler(void *CallBackRef);
-
extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
#ifdef __cplusplus
}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_hal.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_hal.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_hal.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_hal.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c
new file mode 100644
index 0000000000..31de055814
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c
@@ -0,0 +1,107 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures. These functions encapsulate Cortex A53 architecture-specific
+* I/O requirements.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/29/14 First release
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/*****************************************************************************/
+/**
+*
+* Perform a 16-bit endian converion.
+*
+* @param Data contains the value to be converted.
+*
+* @return converted value.
+*
+* @note None.
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+ return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 32-bit endian converion.
+*
+* @param Data contains the value to be converted.
+*
+* @return converted value.
+*
+* @note None.
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+ u16 LoWord;
+ u16 HiWord;
+
+ /* get each of the half words from the 32 bit word */
+
+ LoWord = (u16) (Data & 0x0000FFFFU);
+ HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+ /* byte swap each of the 16 bit half words */
+
+ LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+ HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+ /* swap the half words before returning the value */
+
+ return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h
similarity index 57%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h
index 90fd22559f..06d89dcc37 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -32,40 +32,69 @@
/*****************************************************************************/
/**
*
-* @file xil_io.c
+* @file xil_io.h
*
-* Contains I/O functions for memory-mapped or non-memory-mapped I/O
-* architectures. These functions encapsulate Cortex R5 architecture-specific
-* I/O requirements.
+* This file contains the interface for the general IO component, which
+* encapsulates the Input/Output functions for processors that do not
+* require any special I/O handling.
*
-* @note
-*
-* This file contains architecture-dependent code.
*
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 02/20/14 First release
+* 5.00 pkp 05/29/14 First release
+* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+* ARM processors
*
******************************************************************************/
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
/***************************** Include Files *********************************/
-#include "xil_io.h"
+
#include "xil_types.h"
-#include "xil_assert.h"
+#include "xil_printf.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
#include "xpseudo_asm.h"
-#include "xreg_cortexr5.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
+#endif
/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+# define INST_SYNC mbar(0)
+# define DATA_SYNC mbar(1)
+# else
+# define SYNCHRONIZE_IO dmb()
+# define INST_SYNC isb()
+# define DATA_SYNC dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
/*****************************************************************************/
/**
@@ -81,7 +110,7 @@
* @note None.
*
******************************************************************************/
-u8 Xil_In8(INTPTR Addr)
+static INLINE u8 Xil_In8(UINTPTR Addr)
{
return *(volatile u8 *) Addr;
}
@@ -100,7 +129,7 @@ u8 Xil_In8(INTPTR Addr)
* @note None.
*
******************************************************************************/
-u16 Xil_In16(INTPTR Addr)
+static INLINE u16 Xil_In16(UINTPTR Addr)
{
return *(volatile u16 *) Addr;
}
@@ -119,11 +148,31 @@ u16 Xil_In16(INTPTR Addr)
* @note None.
*
******************************************************************************/
-u32 Xil_In32(INTPTR Addr)
+static INLINE u32 Xil_In32(UINTPTR Addr)
{
return *(volatile u32 *) Addr;
}
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 64-bit memory location by reading the
+* specified Value to the the specified address.
+*
+* @param OutAddress contains the address to perform the output operation
+* at.
+* @param Value contains the Value to be output at the specified address.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+ return *(volatile u64 *) Addr;
+}
+
/*****************************************************************************/
/**
*
@@ -139,9 +188,9 @@ u32 Xil_In32(INTPTR Addr)
* @note None.
*
******************************************************************************/
-void Xil_Out8(INTPTR Addr, u8 Value)
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
{
- volatile u8 *LocalAddr = (u8 *)Addr;
+ volatile u8 *LocalAddr = (volatile u8 *)Addr;
*LocalAddr = Value;
}
@@ -160,9 +209,9 @@ void Xil_Out8(INTPTR Addr, u8 Value)
* @note None.
*
******************************************************************************/
-void Xil_Out16(INTPTR Addr, u16 Value)
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
{
- volatile u16 *LocalAddr = (u16 *)Addr;
+ volatile u16 *LocalAddr = (volatile u16 *)Addr;
*LocalAddr = Value;
}
@@ -181,11 +230,12 @@ void Xil_Out16(INTPTR Addr, u16 Value)
* @note None.
*
******************************************************************************/
-void Xil_Out32(INTPTR Addr, u32 Value)
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
{
- volatile u32 *LocalAddr = (u32 *)Addr;
+ volatile u32 *LocalAddr = (volatile u32 *)Addr;
*LocalAddr = Value;
}
+
/*****************************************************************************/
/**
*
@@ -201,180 +251,101 @@ void Xil_Out32(INTPTR Addr, u32 Value)
* @note None.
*
******************************************************************************/
-void Xil_Out64(INTPTR Addr, u64 Value)
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
{
- volatile u64 *LocalAddr = (u64 *)Addr;
+ volatile u64 *LocalAddr = (volatile u64 *)Addr;
*LocalAddr = Value;
}
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 64-bit memory location by reading the
-* specified Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* at.
-* @param Value contains the Value to be output at the specified address.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-u64 Xil_In64(INTPTR Addr)
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+# else
+# define Xil_In16BE Xil_In16
+# define Xil_In32BE Xil_In32
+# define Xil_Out16BE Xil_Out16
+# define Xil_Out32BE Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
{
- return *(volatile u64 *) Addr;
-}
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 16-bit memory location by reading from the
-* specified address and returning the byte-swapped Value read from that
-* address.
-*
-* @param Addr contains the address to perform the input operation
-* at.
-*
-* @return The byte-swapped Value read from the specified input address.
-*
-* @note None.
-*
-******************************************************************************/
-u16 Xil_In16BE(INTPTR Addr)
-{
- u16 temp;
- u16 result;
-
- temp = Xil_In16(Addr);
-
- result = Xil_EndianSwap16(temp);
-
- return result;
+ u16 value = Xil_In16(Addr);
+ return Xil_EndianSwap16(value);
}
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 32-bit memory location by reading from the
-* specified address and returning the byte-swapped Value read from that
-* address.
-*
-* @param Addr contains the address to perform the input operation
-* at.
-*
-* @return The byte-swapped Value read from the specified input address.
-*
-* @note None.
-*
-******************************************************************************/
-u32 Xil_In32BE(INTPTR Addr)
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
{
- u32 temp;
- u32 result;
-
- temp = Xil_In32(Addr);
-
- result = Xil_EndianSwap32(temp);
-
- return result;
+ u16 value = Xil_In32(Addr);
+ return Xil_EndianSwap32(value);
}
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 16-bit memory location by writing the
-* specified Value to the the specified address. The Value is byte-swapped
-* before being written.
-*
-* @param OutAddress contains the address to perform the output operation
-* at.
-* @param Value contains the Value to be output at the specified address.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void Xil_Out16BE(INTPTR Addr, u16 Value)
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
{
- u16 temp;
-
- temp = Xil_EndianSwap16(Value);
-
- Xil_Out16(Addr, temp);
+ Value = Xil_EndianSwap16(Value);
+ Xil_Out16(Addr, Value);
}
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 32-bit memory location by writing the
-* specified Value to the the specified address. The Value is byte-swapped
-* before being written.
-*
-* @param OutAddress contains the address to perform the output operation
-* at.
-* @param Value contains the Value to be output at the specified address.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void Xil_Out32BE(INTPTR Addr, u32 Value)
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
{
- u32 temp;
-
- temp = Xil_EndianSwap32(Value);
-
- Xil_Out32(Addr, temp);
+ Value = Xil_EndianSwap32(Value);
+ Xil_Out32(Addr, Value);
}
-/*****************************************************************************/
-/**
-*
-* Perform a 16-bit endian converion.
-*
-* @param Data contains the value to be converted.
-*
-* @return converted value.
-*
-* @note None.
-*
-******************************************************************************/
-u16 Xil_EndianSwap16(u16 Data)
-{
- return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+#ifdef __cplusplus
}
+#endif
-/*****************************************************************************/
-/**
-*
-* Perform a 32-bit endian converion.
-*
-* @param Data contains the value to be converted.
-*
-* @return converted value.
-*
-* @note None.
-*
-******************************************************************************/
-u32 Xil_EndianSwap32(u32 Data)
-{
- u16 LoWord;
- u16 HiWord;
-
- /* get each of the half words from the 32 bit word */
-
- LoWord = (u16) (Data & 0x0000FFFFU);
- HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
-
- /* byte swap each of the 16 bit half words */
-
- LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
- HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
-
- /* swap the half words before returning the value */
-
- return ((((u32)LoWord) << 16U) | (u32)HiWord);
-}
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_macroback.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_macroback.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_macroback.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_macroback.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mmu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mmu.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mmu.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mmu.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c
similarity index 81%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c
index 0f0db4fc9d..9dffed148d 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c
@@ -93,7 +93,6 @@ static void outs(const charptr lp, struct params_s *par)
static void outnum( const s32 n, const s32 base, struct params_s *par)
{
- charptr cp;
s32 negative;
s32 i;
char8 outbuf[32];
@@ -141,7 +140,61 @@ static void outnum( const s32 n, const s32 base, struct params_s *par)
}
padding( par->left_flag, par);
}
+/*---------------------------------------------------*/
+/* */
+/* This routine moves a 64-bit number to the output */
+/* buffer as directed by the padding and positioning */
+/* flags. */
+/* */
+#if defined (__aarch64__)
+static void outnum1( const s64 n, const s32 base, params_t *par)
+{
+ s32 negative;
+ s32 i;
+ char8 outbuf[64];
+ const char8 digits[] = "0123456789ABCDEF";
+ u64 num;
+ for(i = 0; i<64; i++) {
+ outbuf[i] = '0';
+ }
+ /* Check if number is negative */
+ if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+ negative = 1;
+ num =(-(n));
+ }
+ else{
+ num = (n);
+ negative = 0;
+ }
+
+ /* Build number (backwards) in outbuf */
+ i = 0;
+ do {
+ outbuf[i] = digits[(num % base)];
+ i++;
+ num /= base;
+ } while (num > 0);
+
+ if (negative != 0) {
+ outbuf[i] = '-';
+ i++;
+ }
+
+ outbuf[i] = 0;
+ i--;
+
+ /* Move the converted number to the buffer and */
+ /* add in the padding where needed. */
+ par->len = (s32)strlen(outbuf);
+ padding( !(par->left_flag), par);
+ while (&outbuf[i] >= outbuf) {
+ outbyte( outbuf[i] );
+ i--;
+}
+ padding( par->left_flag, par);
+}
+#endif
/*---------------------------------------------------*/
/* */
/* This routine gets a number from the format */
@@ -189,7 +242,9 @@ static s32 getnum( charptr* linep)
void xil_printf( const char8 *ctrl1, ...)
{
s32 Check;
+#if defined (__aarch64__)
s32 long_flag;
+#endif
s32 dot_flag;
params_t par;
@@ -214,7 +269,9 @@ void xil_printf( const char8 *ctrl1, ...)
/* initialize all the flags for this format. */
dot_flag = 0;
+#if defined (__aarch64__)
long_flag = 0;
+#endif
par.unsigned_flag = 0;
par.left_flag = 0;
par.do_padding = 0;
@@ -272,7 +329,9 @@ void xil_printf( const char8 *ctrl1, ...)
break;
case 'l':
+ #if defined (__aarch64__)
long_flag = 1;
+ #endif
Check = 0;
break;
@@ -281,19 +340,38 @@ void xil_printf( const char8 *ctrl1, ...)
/* fall through */
case 'i':
case 'd':
- if ((long_flag != 0) || (ch == 'D')) {
- outnum( va_arg(argp, s32), 10L, &par);
+ #if defined (__aarch64__)
+ if (long_flag != 0){
+ outnum1((s64)va_arg(argp, s64), 10L, &par);
}
else {
outnum( va_arg(argp, s32), 10L, &par);
}
+ #else
+ outnum( va_arg(argp, s32), 10L, &par);
+ #endif
Check = 1;
break;
case 'p':
+ #if defined (__aarch64__)
+ par.unsigned_flag = 1;
+ outnum1((s64)va_arg(argp, s64), 16L, &par);
+ Check = 1;
+ break;
+ #endif
case 'X':
case 'x':
par.unsigned_flag = 1;
+ #if defined (__aarch64__)
+ if (long_flag != 0) {
+ outnum1((s64)va_arg(argp, s64), 16L, &par);
+ }
+ else {
+ outnum((s32)va_arg(argp, s32), 16L, &par);
+ }
+ #else
outnum((s32)va_arg(argp, s32), 16L, &par);
+ #endif
Check = 1;
break;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_types.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_types.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_types.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h
similarity index 82%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xparameters_ps.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h
index 91d6b64083..2f527c90ae 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xparameters_ps.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h
@@ -42,6 +42,7 @@
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 5.00 pkp 02/29/14 Initial version
+* 6.0 mus 08/18/16 Defined ARMR5 flag
*
*
* @note
@@ -53,6 +54,10 @@
#ifndef XPARAMETERS_PS_H_
#define XPARAMETERS_PS_H_
+#ifndef ARMR5
+#define ARMR5 ARMR5
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -89,10 +94,9 @@ extern "C" {
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
-#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
+#define XPAR_XWDTPS_0_INTR XPS_LPD_SWDT_INT_ID
+#define XPAR_XWDTPS_1_INTR XPS_FPD_SWDT_INT_ID
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
-#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
-#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
@@ -105,15 +109,6 @@ extern "C" {
#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
-#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID
#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID
@@ -166,28 +161,22 @@ extern "C" {
/* Shared Peripheral Interrupts (SPI) */
-
-/* FIXME */
-/*#define XPS_FPGA0_INT_ID 100U */
-#define XPS_FPGA1_INT_ID 62U
-#define XPS_FPGA2_INT_ID 63U
-#define XPS_FPGA3_INT_ID 64U
-#define XPS_FPGA4_INT_ID 65U
-#define XPS_FPGA5_INT_ID 66U
-#define XPS_FPGA6_INT_ID 67U
-#define XPS_FPGA7_INT_ID 68U
-#define XPS_DMA4_INT_ID 72U
-#define XPS_DMA5_INT_ID 73U
-#define XPS_DMA6_INT_ID 74U
-#define XPS_DMA7_INT_ID 75U
-#define XPS_FPGA8_INT_ID 84U
-#define XPS_FPGA9_INT_ID 85U
-#define XPS_FPGA10_INT_ID 86U
-#define XPS_FPGA11_INT_ID 87U
-#define XPS_FPGA12_INT_ID 88U
-#define XPS_FPGA13_INT_ID 89U
-#define XPS_FPGA14_INT_ID 90U
-#define XPS_FPGA15_INT_ID 91U
+#define XPS_FPGA0_INT_ID 121U
+#define XPS_FPGA1_INT_ID 122U
+#define XPS_FPGA2_INT_ID 123U
+#define XPS_FPGA3_INT_ID 124U
+#define XPS_FPGA4_INT_ID 125U
+#define XPS_FPGA5_INT_ID 126U
+#define XPS_FPGA6_INT_ID 127U
+#define XPS_FPGA7_INT_ID 128U
+#define XPS_FPGA8_INT_ID 136U
+#define XPS_FPGA9_INT_ID 137U
+#define XPS_FPGA10_INT_ID 138U
+#define XPS_FPGA11_INT_ID 139U
+#define XPS_FPGA12_INT_ID 140U
+#define XPS_FPGA13_INT_ID 141U
+#define XPS_FPGA14_INT_ID 142U
+#define XPS_FPGA15_INT_ID 143U
/* Updated Interrupt-IDs */
#define XPS_OCMINTR_INT_ID (10U + 32U)
@@ -204,7 +193,8 @@ extern "C" {
#define XPS_CAN1_INT_ID (24U + 32U)
#define XPS_RTC_ALARM_INT_ID (26U + 32U)
#define XPS_RTC_SEC_INT_ID (27U + 32U)
-#define XPS_WDT_INT_ID (52U + 32U)
+#define XPS_LPD_SWDT_INT_ID (52U + 32U)
+#define XPS_FPD_SWDT_INT_ID (113U + 32U)
#define XPS_TTC0_0_INT_ID (36U + 32U)
#define XPS_TTC0_1_INT_ID (37U + 32U)
#define XPS_TTC0_2_INT_ID (38U + 32U)
@@ -257,33 +247,6 @@ extern "C" {
#define XPS_APM5_INT_ID (123U + 32U)
/* REDEFINES for TEST APP */
-/* Definitions for UART */
-#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
-#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
-#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
-#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
-#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
-#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
-#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
-#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
-#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
-#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
-#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
-#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
-#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
-#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_2_INTR XPS_GEM2_INT_ID
-#define XPAR_PS7_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_3_INTR XPS_GEM3_INT_ID
-#define XPAR_PS7_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
-
-#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
-#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
-#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
-#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
-#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
-
#define XPAR_PSU_UART_0_INTR XPS_UART0_INT_ID
#define XPAR_PSU_UART_1_INTR XPS_UART1_INT_ID
#define XPAR_PSU_USB_0_INTR XPS_USB0_INT_ID
@@ -304,9 +267,8 @@ extern "C" {
#define XPAR_PSU_ETHERNET_3_INTR XPS_GEM3_INT_ID
#define XPAR_PSU_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_PSU_QSPI_0_INTR XPS_QSPI_INT_ID
-#define XPAR_PSU_WDT_0_INTR XPS_WDT_INT_ID
-#define XPAR_PSU_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
-#define XPAR_PSU_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_PSU_WDT_0_INTR XPS_LPD_SWDT_INT_ID
+#define XPAR_PSU_WDT_1_INTR XPS_FPD_SWDT_INT_ID
#define XPAR_PSU_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PSU_TTC_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_PSU_TTC_1_INTR XPS_TTC0_1_INT_ID
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c
index fea992e40d..9d4560a987 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c
@@ -44,6 +44,7 @@
* 5.00 pkp 12/15/14 Initial release
* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit
* mode
+* 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info
*
*
******************************************************************************/
@@ -51,6 +52,7 @@
/***************************** Include Files *********************************/
#include "xil_types.h"
+#include "xil_io.h"
#include "xplatform_info.h"
/************************** Constant Definitions *****************************/
@@ -78,7 +80,7 @@
******************************************************************************/
u32 XGetPlatform_Info()
{
- u32 reg;
+
#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
return XPLAT_ZYNQ_ULTRA_MP;
#elif (__microblaze__)
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
similarity index 71%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
index 2b382acb88..b475c90e79 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -42,7 +42,8 @@
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
+* 5.00 pkp 05/21/14 First release
+* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
*
*
******************************************************************************/
@@ -53,6 +54,7 @@
/***************************** Include Files ********************************/
#include "xil_types.h"
+
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
@@ -67,6 +69,59 @@ extern "C" {
#define stringify(s) tostring(s)
#define tostring(s) #s
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval; \
+ asm volatile("mrs %0, DAIF" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei() //__asm__ __volatile__("cpsie i\n")
+#define cpsidi() //__asm__ __volatile__("cpsid i\n")
+
+#define cpsief() //__asm__ __volatile__("cpsie f\n")
+#define cpsidf() //__asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) /*__asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )*/
+
+#define mfgpr(rn) /*({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u64 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#else
+
/* pseudo assembler instructions */
#define mfcpsr() ({u32 rval; \
__asm__ __volatile__(\
@@ -123,6 +178,8 @@ extern "C" {
rval;\
})
+#endif
+
#define ldrb(adr) ({u8 rval; \
__asm__ __volatile__(\
"ldrb %0,[%1]"\
@@ -150,6 +207,22 @@ extern "C" {
rval;\
})
+#if defined (__aarch64__)
+#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
+#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
+
+#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg) ({u64 rval;\
+ __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
+
+#else
/* CP15 operations */
#define mtcp(rn, v) __asm__ __volatile__(\
"mcr " rn "\n"\
@@ -163,6 +236,7 @@ extern "C" {
);\
rval;\
})
+#endif
/************************** Variable Definitions ****************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xreg_cortexr5.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xreg_cortexr5.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xreg_cortexr5.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xreg_cortexr5.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xstatus.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h
similarity index 98%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xstatus.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h
index ba5f96b208..4873e85eb6 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xstatus.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -303,6 +303,8 @@ extern "C" {
#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE 1163 /* controller completed polling the
+ device for status */
/********************** OPB Arbiter statuses 1176 - 1200 *********************/
@@ -416,7 +418,7 @@ extern "C" {
/**************************** Type Definitions *******************************/
-typedef int XStatus;
+typedef s32 XStatus;
/***************** Macros (Inline Functions) Definitions *********************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c
similarity index 88%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c
index a17ee404b3..a9db4df7fb 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -52,6 +52,9 @@
* are modified to read and write TTC counter value
* respectively
* 5.04 pkp
+* 6.0 mus 08/11/16 Removed implementation of XTime_SetTime API, since
+* TTC counter value register is read only.
+*
*
*
* @note None.
@@ -63,6 +66,7 @@
#include "xpseudo_asm.h"
#include "xil_assert.h"
#include "xil_io.h"
+#include "xdebug.h"
/***************** Macros (Inline Functions) Definitions *********************/
@@ -148,24 +152,9 @@ void XTime_StartTimer(void)
****************************************************************************/
void XTime_SetTime(XTime Xtime_Global)
{
- u32 TimerCntrl;
- /* Disable the timer to configure */
- TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
- SLEEP_TIMER_CNTR_CNTRL_OFFSET);
- TimerCntrl = TimerCntrl | SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK;
- Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
- TimerCntrl);
-
- /* Write the lower 32bit value to timer counter register */
- Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_VAL_OFFSET,
- Xtime_Global);
-
- /* Enable the Timer */
- TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
- SLEEP_TIMER_CNTR_CNTRL_OFFSET);
- TimerCntrl = TimerCntrl & (~SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK);
- Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
- TimerCntrl);
+/*Timer cannot be set to desired value, so the API is left unimplemented*/
+ xdbg_printf(XDBG_DEBUG_GENERAL,
+ "XTime_SetTime:Timer cannot be set to desired value,so API is not implemented\n");
}
/****************************************************************************
@@ -184,4 +173,4 @@ void XTime_GetTime(XTime *Xtime_Global)
*Xtime_Global = Xil_In32(SLEEP_TIMER_BASEADDR +
SLEEP_TIMER_CNTR_VAL_OFFSET);
}
-#endif
\ No newline at end of file
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/Makefile
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/Makefile
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c
similarity index 93%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c
index a30a257fb1..b047a4599f 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c
@@ -51,6 +51,16 @@
* 03/03/16 Added Temperature remote channel for Setsingle
* channel API. Also corrected external mux channel
* numbers.
+* 1.1 kvn 05/05/16 Modified code for MISRA-C:2012 Compliance.
+* 2.0 vns 08/14/16 Fixed CR #956780, added support for enabling/disabling
+* SEQ_CH2 and SEQ_AVG2 registers, modified function
+* prototypes of XSysMonPsu_GetSeqAvgEnables,
+* XSysMonPsu_SetSeqAvgEnables, XSysMonPsu_SetSeqChEnables,
+* XSysMonPsu_GetSeqChEnables,
+* XSysMonPsu_SetSeqInputMode, XSysMonPsu_GetSeqInputMode,
+* XSysMonPsu_SetSeqAcqTime
+* and XSysMonPsu_GetSeqAcqTime to provide support for
+* set/get 64 bit value.
*
*
*
@@ -148,7 +158,6 @@ s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigP
* function will be called.
*
* @param CallBackRef is unused by this function.
-* @param Event is unused by this function.
*
* @return None.
*
@@ -575,11 +584,6 @@ s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
(IsDifferentialMode == FALSE));
Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
- /* Calculate the effective baseaddress based on the Sysmon instance. */
- EffectiveBaseAddress =
- XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
- SysmonBlk);
-
/* Check if the device is in single channel mode else return failure */
if ((XSysMonPsu_GetSequencerMode(InstancePtr, SysmonBlk)
!= XSM_SEQ_MODE_SINGCHAN)) {
@@ -587,6 +591,11 @@ s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
goto End;
}
+ /* Calculate the effective baseaddress based on the Sysmon instance. */
+ EffectiveBaseAddress =
+ XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+ SysmonBlk);
+
/* Read the Configuration Register 0 and extract out Averaging value. */
RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
XSYSMONPSU_CFG_REG0_OFFSET) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK;
@@ -653,10 +662,11 @@ End:
*
* @param InstancePtr is a pointer to the XSysMonPsu instance.
* @param AlmEnableMask is the bit-mask of the alarm outputs to be enabled
-* in the Configuration Register 1.
+* in the Configuration Registers 1 and 3.
* Bit positions of 1 will be enabled. Bit positions of 0 will be
* disabled. This mask is formed by OR'ing XSYSMONPSU_CFR_REG1_ALRM_*_MASK
-* masks defined in xsysmonpsu.h.
+* masks defined in xsysmonpsu.h, but XSM_CFR_ALM_SUPPLY8_MASK to
+* XSM_CFR_ALM_SUPPLY13_MASK are applicable only for PS.
* @param SysmonBlk is the value that tells whether it is for PS Sysmon
* block or PL Sysmon block register region.
*
@@ -668,6 +678,7 @@ End:
* The alarm outputs specified by the AlmEnableMask are negated
* before writing to the Configuration Register 1 because it
* was Disable register bits.
+* Upper 16 bits of AlmEnableMask are applicable only for PS.
*
*****************************************************************************/
void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
@@ -679,7 +690,9 @@ void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
/* Assert the arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(AlmEnableMask <= XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
+ Xil_AssertVoid(AlmEnableMask <=
+ (XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK |
+ (XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK << XSM_CFG_ALARM_SHIFT)));
Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
/* Calculate the effective baseaddress based on the Sysmon instance. */
@@ -698,6 +711,16 @@ void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
*/
XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG1_OFFSET,
RegValue);
+ /* Upper 16 bits of AlmEnableMask are valid only for PS */
+ if (SysmonBlk == XSYSMON_PS) {
+ RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+ XSYSMONPSU_CFG_REG3_OFFSET);
+ RegValue &= (u32)(~XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
+ RegValue |= (~(AlmEnableMask >> XSM_CFG_ALARM_SHIFT) &
+ (u32)XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
+ XSysmonPsu_WriteReg(EffectiveBaseAddress +
+ XSYSMONPSU_CFG_REG3_OFFSET, RegValue);
+ }
}
/****************************************************************************/
@@ -723,13 +746,15 @@ void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
* be disabled and alarms for bit positions of 0 will be enabled.
* The enabled alarm outputs returned by this function is the
* negated value of the the data read from the Configuration
-* Register 1.
+* Register 1. Upper 16 bits of return value are valid only if the
+* channel selected is PS.
*
*****************************************************************************/
u32 XSysMonPsu_GetAlarmEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
u32 RegValue;
u32 EffectiveBaseAddress;
+ u32 ReadReg;
/* Assert the arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
@@ -749,6 +774,13 @@ u32 XSysMonPsu_GetAlarmEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
XSYSMONPSU_CFG_REG1_OFFSET) & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK;
RegValue = (~RegValue & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
+ if (SysmonBlk == XSYSMON_PS) {
+ ReadReg = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+ XSYSMONPSU_CFG_REG3_OFFSET) & XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK;
+ ReadReg = (~ReadReg & XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
+ RegValue |= ReadReg << XSM_CFG_ALARM_SHIFT;
+ }
+
return RegValue;
}
@@ -1143,7 +1175,7 @@ u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* Use XSYSMONPSU_SEQ_CH* defined in xsysmon_hw.h to specify the Channel
* numbers. Bit masks of 1 will be enabled and bit mask of 0 will
* be disabled.
-* The ChEnableMask is a 32 bit mask that is written to the two
+* The ChEnableMask is a 64 bit mask that is written to the three
* 16 bit ADC Channel Selection Sequencer Registers.
* @param SysmonBlk is the value that tells whether it is for PS Sysmon
* block or PL Sysmon block register region.
@@ -1156,7 +1188,7 @@ u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* @note None.
*
*****************************************************************************/
-s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u32 ChEnableMask,
+s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask,
u32 SysmonBlk)
{
s32 Status;
@@ -1193,6 +1225,10 @@ s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u32 ChEnableMask,
(ChEnableMask >> XSM_SEQ_CH_SHIFT) &
XSYSMONPSU_SEQ_CH1_VALID_MASK);
+ XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH2_OFFSET,
+ (ChEnableMask >> XSM_SEQ_CH2_SHIFT) &
+ XSYSMONPSU_SEQ_CH2_VALID_MASK);
+
Status = (s32)XST_SUCCESS;
End:
@@ -1219,9 +1255,9 @@ End:
* @note None.
*
*****************************************************************************/
-u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+u64 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
- u32 RegVal;
+ u64 RegVal;
u32 EffectiveBaseAddress;
/* Assert the arguments. */
@@ -1243,6 +1279,9 @@ u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
XSYSMONPSU_SEQ_CH1_OFFSET) & XSYSMONPSU_SEQ_CH1_VALID_MASK) <<
XSM_SEQ_CH_SHIFT;
+ RegVal |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_CH2_OFFSET) &
+ XSYSMONPSU_SEQ_CH2_VALID_MASK) << XSM_SEQ_CH2_SHIFT;
return RegVal;
}
@@ -1259,8 +1298,8 @@ u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* averaging is to be enabled. Use XSYSMONPSU_SEQ_AVERAGE* defined in
* xsysmonpsu_hw.h to specify the Channel numbers. Averaging will be
* enabled for bit masks of 1 and disabled for bit mask of 0.
-* The AvgEnableChMask is a 32 bit mask that is written to the
-* two 16 bit ADC Channel Averaging Enable Sequencer Registers.
+* The AvgEnableChMask is a 64 bit mask that is written to the
+* three 16 bit ADC Channel Averaging Enable Sequencer Registers.
* @param SysmonBlk is the value that tells whether it is for PS Sysmon
* block or PL Sysmon block register region.
*
@@ -1272,7 +1311,7 @@ u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* @note None.
*
*****************************************************************************/
-s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
+s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u64 AvgEnableChMask,
u32 SysmonBlk)
{
s32 Status;
@@ -1283,11 +1322,6 @@ s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
- /* Calculate the effective baseaddress based on the Sysmon instance. */
- EffectiveBaseAddress =
- XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
- SysmonBlk);
-
/*
* The sequencer must be disabled for writing any of these registers.
* Return XST_FAILURE if the channel sequencer is enabled.
@@ -1295,24 +1329,32 @@ s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
!= XSM_SEQ_MODE_SAFE)) {
Status = (s32)XST_FAILURE;
- goto End;
+ } else {
+ /* Calculate the effective baseaddress based on the Sysmon instance. */
+ EffectiveBaseAddress =
+ XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+ SysmonBlk);
+ /*
+ * Enable/disable the averaging for the specified channels in the
+ * ADC Channel Averaging Enables Sequencer Registers.
+ */
+ XSysmonPsu_WriteReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_AVERAGE0_OFFSET,
+ (AvgEnableChMask & XSYSMONPSU_SEQ_AVERAGE0_MASK));
+
+ XSysmonPsu_WriteReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_AVERAGE1_OFFSET,
+ (AvgEnableChMask >> XSM_SEQ_CH_SHIFT) &
+ XSYSMONPSU_SEQ_AVERAGE1_MASK);
+
+ XSysmonPsu_WriteReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_AVERAGE2_OFFSET,
+ (AvgEnableChMask >> XSM_SEQ_CH2_SHIFT) &
+ XSYSMONPSU_SEQ_AVERAGE2_MASK);
+
+ Status = (s32)XST_SUCCESS;
}
- /*
- * Enable/disable the averaging for the specified channels in the
- * ADC Channel Averaging Enables Sequencer Registers.
- */
- XSysmonPsu_WriteReg(EffectiveBaseAddress +
- XSYSMONPSU_SEQ_AVERAGE0_OFFSET,
- (AvgEnableChMask & XSYSMONPSU_SEQ_AVERAGE0_MASK));
-
- XSysmonPsu_WriteReg(EffectiveBaseAddress +
- XSYSMONPSU_SEQ_AVERAGE1_OFFSET,
- (AvgEnableChMask >> XSM_SEQ_CH_SHIFT) &
- XSYSMONPSU_SEQ_AVERAGE1_MASK);
-
- Status = (s32)XST_SUCCESS;
-End:
return Status;
}
@@ -1335,9 +1377,9 @@ End:
* @note None.
*
*****************************************************************************/
-u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+u64 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
- u32 RegVal;
+ u64 RegVal;
u32 EffectiveBaseAddress;
/* Assert the arguments. */
@@ -1359,6 +1401,9 @@ u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
XSYSMONPSU_SEQ_AVERAGE1_OFFSET) & XSYSMONPSU_SEQ_AVERAGE1_MASK) <<
XSM_SEQ_CH_SHIFT;
+ RegVal |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_AVERAGE2_OFFSET) &
+ XSYSMONPSU_SEQ_AVERAGE2_MASK) << XSM_SEQ_CH2_SHIFT;
return RegVal;
}
@@ -1376,7 +1421,7 @@ u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* defined in xsysmonpsu_hw.h to specify the channel numbers. Differential
* or Bipolar input mode will be set for bit masks of 1 and unipolar input
* mode for bit masks of 0.
-* The InputModeChMask is a 32 bit mask that is written to the two
+* The InputModeChMask is a 64 bit mask that is written to the three
* 16 bit ADC Channel Analog-Input Mode Sequencer Registers.
* @param SysmonBlk is the value that tells whether it is for PS Sysmon
* block or PL Sysmon block register region.
@@ -1389,7 +1434,7 @@ u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* @note None.
*
*****************************************************************************/
-s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u32 InputModeChMask,
+s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u64 InputModeChMask,
u32 SysmonBlk)
{
s32 Status;
@@ -1429,6 +1474,11 @@ s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u32 InputModeChMask,
(InputModeChMask >> XSM_SEQ_CH_SHIFT) &
XSYSMONPSU_SEQ_INPUT_MDE1_MASK);
+ XSysmonPsu_WriteReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET,
+ (InputModeChMask >> XSM_SEQ_CH2_SHIFT) &
+ XSYSMONPSU_SEQ_INPUT_MDE2_MASK);
+
Status = (s32)XST_SUCCESS;
End:
@@ -1454,9 +1504,9 @@ End:
* @note None.
*
*****************************************************************************/
-u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+u64 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
- u32 InputMode;
+ u64 InputMode;
u32 EffectiveBaseAddress;
/* Assert the arguments. */
@@ -1478,6 +1528,9 @@ u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
InputMode |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET) & XSYSMONPSU_SEQ_INPUT_MDE1_MASK) <<
XSM_SEQ_CH_SHIFT;
+ InputMode |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET) &
+ XSYSMONPSU_SEQ_INPUT_MDE2_MASK) << XSM_SEQ_CH2_SHIFT;
return InputMode;
}
@@ -1496,7 +1549,7 @@ u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
* for bit masks of 1 and will be the default 4 ADCCLK cycles for
* bit masks of 0.
-* The AcqCyclesChMask is a 32 bit mask that is written to the two
+* The AcqCyclesChMask is a 64 bit mask that is written to the three
* 16 bit ADC Channel Acquisition Time Sequencer Registers.
* @param SysmonBlk is the value that tells whether it is for PS Sysmon
* block or PL Sysmon block register region.
@@ -1509,7 +1562,7 @@ u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
* @note None.
*
*****************************************************************************/
-s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u32 AcqCyclesChMask,
+s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u64 AcqCyclesChMask,
u32 SysmonBlk)
{
s32 Status;
@@ -1546,6 +1599,10 @@ s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u32 AcqCyclesChMask,
XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ1_OFFSET,
(AcqCyclesChMask >> XSM_SEQ_CH_SHIFT) & XSYSMONPSU_SEQ_ACQ1_MASK);
+ XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ2_OFFSET,
+ (AcqCyclesChMask >> XSM_SEQ_CH2_SHIFT) &
+ XSYSMONPSU_SEQ_ACQ2_MASK);
+
Status = (s32)XST_SUCCESS;
End:
@@ -1571,9 +1628,9 @@ End:
* @note None.
*
*****************************************************************************/
-u32 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+u64 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
- u32 RegValAcq;
+ u64 RegValAcq;
u32 EffectiveBaseAddress;
/* Assert the arguments. */
@@ -1595,6 +1652,9 @@ u32 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk)
RegValAcq |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
XSYSMONPSU_SEQ_ACQ1_OFFSET) & XSYSMONPSU_SEQ_ACQ1_MASK) <<
XSM_SEQ_CH_SHIFT;
+ RegValAcq |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+ XSYSMONPSU_SEQ_ACQ2_OFFSET) &
+ XSYSMONPSU_SEQ_ACQ2_MASK) << XSM_SEQ_CH2_SHIFT;
return RegValAcq;
}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h
similarity index 92%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h
index ae55db9ce6..ba090c5aa8 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h
@@ -151,6 +151,18 @@
* 03/03/16 Added Temperature remote channel for Setsingle
* channel API. Also corrected external mux channel
* numbers.
+* 1.1 kvn 05/05/16 Modified code for MISRA-C:2012 Compliance.
+* 2.0 vns 08/14/16 Fixed CR #956780, added support for enabling/disabling
+* SEQ_CH2 and SEQ_AVG2 registers, modified function
+* prototypes of XSysMonPsu_GetSeqAvgEnables,
+* XSysMonPsu_SetSeqAvgEnables, XSysMonPsu_SetSeqChEnables,
+* XSysMonPsu_GetSeqChEnables,
+* XSysMonPsu_SetSeqInputMode, XSysMonPsu_GetSeqInputMode,
+* XSysMonPsu_SetSeqAcqTime
+* and XSysMonPsu_GetSeqAcqTime to provide support for
+* set/get 64 bit value.
+* Added constants XSM_CFR_ALM_SUPPLY*(8-31)_MASKs to
+* provide support for enabling extra PS alarams.
*
*
*
@@ -332,6 +344,12 @@ extern "C" {
* @name Alarm masks for channels in Configuration registers 1
* @{
*/
+#define XSM_CFR_ALM_SUPPLY13_MASK 0x200000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY12_MASK 0x100000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY11_MASK 0x080000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY10_MASK 0x040000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY9_MASK 0x020000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY8_MASK 0x010000 /**< Alarm 6 - SUPPLY6 */
#define XSM_CFR_ALM_SUPPLY6_MASK 0x0800 /**< Alarm 6 - SUPPLY6 */
#define XSM_CFR_ALM_SUPPLY5_MASK 0x0400 /**< Alarm 5 - SUPPLY5 */
#define XSM_CFR_ALM_SUPPLY4_MASK 0x0200 /**< Alarm 4 - SUPPLY4 */
@@ -458,7 +476,7 @@ typedef struct {
*
*****************************************************************************/
#define XSysMonPsu_TemperatureToRaw_OnChip(Temperature) \
- ((int)(((Temperature) + 273.6777f)*65536.0f*0.00199451786f))
+ ((s32)(((Temperature) + 273.6777f)*65536.0f*0.00199451786f))
/****************************************************************************/
/**
@@ -476,7 +494,7 @@ typedef struct {
*
*****************************************************************************/
#define XSysMonPsu_TemperatureToRaw_ExternalRef(Temperature) \
- ((int)(((Temperature) + 273.8195f)*65536.0f*0.00198842814f))
+ ((s32)(((Temperature) + 273.8195f)*65536.0f*0.00198842814f))
/****************************************************************************/
/**
@@ -534,7 +552,7 @@ void XSysMonPsu_Reset(XSysMonPsu *InstancePtr);
void XSysMonPsu_Reset_FromLPD(XSysMonPsu *InstancePtr);
u32 XSysMonPsu_GetStatus(XSysMonPsu *InstancePtr, u32 SysmonBlk);
void XSysMonPsu_StartAdcConversion(XSysMonPsu *InstancePtr);
-u16 XSysMonPsu_GetAdcData(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk);
+u16 XSysMonPsu_GetAdcData(XSysMonPsu *InstancePtr, u8 Channel, u32 Block);
u16 XSysMonPsu_GetCalibCoefficient(XSysMonPsu *InstancePtr, u8 CoeffType, u32 SysmonBlk);
u16 XSysMonPsu_GetMinMaxMeasurement(XSysMonPsu *InstancePtr, u8 MeasurementType,
u32 SysmonBlk);
@@ -556,18 +574,18 @@ void XSysMonPsu_SetExtenalMux(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk
u32 XSysMonPsu_GetExtenalMux(XSysMonPsu *InstancePtr, u32 SysmonBlk);
void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor, u32 SysmonBlk);
u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u32 ChEnableMask,
+s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask,
u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
+u64 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+u64 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u64 AvgEnableChMask,
u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u32 InputModeChMask,
+s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u64 InputModeChMask,
u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u32 AcqCyclesChMask,
+u64 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u64 AcqCyclesChMask,
u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+u64 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk);
void XSysMonPsu_SetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
u16 Value, u32 SysmonBlk);
u16 XSysMonPsu_GetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c
similarity index 94%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c
index ace39e369e..b692531ad0 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h
index 3012bf327f..80266ebf98 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h
@@ -44,6 +44,8 @@
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.0 kvn 12/15/15 First release
+* 2.0 vns 08/14/16 Added CFG_REG3, SEQ_INPUT_MODE2, SEQ_ACQ2,
+* SEQ_CH2 and SEQ_AVG2 offsets and bit masks
*
*
*
@@ -1563,6 +1565,40 @@ extern "C" {
#define XSYSMONPSU_CFG_REG2_TST_MDE_WIDTH 2U
#define XSYSMONPSU_CFG_REG2_TST_MDE_MASK 0x00000003U
+/* Register: XSysmonPsuCfgReg3 */
+#define XSYSMONPSU_CFG_REG3_OFFSET 0x0000010CU
+#define XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK 0x0000003FU
+
+#define XSM_CFG_ALARM_SHIFT 16U
+
+/* Register: XSysmonPsuSeqCh2 */
+#define XSYSMONPSU_SEQ_CH2_OFFSET 0x00000118U
+
+#define XSYSMONPSU_SEQ_CH2_TEMP_RMT_SHIFT 5U
+#define XSYSMONPSU_SEQ_CH2_TEMP_RMT_MASK 0x00000020U
+
+#define XSYSMONPSU_SEQ_CH2_VCCAMS_SHIFT 4U
+#define XSYSMONPSU_SEQ_CH2_VCCAMS_MASK 0x00000010U
+
+#define XSYSMONPSU_SEQ_CH2_SUP10_SHIFT 3U
+#define XSYSMONPSU_SEQ_CH2_SUP10_MASK 0x00000008U
+
+#define XSYSMONPSU_SEQ_CH2_SUP9_SHIFT 2U
+#define XSYSMONPSU_SEQ_CH2_SUP9_MASK 0x00000004U
+
+#define XSYSMONPSU_SEQ_CH2_SUP8_SHIFT 1U
+#define XSYSMONPSU_SEQ_CH2_SUP8_MASK 0x00000002U
+
+#define XSYSMONPSU_SEQ_CH2_SUP7_SHIFT 0U
+#define XSYSMONPSU_SEQ_CH2_SUP7_MASK 0x00000001U
+
+#define XSYSMONPSU_SEQ_CH2_VALID_MASK 0x0000003FU
+
+/* Register: XSysmonPsuSeqAverage0 */
+#define XSYSMONPSU_SEQ_AVERAGE2_OFFSET 0x0000011CU
+#define XSYSMONPSU_SEQ_AVERAGE1_RSTVAL 0x00000000U
+#define XSYSMONPSU_SEQ_AVERAGE2_MASK 0x0000003FU
+
/**
* Register: XSysmonPsuSeqCh0
*/
@@ -1695,6 +1731,7 @@ extern "C" {
#define XSYSMONPSU_SEQ_CH1_VAUX00_MASK 0x00000001U
#define XSM_SEQ_CH_SHIFT 16U
+#define XSM_SEQ_CH2_SHIFT 32U
/**
* Register: XSysmonPsuSeqAverage0
@@ -2048,6 +2085,22 @@ extern "C" {
#define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_WIDTH 1U
#define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_MASK 0x00000001U
+/* Register: XSysmonPsuSeqInputMde2 */
+#define XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET 0x000001E0U
+#define XSYSMONPSU_SEQ_INPUT_MDE2_RSTVAL 0x00000000U
+
+#define XSYSMONPSU_SEQ_INPUT_MDE2_SHIFT 0U
+#define XSYSMONPSU_SEQ_INPUT_MDE2_MASK 0x0000003FU
+
+/**
+ * Register: XSysmonPsuSeqAcq2
+ */
+#define XSYSMONPSU_SEQ_ACQ2_OFFSET 0x000001E4U
+#define XSYSMONPSU_SEQ_ACQ2_RSTVAL 0x00000000U
+
+#define XSYSMONPSU_SEQ_ACQ2_SHIFT 0U
+#define XSYSMONPSU_SEQ_ACQ2_MASK 0x0000003FU
+
/**
* Register: XSysmonPsuSup7
*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_intr.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_selftest.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_sinit.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/Makefile
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/Makefile
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c
index 4534553f63..394262868b 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c
@@ -50,6 +50,8 @@
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.01 pkp 01/30/16 Modified XTtcPs_CfgInitialize to add XTtcps_Stop
* to stop the timer before configuring
+* 3.2 mus 10/28/16 Modified XTtcPs_CalcIntervalFromFreq to calculate
+* 32 bit interval count for zynq ultrascale+mpsoc
*
*
*
@@ -377,7 +379,7 @@ u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
*
****************************************************************************/
void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
- u16 *Interval, u8 *Prescaler)
+ XInterval *Interval, u8 *Prescaler)
{
u8 TmpPrescaler;
u32 TempValue;
@@ -396,7 +398,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
* The frequency is too high, it is too close to the input
* clock value. Use maximum values to signal caller.
*/
- *Interval = 0xFFFFU;
+ *Interval = XTTCPS_MAX_INTERVAL_COUNT;
*Prescaler = 0xFFU;
return;
}
@@ -408,7 +410,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
/*
* We do not need a prescaler, so set the values appropriately
*/
- *Interval = (u16)TempValue;
+ *Interval = (XInterval)TempValue;
*Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
return;
}
@@ -425,7 +427,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
/*
* Set the values appropriately
*/
- *Interval = (u16)TempValue;
+ *Interval = (XInterval)TempValue;
*Prescaler = TmpPrescaler;
return;
}
@@ -434,7 +436,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
/* Can not find interval values that work for the given frequency.
* Return maximum values to signal caller.
*/
- *Interval = 0XFFFFU;
+ *Interval = XTTCPS_MAX_INTERVAL_COUNT;
*Prescaler = 0XFFU;
return;
}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h
similarity index 89%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h
index 646d24db5d..be266d9b3e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h
@@ -91,6 +91,8 @@
* 2.0 adk 12/10/13 Updated as per the New Tcl API's
* 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also code
* modified for MISRA-C:2012 compliance.
+* 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
+* macros to return 32 bit values for zynq ultrascale+mpsoc
*
*
******************************************************************************/
@@ -108,6 +110,21 @@ extern "C" {
#include "xstatus.h"
/************************** Constant Definitions *****************************/
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
+
+/*
+ * Maximum Value for interval counter
+ */
+ #if defined(ARMA9)
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
+ #else
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
+ #endif
/** @name Configuration options
*
@@ -125,7 +142,6 @@ extern "C" {
#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
/*@}*/
-
/**************************** Type Definitions *******************************/
/**
@@ -148,7 +164,14 @@ typedef struct {
u32 IsReady; /**< Device is initialized and ready */
} XTtcPs;
-
+/**
+ * This typedef contains interval count
+ */
+#if defined(ARMA9)
+typedef u16 XInterval;
+#else
+typedef u32 XInterval;
+#endif
/***************** Macros (Inline Functions) Definitions *********************/
/*
@@ -223,14 +246,27 @@ typedef struct {
*
* @param InstancePtr is a pointer to the XTtcPs instance.
*
-* @return 16-bit counter value.
+* @return zynq:16 bit counter value.
+* zynq ultrascale+mpsoc:32 bit counter value.
*
* @note C-style signature:
-* u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+* zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+* zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
*
****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit counter for zynq
+ */
#define XTtcPs_GetCounterValue(InstancePtr) \
(u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#else
+/*
+ * ttc supports 32 bit counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#endif
/*****************************************************************************/
/**
@@ -256,15 +292,27 @@ typedef struct {
*
* @param InstancePtr is a pointer to the XTtcPs instance.
*
-* @return 16-bit interval value
+* @return zynq:16 bit interval value.
+* zynq ultrascale+mpsoc:32 bit interval value.
*
* @note C-style signature:
-* u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+* zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+* zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
*
****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit interval counter for zynq
+ */
#define XTtcPs_GetInterval(InstancePtr) \
(u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
-
+#else
+/*
+ * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#endif
/*****************************************************************************/
/**
*
@@ -391,7 +439,7 @@ void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
- u16 *Interval, u8 *Prescaler);
+ XInterval *Interval, u8 *Prescaler);
/*
* Functions for options, in file xttcps_options.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c
similarity index 94%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_g.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c
index 10c16eb024..28d3560923 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_hw.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_hw.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_hw.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_options.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_options.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_options.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/Makefile
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/Makefile
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h
index 6bd42b21cc..d915917bb7 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h
@@ -161,6 +161,7 @@
* platform variable in driver instance structure.
* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
* uart is connected to a valid interrupt controller CR#946803.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
*
*
*
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c
similarity index 94%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c
index 94aaf5b2e4..d4a8e5ab95 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_intr.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c
index 849cb48dbf..3068ee7956 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_intr.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c
@@ -249,7 +249,7 @@ void XUartPs_InterruptHandler(XUartPs *InstancePtr)
*****************************************************************************/
static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
{
- u32 ByteStatusValue, EventData;
+ u32 EventData;
u32 Event;
InstancePtr->is_rxbs_error = 0;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_options.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c
index 7051d07eca..9a699afa1f 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_options.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c
@@ -47,6 +47,7 @@
* 1.00 sdm 09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
* value was not being written to the register.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
*
*
*
@@ -199,6 +200,8 @@ void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
* the register.
*/
if ((Options & OptionsTable[Index].Option) != (u16)0) {
+ if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK)
+ Register &= ~XUARTPS_CR_STOPBRK;
Register |= OptionsTable[Index].Mask;
}
else {
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_selftest.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_selftest.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_selftest.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_sinit.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_sinit.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/Makefile
new file mode 100644
index 0000000000..d306488148
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xusbps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling usbpsu"
+
+xusbps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xusbps_includes
+
+xusbps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c
new file mode 100644
index 0000000000..c39d11a2ff
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c
@@ -0,0 +1,906 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.0 sg 06/16/16 First release
+* 1.1 sg 10/24/16 Added new function XUsbPsu_IsSuperSpeed
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* Waits until a bit in a register is cleared or timeout occurs
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param Offset is register offset.
+* @param BitMask is bit mask of required bit to be checked.
+* @param Timeout is the time to wait specified in micro seconds.
+*
+* @return
+* - XST_SUCCESS when bit is cleared.
+* - XST_FAILURE when timed out.
+*
+******************************************************************************/
+s32 XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+ u32 BitMask, u32 Timeout)
+{
+ u32 RegVal;
+ u32 LocalTimeout = Timeout;
+
+ do {
+ RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
+ if ((RegVal & BitMask) == 0U) {
+ break;
+ }
+ LocalTimeout--;
+ if (LocalTimeout == 0U) {
+ return XST_FAILURE;
+ }
+ XUsbSleep(1U);
+ } while (1);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Waits until a bit in a register is set or timeout occurs
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param Offset is register offset.
+* @param BitMask is bit mask of required bit to be checked.
+* @param Timeout is the time to wait specified in micro seconds.
+*
+* @return
+* - XST_SUCCESS when bit is set.
+* - XST_FAILURE when timed out.
+*
+******************************************************************************/
+s32 XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+ u32 BitMask, u32 Timeout)
+{
+ u32 RegVal;
+ u32 LocalTimeout = Timeout;
+
+ do {
+ RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
+ if ((RegVal & BitMask) != 0U) {
+ break;
+ }
+ LocalTimeout--;
+ if (LocalTimeout == 0U) {
+ return XST_FAILURE;
+ }
+ XUsbSleep(1U);
+ } while (1);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Sets mode of Core to USB Device/Host/OTG.
+*
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param Mode is mode to set
+* - XUSBPSU_GCTL_PRTCAP_OTG
+* - XUSBPSU_GCTL_PRTCAP_HOST
+* - XUSBPSU_GCTL_PRTCAP_DEVICE
+*
+* @return None
+*
+******************************************************************************/
+void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 Mode)
+{
+ u32 RegVal;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid((Mode <= XUSBPSU_GCTL_PRTCAP_OTG) &&
+ (Mode >= XUSBPSU_GCTL_PRTCAP_HOST));
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+ RegVal &= ~(XUSBPSU_GCTL_PRTCAPDIR(XUSBPSU_GCTL_PRTCAP_OTG));
+ RegVal |= XUSBPSU_GCTL_PRTCAPDIR(Mode);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Issues core PHY reset.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return None
+*
+******************************************************************************/
+void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /* Before Resetting PHY, put Core in Reset */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+ RegVal |= XUSBPSU_GCTL_CORESOFTRESET;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+
+ /* Assert USB3 PHY reset */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
+ RegVal |= XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
+
+ /* Assert USB2 PHY reset */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
+ RegVal |= XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
+
+ XUsbSleep(XUSBPSU_PHY_TIMEOUT);
+
+ /* Clear USB3 PHY reset */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
+ RegVal &= ~XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
+
+ /* Clear USB2 PHY reset */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
+ RegVal &= ~XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
+
+ XUsbSleep(XUSBPSU_PHY_TIMEOUT);
+
+ /* Take Core out of reset state after PHYS are stable*/
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+ RegVal &= ~XUSBPSU_GCTL_CORESOFTRESET;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Sets up Event buffers so that events are written by Core.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return None
+*
+******************************************************************************/
+void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr)
+{
+ struct XUsbPsu_EvtBuffer *Evt;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ Evt = &InstancePtr->Evt;
+ Evt->BuffAddr = (void *)InstancePtr->EventBuffer;
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0),
+ (UINTPTR)InstancePtr->EventBuffer);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0),
+ ((UINTPTR)(InstancePtr->EventBuffer) >> 16U) >> 16U);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0),
+ XUSBPSU_GEVNTSIZ_SIZE(sizeof(InstancePtr->EventBuffer)));
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 0);
+}
+
+/*****************************************************************************/
+/**
+* Resets Event buffer Registers to zero so that events are not written by Core.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return None
+*
+******************************************************************************/
+void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr)
+{
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0U), 0U);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0U), 0U);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0U),
+ (u32)XUSBPSU_GEVNTSIZ_INTMASK | XUSBPSU_GEVNTSIZ_SIZE(0U));
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0U), 0U);
+}
+
+/*****************************************************************************/
+/**
+* Reads data from Hardware Params Registers of Core.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param RegIndex is Register number to read
+* - XUSBPSU_GHWPARAMS0
+* - XUSBPSU_GHWPARAMS1
+* - XUSBPSU_GHWPARAMS2
+* - XUSBPSU_GHWPARAMS3
+* - XUSBPSU_GHWPARAMS4
+* - XUSBPSU_GHWPARAMS5
+* - XUSBPSU_GHWPARAMS6
+* - XUSBPSU_GHWPARAMS7
+*
+* @return One of the GHWPARAMS RegValister contents.
+*
+******************************************************************************/
+u32 XUsbPsu_ReadHwParams(struct XUsbPsu *InstancePtr, u8 RegIndex)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(RegIndex <= (u8)XUSBPSU_GHWPARAMS7);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, ((u32)XUSBPSU_GHWPARAMS0_OFFSET +
+ ((u32)RegIndex * (u32)4)));
+ return RegVal;
+}
+
+/*****************************************************************************/
+/**
+* Initializes Core.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if initialization was not successful
+*
+******************************************************************************/
+s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+ u32 Hwparams1;
+
+ /* issue device SoftReset too */
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, XUSBPSU_DCTL_CSFTRST);
+
+ if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DCTL,
+ XUSBPSU_DCTL_CSFTRST, 500U) == XST_FAILURE) {
+ /* timed out return failure */
+ return XST_FAILURE;
+ }
+
+ XUsbPsu_PhyReset(InstancePtr);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+ RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK;
+ RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE;
+ RegVal |= XUSBPSU_GCTL_U2EXIT_LFPS;
+
+ Hwparams1 = XUsbPsu_ReadHwParams(InstancePtr, 1U);
+
+ switch (XUSBPSU_GHWPARAMS1_EN_PWROPT(Hwparams1)) {
+ case XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK:
+ RegVal &= ~XUSBPSU_GCTL_DSBLCLKGTNG;
+ break;
+
+ case XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB:
+ /* enable hibernation here */
+ break;
+
+ default:
+ /* Made for Misra-C Compliance. */
+ break;
+ }
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Enables an interrupt in Event Enable RegValister.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on
+* @param Mask is the OR of any Interrupt Enable Masks:
+* - XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
+* - XUSBPSU_DEVTEN_EVNTOVERFLOWEN
+* - XUSBPSU_DEVTEN_CMDCMPLTEN
+* - XUSBPSU_DEVTEN_ERRTICERREN
+* - XUSBPSU_DEVTEN_SOFEN
+* - XUSBPSU_DEVTEN_EOPFEN
+* - XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
+* - XUSBPSU_DEVTEN_WKUPEVTEN
+* - XUSBPSU_DEVTEN_ULSTCNGEN
+* - XUSBPSU_DEVTEN_CONNECTDONEEN
+* - XUSBPSU_DEVTEN_USBRSTEN
+* - XUSBPSU_DEVTEN_DISCONNEVTEN
+*
+* @return None
+*
+******************************************************************************/
+void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
+{
+ u32 RegVal;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
+ RegVal |= Mask;
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Disables an interrupt in Event Enable RegValister.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param Mask is the OR of Interrupt Enable Masks
+* - XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
+* - XUSBPSU_DEVTEN_EVNTOVERFLOWEN
+* - XUSBPSU_DEVTEN_CMDCMPLTEN
+* - XUSBPSU_DEVTEN_ERRTICERREN
+* - XUSBPSU_DEVTEN_SOFEN
+* - XUSBPSU_DEVTEN_EOPFEN
+* - XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
+* - XUSBPSU_DEVTEN_WKUPEVTEN
+* - XUSBPSU_DEVTEN_ULSTCNGEN
+* - XUSBPSU_DEVTEN_CONNECTDONEEN
+* - XUSBPSU_DEVTEN_USBRSTEN
+* - XUSBPSU_DEVTEN_DISCONNEVTEN
+*
+* @return None
+*
+******************************************************************************/
+void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
+{
+ u32 RegVal;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
+ RegVal &= ~Mask;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
+}
+
+/****************************************************************************/
+/**
+*
+* This function does the following:
+* - initializes a specific XUsbPsu instance.
+* - sets up Event Buffer for Core to write events.
+* - Core Reset and PHY Reset.
+* - Sets core in Device Mode.
+* - Sets default speed as HIGH_SPEED.
+* - Sets Device Address to 0.
+* - Enables interrupts.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param ConfigPtr points to the XUsbPsu device configuration structure.
+* @param BaseAddress is the device base address in the virtual memory
+* address space. If the address translation is not used then the
+* physical address is passed.
+* Unexpected errors may occur if the address mapping is changed
+* after this function is invoked.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
+ XUsbPsu_Config *ConfigPtr, u32 BaseAddress)
+{
+ int Status;
+ u32 RegVal;
+
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+ Xil_AssertNonvoid(BaseAddress != 0U)
+
+ InstancePtr->ConfigPtr = ConfigPtr;
+
+ Status = XUsbPsu_CoreInit(InstancePtr);
+ if (Status != XST_SUCCESS) {
+#ifdef XUSBPSU_DEBUG
+ xil_printf("Core initialization failed\r\n");
+#endif
+ return XST_FAILURE;
+ }
+
+ RegVal = XUsbPsu_ReadHwParams(InstancePtr, 3U);
+ InstancePtr->NumInEps = (u8)XUSBPSU_NUM_IN_EPS(RegVal);
+ InstancePtr->NumOutEps = (u8)(XUSBPSU_NUM_EPS(RegVal) -
+ InstancePtr->NumInEps);
+
+ /* Map USB and Physical Endpoints */
+ XUsbPsu_InitializeEps(InstancePtr);
+
+ XUsbPsu_EventBuffersSetup(InstancePtr);
+
+ XUsbPsu_SetMode(InstancePtr, XUSBPSU_GCTL_PRTCAP_DEVICE);
+
+ /*
+ * Setting to max speed to support SS and HS
+ */
+ XUsbPsu_SetSpeed(InstancePtr, XUSBPSU_DCFG_SUPERSPEED);
+
+ (void)XUsbPsu_SetDeviceAddress(InstancePtr, 0U);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Starts the controller so that Host can detect this device.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Start(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+
+ RegVal |= XUSBPSU_DCTL_RUN_STOP;
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
+ XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Stops the controller so that Device disconnects from Host.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Stop(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_RUN_STOP;
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ if (XUsbPsu_Wait_Set_Timeout(InstancePtr, XUSBPSU_DSTS,
+ XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+ * Enables USB2 Test Modes
+ *
+ * @param InstancePtr is a pointer to the XUsbPsu instance.
+ * @param Mode is Test mode to set.
+ *
+ * @return XST_SUCCESS else XST_FAILURE
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+s32 XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, u32 Mode)
+{
+ u32 RegVal;
+ s32 Status = XST_SUCCESS;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid((Mode >= XUSBPSU_TEST_J)
+ && (Mode <= XUSBPSU_TEST_FORCE_ENABLE));
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
+
+ switch (Mode) {
+ case XUSBPSU_TEST_J:
+ case XUSBPSU_TEST_K:
+ case XUSBPSU_TEST_SE0_NAK:
+ case XUSBPSU_TEST_PACKET:
+ case XUSBPSU_TEST_FORCE_ENABLE:
+ RegVal |= (u32)Mode << 1;
+ break;
+
+ default:
+ Status = (s32)XST_FAILURE;
+ break;
+ }
+
+ if (Status != (s32)XST_FAILURE) {
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+ Status = XST_SUCCESS;
+ }
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+ * Gets current State of USB Link
+ *
+ * @param InstancePtr is a pointer to the XUsbPsu instance.
+ *
+ * @return Link State
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+XusbPsuLinkState XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
+
+ return XUSBPSU_DSTS_USBLNKST(RegVal);
+}
+
+/****************************************************************************/
+/**
+ * Sets USB Link to a particular State
+ *
+ * @param InstancePtr is a pointer to the XUsbPsu instance.
+ * @param State is State of Link to set.
+ *
+ * @return XST_SUCCESS else XST_FAILURE
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+s32 XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
+ XusbPsuLinkStateChange State)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Wait until device controller is ready. */
+ if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
+ XUSBPSU_DSTS_DCNRD, 500U) == XST_FAILURE) {
+ return XST_FAILURE;
+ }
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_ULSTCHNGREQ_MASK;
+
+ RegVal |= XUSBPSU_DCTL_ULSTCHNGREQ(State);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sets speed of the Core for connecting to Host
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Speed is required speed
+* - XUSBPSU_DCFG_HIGHSPEED
+* - XUSBPSU_DCFG_FULLSPEED2
+* - XUSBPSU_DCFG_LOWSPEED
+* - XUSBPSU_DCFG_FULLSPEED1
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed)
+{
+ u32 RegVal;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Speed <= (u32)XUSBPSU_DCFG_SUPERSPEED);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+ RegVal &= ~(XUSBPSU_DCFG_SPEED_MASK);
+ RegVal |= Speed;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+}
+
+/****************************************************************************/
+/**
+* Sets Device Address of the Core
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Addr is address to set.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Addr <= 127U);
+
+ if (InstancePtr->State == XUSBPSU_STATE_CONFIGURED) {
+ return XST_FAILURE;
+ }
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+ RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
+ RegVal |= XUSBPSU_DCFG_DEVADDR(Addr);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+
+ if (Addr) {
+ InstancePtr->State = XUSBPSU_STATE_ADDRESS;
+ }
+ else {
+ InstancePtr->State = XUSBPSU_STATE_DEFAULT;
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sets speed of the Core for connecting to Host
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr)
+{
+ if (InstancePtr->Speed != XUSBPSU_SPEED_SUPER) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Set U1 sleep timeout
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Sleep is time in microseconds
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
+ RegVal &= ~XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK;
+ RegVal |= (Sleep << XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Set U2 sleep timeout
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Sleep is time in microseconds
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
+ RegVal &= ~XUSBPSU_PORTMSC_30_U2_TIMEOUT_MASK;
+ RegVal |= (Sleep << XUSBPSU_PORTMSC_30_U2_TIMEOUT_SHIFT);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
+
+ return XST_SUCCESS;
+}
+/****************************************************************************/
+/**
+* Enable Accept U1 and U2 sleep enable
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal |= XUSBPSU_DCTL_ACCEPTU2ENA | XUSBPSU_DCTL_ACCEPTU1ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U1 enable sleep
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U1SleepEnable(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal |= XUSBPSU_DCTL_INITU1ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U2 enable sleep
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U2SleepEnable(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal |= XUSBPSU_DCTL_INITU2ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U1 disable sleep
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U1SleepDisable(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_INITU1ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U2 disable sleep
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U2SleepDisable(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_INITU2ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ return XST_SUCCESS;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h
new file mode 100644
index 0000000000..a1366487ba
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h
@@ -0,0 +1,608 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu.h
+* @addtogroup usbpsu_v1_0
+* @{
+* @details
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.0 sg 06/06/16 First release
+* 1.1 sg 10/24/16 Update for backward compatability
+* Added XUsbPsu_IsSuperSpeed function in xusbpsu.c
+*
+*
+*
+*****************************************************************************/
+#ifndef XUSBPSU_H /* Prevent circular inclusions */
+#define XUSBPSU_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xusbpsu_hw.h"
+#include "xil_io.h"
+/*
+ * The header sleep.h and API usleep() can only be used with an arm design.
+ * MB_Sleep() is used for microblaze design.
+ */
+#if defined (__arm__) || defined (__aarch64__)
+#include "sleep.h"
+#endif
+
+#ifdef __MICROBLAZE__
+#include "microblaze_sleep.h"
+#endif
+#include "xil_cache.h"
+
+/************************** Constant Definitions ****************************/
+
+#define ALIGNMENT_CACHELINE __attribute__ ((aligned(64)))
+
+#define XUSBPSU_PHY_TIMEOUT 5000U /* in micro seconds */
+
+#define XUSBPSU_EP_DIR_IN 1U
+#define XUSBPSU_EP_DIR_OUT 0U
+
+#define XUSBPSU_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */
+#define XUSBPSU_ENDPOINT_DIR_MASK 0x80
+
+#define XUSBPSU_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
+#define XUSBPSU_ENDPOINT_XFER_CONTROL 0U
+#define XUSBPSU_ENDPOINT_XFER_ISOC 1U
+#define XUSBPSU_ENDPOINT_XFER_BULK 2U
+#define XUSBPSU_ENDPOINT_XFER_INT 3U
+#define XUSBPSU_ENDPOINT_MAX_ADJUSTABLE 0x80
+
+#define XUSBPSU_TEST_J 1U
+#define XUSBPSU_TEST_K 2U
+#define XUSBPSU_TEST_SE0_NAK 3U
+#define XUSBPSU_TEST_PACKET 4U
+#define XUSBPSU_TEST_FORCE_ENABLE 5U
+
+#define XUSBPSU_NUM_TRBS 8
+
+#define XUSBPSU_EVENT_PENDING (0x00000001U << 0)
+
+#define XUSBPSU_EP_ENABLED (0x00000001U << 0)
+#define XUSBPSU_EP_STALL (0x00000001U << 1)
+#define XUSBPSU_EP_WEDGE (0x00000001U << 2)
+#define XUSBPSU_EP_BUSY ((u32)0x00000001U << 4)
+#define XUSBPSU_EP_PENDING_REQUEST (0x00000001U << 5)
+#define XUSBPSU_EP_MISSED_ISOC (0x00000001U << 6)
+
+#define XUSBPSU_GHWPARAMS0 0U
+#define XUSBPSU_GHWPARAMS1 1U
+#define XUSBPSU_GHWPARAMS2 2U
+#define XUSBPSU_GHWPARAMS3 3U
+#define XUSBPSU_GHWPARAMS4 4U
+#define XUSBPSU_GHWPARAMS5 5U
+#define XUSBPSU_GHWPARAMS6 6U
+#define XUSBPSU_GHWPARAMS7 7U
+
+/* HWPARAMS0 */
+#define XUSBPSU_MODE(n) ((n) & 0x7)
+#define XUSBPSU_MDWIDTH(n) (((n) & 0xff00) >> 8)
+
+/* HWPARAMS1 */
+#define XUSBPSU_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
+
+/* HWPARAMS3 */
+#define XUSBPSU_NUM_IN_EPS_MASK ((u32)0x0000001fU << (u32)18)
+#define XUSBPSU_NUM_EPS_MASK ((u32)0x0000003fU << (u32)12)
+#define XUSBPSU_NUM_EPS(p) (((u32)(p) & \
+ (XUSBPSU_NUM_EPS_MASK)) >> (u32)12)
+#define XUSBPSU_NUM_IN_EPS(p) (((u32)(p) & \
+ (XUSBPSU_NUM_IN_EPS_MASK)) >> (u32)18)
+
+/* HWPARAMS7 */
+#define XUSBPSU_RAM1_DEPTH(n) ((n) & 0xffff)
+
+#define XUSBPSU_DEPEVT_XFERCOMPLETE 0x01U
+#define XUSBPSU_DEPEVT_XFERINPROGRESS 0x02U
+#define XUSBPSU_DEPEVT_XFERNOTREADY 0x03U
+#define XUSBPSU_DEPEVT_STREAMEVT 0x06U
+#define XUSBPSU_DEPEVT_EPCMDCMPLT 0x07U
+
+/* Within XferNotReady */
+#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
+
+/* Within XferComplete */
+#define DEPEVT_STATUS_BUSERR (1 << 0)
+#define DEPEVT_STATUS_SHORT (1 << 1)
+#define DEPEVT_STATUS_IOC (1 << 2)
+#define DEPEVT_STATUS_LST (1 << 3)
+
+/* Stream event only */
+#define DEPEVT_STREAMEVT_FOUND 1U
+#define DEPEVT_STREAMEVT_NOTFOUND 2U
+
+/* Control-only Status */
+#define DEPEVT_STATUS_CONTROL_DATA 1U
+#define DEPEVT_STATUS_CONTROL_STATUS 2U
+#define DEPEVT_STATUS_CONTROL_DATA_INVALTRB 9
+#define DEPEVT_STATUS_CONTROL_STATUS_INVALTRB 0xA
+
+#define XUSBPSU_ENDPOINTS_NUM 12U
+
+#define XUSBPSU_EVENT_SIZE 4U /* bytes */
+#define XUSBPSU_EVENT_MAX_NUM 64U /* 2 events/endpoint */
+#define XUSBPSU_EVENT_BUFFERS_SIZE (XUSBPSU_EVENT_SIZE * \
+ XUSBPSU_EVENT_MAX_NUM)
+
+#define XUSBPSU_EVENT_TYPE_MASK 0x000000feU
+
+#define XUSBPSU_EVENT_TYPE_DEV 0U
+#define XUSBPSU_EVENT_TYPE_CARKIT 3U
+#define XUSBPSU_EVENT_TYPE_I2C 4U
+
+#define XUSBPSU_DEVICE_EVENT_DISCONNECT 0U
+#define XUSBPSU_DEVICE_EVENT_RESET 1U
+#define XUSBPSU_DEVICE_EVENT_CONNECT_DONE 2U
+#define XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE 3U
+#define XUSBPSU_DEVICE_EVENT_WAKEUP 4U
+#define XUSBPSU_DEVICE_EVENT_HIBER_REQ 5U
+#define XUSBPSU_DEVICE_EVENT_EOPF 6U
+#define XUSBPSU_DEVICE_EVENT_SOF 7U
+#define XUSBPSU_DEVICE_EVENT_ERRATIC_ERROR 9U
+#define XUSBPSU_DEVICE_EVENT_CMD_CMPL 10U
+#define XUSBPSU_DEVICE_EVENT_OVERFLOW 11U
+
+#define XUSBPSU_GEVNTCOUNT_MASK 0x0000fffcU
+
+/*
+ * Control Endpoint state
+ */
+#define XUSBPSU_EP0_SETUP_PHASE 1U /**< Setup Phase */
+#define XUSBPSU_EP0_DATA_PHASE 2U /**< Data Phase */
+#define XUSBPSU_EP0_STATUS_PHASE 3U /**< Status Pahse */
+
+/*
+ * Link State
+ */
+#define XUSBPSU_LINK_STATE_MASK 0x0FU
+
+typedef enum {
+ XUSBPSU_LINK_STATE_U0 = 0x00U, /**< in HS - ON */
+ XUSBPSU_LINK_STATE_U1 = 0x01U,
+ XUSBPSU_LINK_STATE_U2 = 0x02U, /**< in HS - SLEEP */
+ XUSBPSU_LINK_STATE_U3 = 0x03U, /**< in HS - SUSPEND */
+ XUSBPSU_LINK_STATE_SS_DIS = 0x04U,
+ XUSBPSU_LINK_STATE_RX_DET = 0x05U,
+ XUSBPSU_LINK_STATE_SS_INACT = 0x06U,
+ XUSBPSU_LINK_STATE_POLL = 0x07U,
+ XUSBPSU_LINK_STATE_RECOV = 0x08U,
+ XUSBPSU_LINK_STATE_HRESET = 0x09U,
+ XUSBPSU_LINK_STATE_CMPLY = 0x0AU,
+ XUSBPSU_LINK_STATE_LPBK = 0x0BU,
+ XUSBPSU_LINK_STATE_RESET = 0x0EU,
+ XUSBPSU_LINK_STATE_RESUME = 0x0FU,
+}XusbPsuLinkState;
+
+typedef enum {
+ XUSBPSU_LINK_STATE_CHANGE_U0 = 0x00U, /**< in HS - ON */
+ XUSBPSU_LINK_STATE_CHANGE_SS_DIS = 0x04U,
+ XUSBPSU_LINK_STATE_CHANGE_RX_DET = 0x05U,
+ XUSBPSU_LINK_STATE_CHANGE_SS_INACT = 0x06U,
+ XUSBPSU_LINK_STATE_CHANGE_RECOV = 0x08U,
+ XUSBPSU_LINK_STATE_CHANGE_CMPLY = 0x0AU,
+}XusbPsuLinkStateChange;
+
+/*
+ * Device States
+ */
+#define XUSBPSU_STATE_ATTACHED 0U
+#define XUSBPSU_STATE_POWERED 1U
+#define XUSBPSU_STATE_DEFAULT 2U
+#define XUSBPSU_STATE_ADDRESS 3U
+#define XUSBPSU_STATE_CONFIGURED 4U
+#define XUSBPSU_STATE_SUSPENDED 5U
+
+/*
+ * Device Speeds
+ */
+#define XUSBPSU_SPEED_UNKNOWN 0U
+#define XUSBPSU_SPEED_LOW 1U
+#define XUSBPSU_SPEED_FULL 2U
+#define XUSBPSU_SPEED_HIGH 3U
+#define XUSBPSU_SPEED_SUPER 4U
+
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XUSBPSU
+ * device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of controller */
+ u32 BaseAddress; /**< Core register base address */
+} XUsbPsu_Config;
+
+/**
+ * Software Event buffer representation
+ */
+struct XUsbPsu_EvtBuffer {
+ void *BuffAddr;
+ u32 Offset;
+ u32 Count;
+ u32 Flags;
+};
+
+/**
+ * Transfer Request Block - Hardware format
+ */
+struct XUsbPsu_Trb {
+ u32 BufferPtrLow;
+ u32 BufferPtrHigh;
+ u32 Size;
+ u32 Ctrl;
+} __attribute__((packed));
+
+
+/*
+ * Endpoint Parameters
+ */
+struct XUsbPsu_EpParams {
+ u32 Param2; /**< Parameter 2 */
+ u32 Param1; /**< Parameter 1 */
+ u32 Param0; /**< Parameter 0 */
+};
+
+/**
+ * USB Standard Control Request
+ */
+typedef struct {
+ u8 bRequestType;
+ u8 bRequest;
+ u16 wValue;
+ u16 wIndex;
+ u16 wLength;
+} __attribute__ ((packed)) SetupPacket;
+
+/**
+ * Endpoint representation
+ */
+struct XUsbPsu_Ep {
+ void (*Handler)(void *, u32, u32);
+ /** < User handler called
+ * when data is sent for IN Ep
+ * and received for OUT Ep
+ */
+ struct XUsbPsu_Trb EpTrb ALIGNMENT_CACHELINE;/**< TRB used by endpoint */
+ u32 EpStatus; /**< Flags to represent Endpoint status */
+ u32 RequestedBytes; /**< RequestedBytes for transfer */
+ u32 BytesTxed; /**< Actual Bytes transferred */
+ u16 MaxSize; /**< Size of endpoint */
+ u8 *BufferPtr; /**< Buffer location */
+ u8 ResourceIndex; /**< Resource Index assigned to
+ * Endpoint by core
+ */
+ u8 PhyEpNum; /**< Physical Endpoint Number in core */
+ u8 UsbEpNum; /**< USB Endpoint Number */
+ u8 Type; /**< Type of Endpoint -
+ * Control/BULK/INTERRUPT/ISOC
+ */
+ u8 Direction; /**< Direction - EP_DIR_OUT/EP_DIR_IN */
+ u8 UnalignedTx;
+};
+
+/**
+ * USB Device Controller representation
+ */
+struct XUsbPsu {
+ SetupPacket SetupData ALIGNMENT_CACHELINE;
+ /**< Setup Packet buffer */
+ struct XUsbPsu_Trb Ep0_Trb ALIGNMENT_CACHELINE;
+ /**< TRB for control transfers */
+ XUsbPsu_Config *ConfigPtr; /**< Configuration info pointer */
+ struct XUsbPsu_Ep eps[XUSBPSU_ENDPOINTS_NUM]; /**< Endpoints */
+ struct XUsbPsu_EvtBuffer Evt;
+ struct XUsbPsu_EpParams EpParams;
+ u32 BaseAddress; /**< Core register base address */
+ u32 DevDescSize;
+ u32 ConfigDescSize;
+ void (*Chapter9)(struct XUsbPsu *, SetupPacket *);
+ void (*ClassHandler)(struct XUsbPsu *, SetupPacket *);
+ void *DevDesc;
+ void *ConfigDesc;
+ u8 EventBuffer[XUSBPSU_EVENT_BUFFERS_SIZE]
+ __attribute__((aligned(XUSBPSU_EVENT_BUFFERS_SIZE)));
+ u8 NumOutEps;
+ u8 NumInEps;
+ u8 ControlDir;
+ u8 IsInTestMode;
+ u8 TestMode;
+ u8 Speed;
+ u8 State;
+ u8 Ep0State;
+ u8 LinkState;
+ u8 UnalignedTx;
+ u8 IsConfigDone;
+ u8 IsThreeStage;
+};
+
+struct XUsbPsu_Event_Type {
+ u32 Is_DevEvt:1;
+ u32 Type:7;
+ u32 Reserved8_31:24;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_depvt - Device Endpoint Events
+ * @Is_EpEvt: indicates this is an endpoint event
+ * @endpoint_number: number of the endpoint
+ * @endpoint_event: The event we have:
+ * 0x00 - Reserved
+ * 0x01 - XferComplete
+ * 0x02 - XferInProgress
+ * 0x03 - XferNotReady
+ * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
+ * 0x05 - Reserved
+ * 0x06 - StreamEvt
+ * 0x07 - EPCmdCmplt
+ * @Reserved11_10: Reserved, don't use.
+ * @Status: Indicates the status of the event. Refer to databook for
+ * more information.
+ * @Parameters: Parameters of the current event. Refer to databook for
+ * more information.
+ */
+struct XUsbPsu_Event_Epevt {
+ u32 Is_EpEvt:1;
+ u32 Epnumber:5;
+ u32 Endpoint_Event:4;
+ u32 Reserved11_10:2;
+ u32 Status:4;
+ u32 Parameters:16;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_devt - Device Events
+ * @Is_DevEvt: indicates this is a non-endpoint event
+ * @Device_Event: indicates it's a device event. Should read as 0x00
+ * @Type: indicates the type of device event.
+ * 0 - DisconnEvt
+ * 1 - USBRst
+ * 2 - ConnectDone
+ * 3 - ULStChng
+ * 4 - WkUpEvt
+ * 5 - Reserved
+ * 6 - EOPF
+ * 7 - SOF
+ * 8 - Reserved
+ * 9 - ErrticErr
+ * 10 - CmdCmplt
+ * 11 - EvntOverflow
+ * 12 - VndrDevTstRcved
+ * @Reserved15_12: Reserved, not used
+ * @Event_Info: Information about this event
+ * @Reserved31_25: Reserved, not used
+ */
+struct XUsbPsu_Event_Devt {
+ u32 Is_DevEvt:1;
+ u32 Device_Event:7;
+ u32 Type:4;
+ u32 Reserved15_12:4;
+ u32 Event_Info:9;
+ u32 Reserved31_25:7;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_gevt - Other Core Events
+ * @one_bit: indicates this is a non-endpoint event (not used)
+ * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
+ * @phy_port_number: self-explanatory
+ * @reserved31_12: Reserved, not used.
+ */
+struct XUsbPsu_Event_Gevt {
+ u32 Is_GlobalEvt:1;
+ u32 Device_Event:7;
+ u32 Phy_Port_Number:4;
+ u32 Reserved31_12:20;
+} __attribute__((packed));
+
+/**
+ * union XUsbPsu_event - representation of Event Buffer contents
+ * @raw: raw 32-bit event
+ * @type: the type of the event
+ * @depevt: Device Endpoint Event
+ * @devt: Device Event
+ * @gevt: Global Event
+ */
+union XUsbPsu_Event {
+ u32 Raw;
+ struct XUsbPsu_Event_Type Type;
+ struct XUsbPsu_Event_Epevt Epevt;
+ struct XUsbPsu_Event_Devt Devt;
+ struct XUsbPsu_Event_Gevt Gevt;
+};
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0U)
+
+#define roundup(x, y) ( \
+{ \
+ const typeof(y) y__ = (y); \
+ (((x) + (u32)(y__ - 1)) / (u32)y__) * (u32)y__; \
+} \
+)
+
+#define DECLARE_DEV_DESC(Instance, desc) \
+ (Instance).DevDesc = &(desc); \
+ (Instance).DevDescSize = sizeof((desc))
+
+#define DECLARE_CONFIG_DESC(Instance, desc) \
+ (Instance).ConfigDesc = &(desc); \
+ (Instance).ConfigDescSize = sizeof((desc))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions in xusbpsu.c
+ */
+s32 XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+ u32 BitMask, u32 Timeout);
+s32 XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+ u32 BitMask, u32 Timeout);
+void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 Mode);
+void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr);
+void XUsbPsu_CoreNumEps(struct XUsbPsu *InstancePtr);
+void XUsbPsu_cache_hwparams(struct XUsbPsu *InstancePtr);
+u32 XUsbPsu_ReadHwParams(struct XUsbPsu *InstancePtr, u8 RegIndex);
+s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask);
+void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask);
+s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
+ XUsbPsu_Config *ConfigPtr, u32 BaseAddress);
+s32 XUsbPsu_Start(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_Stop(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, u32 Mode);
+XusbPsuLinkState XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
+ XusbPsuLinkStateChange State);
+s32 XUsbPsu_SendGenericCmd(struct XUsbPsu *InstancePtr,
+ s32 Cmd, u32 Param);
+void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed);
+s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr);
+s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep);
+s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep);
+s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U1SleepEnable(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U2SleepEnable(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U1SleepDisable(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U2SleepDisable(struct XUsbPsu *InstancePtr);
+
+/*
+ * Functions in xusbpsu_endpoint.c
+ */
+struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr);
+u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
+ u8 Dir);
+const char *XUsbPsu_EpCmdString(u8 Cmd);
+s32 XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+ u32 Cmd, struct XUsbPsu_EpParams *Params);
+s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum,
+ u8 Dir);
+s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+ u16 Size, u8 Type);
+s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir);
+s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+ u16 Maxsize, u8 Type);
+s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir);
+s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size);
+void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr);
+void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir);
+void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp,
+ u8 *BufferPtr, u32 BufferLen);
+s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp,
+ u8 *BufferPtr, u32 Length);
+void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
+void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
+void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 Epnum,
+ u8 Dir, void (*Handler)(void *, u32, u32));
+s32 XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
+void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+
+/*
+ * Functions in xusbpsu_controltransfers.c
+ */
+s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr);
+void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetConfiguration(struct XUsbPsu *InstancePtr,
+ SetupPacket *Ctrl);
+void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr,
+ struct XUsbPsu_Ep *Ept);
+void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr,
+ u32 BufferLen);
+s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length);
+void XUsbSleep(u32 USeconds);
+
+/*
+ * Functions in xusbpsu_intr.c
+ */
+void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr,
+ u32 EvtInfo);
+void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Devt *Event);
+void XUsbPsu_EventHandler(struct XUsbPsu *InstancePtr,
+ const union XUsbPsu_Event *Event);
+void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr);
+void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr);
+
+/*
+ * Functions in xusbpsu_sinit.c
+ */
+XUsbPsu_Config *XUsbPsu_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro. */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c
new file mode 100644
index 0000000000..b3a93dc636
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c
@@ -0,0 +1,681 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_controltransfers.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 sg 06/06/16 First release
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xusbpsu.h"
+#include "xusbpsu_endpoint.h"
+/************************** Constant Definitions *****************************/
+
+#define USB_DIR_OUT 0U /* to device */
+#define USB_DIR_IN 0x80U /* to host */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+* Initiates DMA on Control Endpoint 0 to receive Setup packet.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr)
+{
+ struct XUsbPsu_EpParams *Params;
+ struct XUsbPsu_Trb *TrbPtr;
+ struct XUsbPsu_Ep *Ept;
+ s32 Ret;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+
+ /* Setup packet always on EP0 */
+ Ept = &InstancePtr->eps[0];
+ if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+ return XST_FAILURE;
+ }
+
+ TrbPtr = &InstancePtr->Ep0_Trb;
+
+ TrbPtr->BufferPtrLow = (UINTPTR)&InstancePtr->SetupData;
+ TrbPtr->BufferPtrHigh = ((UINTPTR)&InstancePtr->SetupData >> 16) >> 16;
+ TrbPtr->Size = 8U;
+ TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_SETUP;
+
+ TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+ | XUSBPSU_TRB_CTRL_LST
+ | XUSBPSU_TRB_CTRL_IOC
+ | XUSBPSU_TRB_CTRL_ISP_IMI);
+
+ Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+ Params->Param0 = 0U;
+ Params->Param1 = (UINTPTR)TrbPtr;
+
+ InstancePtr->Ep0State = XUSBPSU_EP0_SETUP_PHASE;
+
+ Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
+ XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+ if (Ret != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ Ept->EpStatus |= XUSBPSU_EP_BUSY;
+ Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+ Ept->UsbEpNum, Ept->Direction);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Stalls Control Endpoint and restarts to receive Setup packet.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr)
+{
+ struct XUsbPsu_Ep *Ept;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /* reinitialize physical ep1 */
+ Ept = &InstancePtr->eps[1];
+ Ept->EpStatus = XUSBPSU_EP_ENABLED;
+
+ /* stall is always issued on EP0 */
+ XUsbPsu_EpSetStall(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT);
+
+ Ept = &InstancePtr->eps[0];
+ Ept->EpStatus = XUSBPSU_EP_ENABLED;
+ InstancePtr->Ep0State = XUSBPSU_EP0_SETUP_PHASE;
+ (void)XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Checks the Data Phase and calls user Endpoint handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_Trb *TrbPtr;
+ u32 Status;
+ u32 Length;
+ u32 Epnum;
+ u8 Dir;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Event != NULL);
+
+ Epnum = Event->Epnumber;
+ Dir = (u8)(!!Epnum);
+ Ept = &InstancePtr->eps[Epnum];
+ TrbPtr = &InstancePtr->Ep0_Trb;
+
+ Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+ Status = XUSBPSU_TRB_SIZE_TRBSTS(TrbPtr->Size);
+ if (Status == XUSBPSU_TRBSTS_SETUP_PENDING) {
+ return;
+ }
+
+ Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK;
+
+ if (Length == 0U) {
+ Ept->BytesTxed = Ept->RequestedBytes;
+ } else {
+ if (Dir == XUSBPSU_EP_DIR_IN) {
+ Ept->BytesTxed = Ept->RequestedBytes - Length;
+ } else if (Dir == XUSBPSU_EP_DIR_OUT) {
+ if (Ept->UnalignedTx == 1U) {
+ Ept->BytesTxed = Ept->RequestedBytes;
+ Ept->UnalignedTx = 0U;
+ }
+ }
+ }
+
+ if (Dir == XUSBPSU_EP_DIR_OUT) {
+ /* Invalidate Cache */
+ Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed);
+ }
+
+ if (Ept->Handler != NULL) {
+ Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed);
+ }
+}
+
+/****************************************************************************/
+/**
+* Checks the Status Phase and starts next Control transfer.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Trb *TrbPtr;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Event != NULL);
+
+ TrbPtr = &InstancePtr->Ep0_Trb;
+
+ if (InstancePtr->IsInTestMode != 0U) {
+ s32 Ret;
+
+ Ret = XUsbPsu_SetTestMode(InstancePtr,
+ InstancePtr->TestMode);
+ if (Ret < 0) {
+ XUsbPsu_Ep0StallRestart(InstancePtr);
+ return;
+ }
+ }
+ Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+ (void)XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Handles Transfer complete event of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Ep *Ept;
+ SetupPacket *Ctrl;
+ u16 Length;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Event != NULL);
+
+ Ept = &InstancePtr->eps[Event->Epnumber];
+ Ctrl = &InstancePtr->SetupData;
+
+ Ept->EpStatus &= ~XUSBPSU_EP_BUSY;
+ Ept->ResourceIndex = 0U;
+
+ switch (InstancePtr->Ep0State) {
+ case XUSBPSU_EP0_SETUP_PHASE:
+ Xil_DCacheInvalidateRange((INTPTR)&InstancePtr->SetupData,
+ sizeof(InstancePtr->SetupData));
+ Length = Ctrl->wLength;
+ if (Length == 0U) {
+ InstancePtr->IsThreeStage = 0U;
+ InstancePtr->ControlDir = XUSBPSU_EP_DIR_OUT;
+ } else {
+ InstancePtr->IsThreeStage = 1U;
+ InstancePtr->ControlDir = !!(Ctrl->bRequestType &
+ USB_DIR_IN);
+ }
+
+ Xil_AssertVoid(InstancePtr->Chapter9 != NULL);
+
+ InstancePtr->Chapter9(InstancePtr,
+ &InstancePtr->SetupData);
+ break;
+
+ case XUSBPSU_EP0_DATA_PHASE:
+ XUsbPsu_Ep0DataDone(InstancePtr, Event);
+ break;
+
+ case XUSBPSU_EP0_STATUS_PHASE:
+ XUsbPsu_Ep0StatusDone(InstancePtr, Event);
+ break;
+
+ default:
+ /* Default case is a required MISRA-C guideline. */
+ break;
+ }
+}
+
+/****************************************************************************/
+/**
+* Starts Status Phase of Control Transfer
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_EpParams *Params;
+ struct XUsbPsu_Trb *TrbPtr;
+ u32 Type;
+ s32 Ret;
+ u8 Dir;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Event != NULL);
+
+ Ept = &InstancePtr->eps[Event->Epnumber];
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+ if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+ return XST_FAILURE;
+ }
+
+ Type = (InstancePtr->IsThreeStage != 0U) ? XUSBPSU_TRBCTL_CONTROL_STATUS3
+ : XUSBPSU_TRBCTL_CONTROL_STATUS2;
+ TrbPtr = &InstancePtr->Ep0_Trb;
+ /* we use same TrbPtr for setup packet */
+ TrbPtr->BufferPtrLow = (UINTPTR)&InstancePtr->SetupData;
+ TrbPtr->BufferPtrHigh = ((UINTPTR)&InstancePtr->SetupData >> 16) >> 16;
+ TrbPtr->Size = 0U;
+ TrbPtr->Ctrl = Type;
+
+ TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+ | XUSBPSU_TRB_CTRL_LST
+ | XUSBPSU_TRB_CTRL_IOC
+ | XUSBPSU_TRB_CTRL_ISP_IMI);
+
+ Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+ Params->Param0 = 0U;
+ Params->Param1 = (UINTPTR)TrbPtr;
+
+ InstancePtr->Ep0State = XUSBPSU_EP0_STATUS_PHASE;
+
+ /*
+ * Control OUT transfer - Status stage happens on EP0 IN - EP1
+ * Control IN transfer - Status stage happens on EP0 OUT - EP0
+ */
+ Dir = !InstancePtr->ControlDir;
+
+ Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, Dir,
+ XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+ if (Ret != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ Ept->EpStatus |= XUSBPSU_EP_BUSY;
+ Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+ Ept->UsbEpNum, Ept->Direction);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Ends Data Phase - used incase of error.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Dep is a pointer to the Endpoint structure.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr,
+ struct XUsbPsu_Ep *Ept)
+{
+ struct XUsbPsu_EpParams *Params;
+ u32 Cmd;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Ept != NULL);
+
+ if (Ept->ResourceIndex == 0U) {
+ return;
+ }
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertVoid(Params != NULL);
+
+ Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
+ Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
+ (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction,
+ Cmd, Params);
+ Ept->ResourceIndex = 0U;
+ XUsbSleep(200U);
+}
+
+/****************************************************************************/
+/**
+* Handles Transfer Not Ready event of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Ep *Ept;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Event != NULL);
+
+ Ept = &InstancePtr->eps[Event->Epnumber];
+
+ switch (Event->Status) {
+ case DEPEVT_STATUS_CONTROL_DATA:
+ /*
+ * We already have a DATA transfer in the controller's cache,
+ * if we receive a XferNotReady(DATA) we will ignore it, unless
+ * it's for the wrong direction.
+ *
+ * In that case, we must issue END_TRANSFER command to the Data
+ * Phase we already have started and issue SetStall on the
+ * control endpoint.
+ */
+ if (Event->Epnumber != InstancePtr->ControlDir) {
+ XUsbPsu_Ep0_EndControlData(InstancePtr, Ept);
+ XUsbPsu_Ep0StallRestart(InstancePtr);
+ }
+ break;
+
+ case DEPEVT_STATUS_CONTROL_STATUS:
+ (void)XUsbPsu_Ep0StartStatus(InstancePtr, Event);
+ break;
+
+ default:
+ /* Default case is a required MIRSA-C guideline. */
+ break;
+ }
+}
+
+/****************************************************************************/
+/**
+* Handles Interrupts of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Event != NULL);
+
+ switch (Event->Endpoint_Event) {
+ case XUSBPSU_DEPEVT_XFERCOMPLETE:
+ XUsbPsu_Ep0XferComplete(InstancePtr, Event);
+ break;
+
+ case XUSBPSU_DEPEVT_XFERNOTREADY:
+ XUsbPsu_Ep0XferNotReady(InstancePtr, Event);
+ break;
+
+ case XUSBPSU_DEPEVT_XFERINPROGRESS:
+ case XUSBPSU_DEPEVT_STREAMEVT:
+ case XUSBPSU_DEPEVT_EPCMDCMPLT:
+ break;
+
+ default:
+ /* Default case is a required MIRSA-C guideline. */
+ break;
+ }
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to send data on Control Endpoint EP0 IN to Host.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param BufferPtr is pointer to data.
+* @param BufferLen is Length of data buffer.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 BufferLen)
+{
+ /* Control IN - EP1 */
+ struct XUsbPsu_EpParams *Params;
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_Trb *TrbPtr;
+ s32 Ret;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+
+ Ept = &InstancePtr->eps[1];
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+
+ if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+ return XST_FAILURE;
+ }
+
+ Ept->RequestedBytes = BufferLen;
+ Ept->BytesTxed = 0U;
+ Ept->BufferPtr = BufferPtr;
+
+ TrbPtr = &InstancePtr->Ep0_Trb;
+
+ TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
+ TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+ TrbPtr->Size = BufferLen;
+ TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_DATA;
+
+ TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+ | XUSBPSU_TRB_CTRL_LST
+ | XUSBPSU_TRB_CTRL_IOC
+ | XUSBPSU_TRB_CTRL_ISP_IMI);
+
+ Params->Param0 = 0U;
+ Params->Param1 = (UINTPTR)TrbPtr;
+
+ Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+ Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen);
+
+ InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE;
+
+ Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_IN,
+ XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+ if (Ret != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ Ept->EpStatus |= XUSBPSU_EP_BUSY;
+ Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+ Ept->UsbEpNum, Ept->Direction);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to receive data on Control Endpoint EP0 OUT from Host.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param BufferPtr is pointer to data.
+* @param Length is Length of data to be received.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length)
+{
+ struct XUsbPsu_EpParams *Params;
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_Trb *TrbPtr;
+ u32 Size;
+ s32 Ret;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+
+ Ept = &InstancePtr->eps[0];
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+
+ if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+ return XST_FAILURE;
+ }
+
+ Ept->RequestedBytes = Length;
+ Size = Length;
+ Ept->BytesTxed = 0U;
+ Ept->BufferPtr = BufferPtr;
+
+ /*
+ * 8.2.5 - An OUT transfer size (Total TRB buffer allocation)
+ * must be a multiple of MaxPacketSize even if software is expecting a
+ * fixed non-multiple of MaxPacketSize transfer from the Host.
+ */
+ if (!IS_ALIGNED(Length, Ept->MaxSize)) {
+ Size = (u32)roundup(Length, Ept->MaxSize);
+ InstancePtr->UnalignedTx = 1U;
+ }
+
+ TrbPtr = &InstancePtr->Ep0_Trb;
+
+ TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
+ TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+ TrbPtr->Size = Size;
+ TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_DATA;
+
+ TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+ | XUSBPSU_TRB_CTRL_LST
+ | XUSBPSU_TRB_CTRL_IOC
+ | XUSBPSU_TRB_CTRL_ISP_IMI);
+
+ Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+ Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length);
+
+ Params->Param0 = 0U;
+ Params->Param1 = (UINTPTR)TrbPtr;
+
+ InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE;
+
+ Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
+ XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+ if (Ret != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ Ept->EpStatus |= XUSBPSU_EP_BUSY;
+ Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+ Ept->UsbEpNum, Ept->Direction);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* API for Sleep routine.
+*
+* @param USeconds is time in MicroSeconds.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XUsbSleep(u32 USeconds) {
+ (void)usleep(USeconds);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c
new file mode 100644
index 0000000000..41368e5263
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c
@@ -0,0 +1,927 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_endpoint.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 sg 06/06/16 First release
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xusbpsu.h"
+#include "xusbpsu_endpoint.h"
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* return Physical EP number as dwc3 mapping */
+#define PhysicalEp(epnum, direction) (((epnum) << 1 ) | (direction))
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+* Returns zeroed parameters to be used by Endpoint commands
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return Zeroed Params structure pointer.
+*
+* @note None.
+*
+*****************************************************************************/
+struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr)
+{
+ if (InstancePtr == NULL) {
+ return NULL;
+ }
+
+ InstancePtr->EpParams.Param0 = 0x00U;
+ InstancePtr->EpParams.Param1 = 0x00U;
+ InstancePtr->EpParams.Param2 = 0x00U;
+
+ return &InstancePtr->EpParams;
+}
+
+/****************************************************************************/
+/**
+* Returns Transfer Index assigned by Core for an Endpoint transfer.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT
+*
+* @return Transfer Resource Index.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
+ u8 Dir)
+{
+ u8 PhyEpNum;
+ u32 ResourceIndex;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = (u8)PhysicalEp(UsbEpNum, Dir);
+ ResourceIndex = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum));
+
+ return (u32)XUSBPSU_DEPCMD_GET_RSC_IDX(ResourceIndex);
+}
+
+/****************************************************************************/
+/**
+* Sends Endpoint command to Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint
+* - XUSBPSU_EP_DIR_IN/ XUSBPSU_EP_DIR_OUT.
+* @param Cmd is Endpoint command.
+* @param Params is Endpoint command parameters.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+ u32 Cmd, struct XUsbPsu_EpParams *Params)
+{
+ u32 PhyEpNum;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(UsbEpNum, Dir);
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR0(PhyEpNum),
+ Params->Param0);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR1(PhyEpNum),
+ Params->Param1);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR2(PhyEpNum),
+ Params->Param2);
+
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum),
+ Cmd | XUSBPSU_DEPCMD_CMDACT);
+
+ if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum),
+ XUSBPSU_DEPCMD_CMDACT, 500U) == (s32)XST_FAILURE) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sends Start New Configuration command to Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint
+* - XUSBPSU_EP_DIR_IN/ XUSBPSU_EP_DIR_OUT.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note
+* As per data book this command should be issued by software
+* under these conditions:
+* 1. After power-on-reset with XferRscIdx=0 before starting
+* to configure Physical Endpoints 0 and 1.
+* 2. With XferRscIdx=2 before starting to configure
+* Physical Endpoints > 1
+* 3. This command should always be issued to
+* Endpoint 0 (DEPCMD0).
+*
+*****************************************************************************/
+s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum, u8 Dir)
+{
+ struct XUsbPsu_EpParams *Params;
+ u32 Cmd;
+ u8 PhyEpNum;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u32)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = (u8)PhysicalEp(UsbEpNum, (u32)Dir);
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+
+ if (PhyEpNum != 1U) {
+ Cmd = XUSBPSU_DEPCMD_DEPSTARTCFG;
+ /* XferRscIdx == 0 for EP0 and 2 for the remaining */
+ if (PhyEpNum > 1U) {
+ if (InstancePtr->IsConfigDone != 0U) {
+ return XST_SUCCESS;
+ }
+ InstancePtr->IsConfigDone = 1U;
+ Cmd |= XUSBPSU_DEPCMD_PARAM(2);
+ }
+
+ return XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
+ Cmd, Params);
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sends Set Endpoint Configuration command to Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param Size is size of Endpoint size.
+* @param Type is Endpoint type Control/Bulk/Interrupt/Isoc.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+ u16 Size, u8 Type)
+{
+ struct XUsbPsu_EpParams *Params;
+ u8 PhyEpNum;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+ Xil_AssertNonvoid((Size >= 64U) && (Size <= 1024U));
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+
+ PhyEpNum = PhysicalEp(UsbEpNum , Dir);
+
+ Params->Param0 = XUSBPSU_DEPCFG_EP_TYPE(Type)
+ | XUSBPSU_DEPCFG_MAX_PACKET_SIZE(Size);
+
+ /*
+ * Set burst size to 1 as recommended
+ */
+ Params->Param0 |= XUSBPSU_DEPCFG_BURST_SIZE(1);
+
+ Params->Param1 = XUSBPSU_DEPCFG_XFER_COMPLETE_EN
+ | XUSBPSU_DEPCFG_XFER_NOT_READY_EN;
+
+ /*
+ * We are doing 1:1 mapping for endpoints, meaning
+ * Physical Endpoints 2 maps to Logical Endpoint 2 and
+ * so on. We consider the direction bit as part of the physical
+ * endpoint number. So USB endpoint 0x81 is 0x03.
+ */
+ Params->Param1 |= XUSBPSU_DEPCFG_EP_NUMBER(PhyEpNum);
+
+ if (Dir != XUSBPSU_EP_DIR_OUT) {
+ Params->Param0 |= XUSBPSU_DEPCFG_FIFO_NUMBER((u32)PhyEpNum >> 1);
+ }
+
+ return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir,
+ XUSBPSU_DEPCMD_SETEPCONFIG, Params);
+}
+
+/****************************************************************************/
+/**
+* Sends Set Transfer Resource command to Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/
+* XUSBPSU_EP_DIR_OUT.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+ struct XUsbPsu_EpParams *Params;
+
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+
+ Params->Param0 = XUSBPSU_DEPXFERCFG_NUM_XFER_RES(1);
+
+ return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir,
+ XUSBPSU_DEPCMD_SETTRANSFRESOURCE, Params);
+}
+
+/****************************************************************************/
+/**
+* Enables Endpoint for sending/receiving data.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param Maxsize is size of Endpoint size.
+* @param Type is Endpoint type Control/Bulk/Interrupt/Isoc.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+****************************************************************************/
+s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+ u16 Maxsize, u8 Type)
+{
+ struct XUsbPsu_Ep *Ept;
+ u32 RegVal;
+ s32 Ret = (s32)XST_FAILURE;
+ u32 PhyEpNum;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+ Xil_AssertNonvoid((Maxsize >= 64U) && (Maxsize <= 1024U));
+
+ PhyEpNum = PhysicalEp(UsbEpNum , Dir);
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ Ept->UsbEpNum = UsbEpNum;
+ Ept->Direction = Dir;
+ Ept->Type = Type;
+ Ept->MaxSize = Maxsize;
+ Ept->PhyEpNum = (u8)PhyEpNum;
+
+ if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) {
+ Ret = XUsbPsu_StartEpConfig(InstancePtr, UsbEpNum, Dir);
+ if (Ret != 0) {
+ return Ret;
+ }
+ }
+
+ Ret = XUsbPsu_SetEpConfig(InstancePtr, UsbEpNum, Dir, Maxsize, Type);
+ if (Ret != 0) {
+ return Ret;
+ }
+
+ if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) {
+ Ret = XUsbPsu_SetXferResource(InstancePtr, UsbEpNum, Dir);
+ if (Ret != 0) {
+ return Ret;
+ }
+
+ Ept->EpStatus |= XUSBPSU_EP_ENABLED;
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA);
+ RegVal |= XUSBPSU_DALEPENA_EP(Ept->PhyEpNum);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal);
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Disables Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint
+* - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+****************************************************************************/
+s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+ u32 RegVal;
+ u8 PhyEpNum;
+ struct XUsbPsu_Ep *Ept;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+ (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(UsbEpNum , Dir);
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA);
+ RegVal &= ~XUSBPSU_DALEPENA_EP(PhyEpNum);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal);
+
+ Ept->Type = 0U;
+ Ept->EpStatus = 0U;
+ Ept->MaxSize = 0U;
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enables USB Control Endpoint i.e., EP0OUT and EP0IN of Core.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Size is control endpoint size.
+*
+* @return XST_SUCCESS else XST_FAILURE.
+*
+* @note None.
+*
+****************************************************************************/
+s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size)
+{
+ s32 RetVal;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid((Size >= 64U) && (Size <= 512U));
+
+ RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, Size,
+ XUSBPSU_ENDPOINT_XFER_CONTROL);
+ if (RetVal != 0) {
+ return XST_FAILURE;
+ }
+
+ RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_IN, Size,
+ XUSBPSU_ENDPOINT_XFER_CONTROL);
+ if (RetVal != 0) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initializes Endpoints. All OUT endpoints are even numbered and all IN
+* endpoints are odd numbered. EP0 is for Control OUT and EP1 is for
+* Control IN.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr)
+{
+ u8 i;
+ u8 Epnum;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ for (i = 0U; i < InstancePtr->NumOutEps; i++) {
+ Epnum = (i << 1U) | XUSBPSU_EP_DIR_OUT;
+ InstancePtr->eps[Epnum].PhyEpNum = Epnum;
+ InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_OUT;
+ }
+ for (i = 0U; i < InstancePtr->NumInEps; i++) {
+ Epnum = (i << 1U) | XUSBPSU_EP_DIR_IN;
+ InstancePtr->eps[Epnum].PhyEpNum = Epnum;
+ InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_IN;
+ }
+}
+
+/****************************************************************************/
+/**
+* Stops transfer on Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_EpParams *Params;
+ u8 PhyEpNum;
+ u32 Cmd;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(UsbEpNum <= (u8)16U);
+ Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(UsbEpNum, Dir);
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertVoid(Params != NULL);
+
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ if (Ept->ResourceIndex == 0U) {
+ return;
+ }
+
+ /*
+ * - Issue EndTransfer WITH CMDIOC bit set
+ * - Wait 100us
+ */
+ Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
+ Cmd |= XUSBPSU_DEPCMD_CMDIOC;
+ Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
+ (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+ Cmd, Params);
+ Ept->ResourceIndex = 0U;
+ Ept->EpStatus &= ~XUSBPSU_EP_BUSY;
+ XUsbSleep(100U);
+}
+
+/****************************************************************************/
+/**
+* Clears Stall on all endpoints.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr)
+{
+ struct XUsbPsu_EpParams *Params;
+ u32 Epnum;
+ struct XUsbPsu_Ep *Ept;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertVoid(Params != NULL);
+
+ for (Epnum = 1U; Epnum < XUSBPSU_ENDPOINTS_NUM; Epnum++) {
+
+ Ept = &InstancePtr->eps[Epnum];
+ if (Ept == NULL) {
+ continue;
+ }
+
+ if ((Ept->EpStatus & XUSBPSU_EP_STALL) == 0U) {
+ continue;
+ }
+
+ Ept->EpStatus &= ~XUSBPSU_EP_STALL;
+
+ (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum,
+ Ept->Direction, XUSBPSU_DEPCMD_CLEARSTALL,
+ Params);
+ }
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to send data on endpoint to Host.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param UsbEp is USB endpoint number.
+* @param BufferPtr is pointer to data.
+* @param BufferLen is length of data buffer.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp,
+ u8 *BufferPtr, u32 BufferLen)
+{
+ u8 PhyEpNum;
+ s32 RetVal;
+ struct XUsbPsu_Trb *TrbPtr;
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_EpParams *Params;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEp <= (u8)16U);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+
+ PhyEpNum = PhysicalEp(UsbEp, XUSBPSU_EP_DIR_IN);
+ if (PhyEpNum == 1U) {
+ RetVal = XUsbPsu_Ep0Send(InstancePtr, BufferPtr, BufferLen);
+ return RetVal;
+ }
+
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ if (Ept->Direction != XUSBPSU_EP_DIR_IN) {
+ return XST_FAILURE;
+ }
+
+ Ept->RequestedBytes = BufferLen;
+ Ept->BytesTxed = 0U;
+ Ept->BufferPtr = BufferPtr;
+
+ TrbPtr = &Ept->EpTrb;
+ Xil_AssertNonvoid(TrbPtr != NULL);
+
+ TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
+ TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+ TrbPtr->Size = BufferLen & XUSBPSU_TRB_SIZE_MASK;
+ TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL;
+
+ TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+ | XUSBPSU_TRB_CTRL_LST
+ | XUSBPSU_TRB_CTRL_IOC
+ | XUSBPSU_TRB_CTRL_ISP_IMI);
+
+ Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+ Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen);
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+ Params->Param0 = 0U;
+ Params->Param1 = (UINTPTR)TrbPtr;
+
+ RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction,
+ XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+ if (RetVal != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+ Ept->UsbEpNum,
+ Ept->Direction);
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to receive data on Endpoint from Host.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param EpNum is USB endpoint number.
+* @param BufferPtr is pointer to data.
+* @param Length is length of data to be received.
+*
+* @return XST_SUCCESS else XST_FAILURE
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp,
+ u8 *BufferPtr, u32 Length)
+{
+ u8 PhyEpNum;
+ u32 Size;
+ s32 RetVal;
+ struct XUsbPsu_Trb *TrbPtr;
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_EpParams *Params;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(UsbEp <= (u8)16U);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+
+ PhyEpNum = PhysicalEp(UsbEp, XUSBPSU_EP_DIR_OUT);
+ if (PhyEpNum == 0U) {
+ RetVal = XUsbPsu_Ep0Recv(InstancePtr, BufferPtr, Length);
+ return RetVal;
+ }
+
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ if (Ept->Direction != XUSBPSU_EP_DIR_OUT) {
+ return XST_FAILURE;
+ }
+
+ Ept->RequestedBytes = Length;
+ Size = Length;
+ Ept->BytesTxed = 0U;
+ Ept->BufferPtr = BufferPtr;
+
+ /*
+ * 8.2.5 - An OUT transfer size (Total TRB buffer allocation)
+ * must be a multiple of MaxPacketSize even if software is expecting a
+ * fixed non-multiple of MaxPacketSize transfer from the Host.
+ */
+ if (!IS_ALIGNED(Length, Ept->MaxSize)) {
+ Size = (u32)roundup(Length, Ept->MaxSize);
+ Ept->UnalignedTx = 1U;
+ }
+
+ TrbPtr = &Ept->EpTrb;
+ Xil_AssertNonvoid(TrbPtr != NULL);
+
+ TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
+ TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+ TrbPtr->Size = Size;
+ TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL;
+
+ TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+ | XUSBPSU_TRB_CTRL_LST
+ | XUSBPSU_TRB_CTRL_IOC
+ | XUSBPSU_TRB_CTRL_ISP_IMI);
+
+
+ Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+ Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length);
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertNonvoid(Params != NULL);
+ Params->Param0 = 0U;
+ Params->Param1 = (UINTPTR)TrbPtr;
+
+ RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction,
+ XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+ if (RetVal != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+ Ept->UsbEpNum,
+ Ept->Direction);
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Stalls an Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param EpNum is USB endpoint number.
+* @param Dir is direction.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+ u8 PhyEpNum;
+ struct XUsbPsu_Ep *Ept = NULL;
+ struct XUsbPsu_EpParams *Params;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Epnum <= (u8)16U);
+ Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(Epnum, Dir);
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertVoid(Params != NULL);
+
+ (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+ XUSBPSU_DEPCMD_SETSTALL, Params);
+
+ Ept->EpStatus |= XUSBPSU_EP_STALL;
+}
+
+/****************************************************************************/
+/**
+* Clears Stall on an Endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param EpNum is USB endpoint number.
+* @param Dir is direction.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+ u8 PhyEpNum;
+ struct XUsbPsu_Ep *Ept = NULL;
+ struct XUsbPsu_EpParams *Params;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Epnum <= (u8)16U);
+ Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(Epnum, Dir);
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ Params = XUsbPsu_GetEpParams(InstancePtr);
+ Xil_AssertVoid(Params != NULL);
+
+ (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+ XUSBPSU_DEPCMD_CLEARSTALL, Params);
+
+ Ept->EpStatus &= ~XUSBPSU_EP_STALL;
+}
+
+/****************************************************************************/
+/**
+* Sets an user handler to be called after data is sent/received by an Endpoint
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param EpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param Handler is user handler to be called.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 Epnum,
+ u8 Dir, void (*Handler)(void *, u32, u32))
+{
+ u8 PhyEpNum;
+ struct XUsbPsu_Ep *Ept;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Epnum <= (u8)16U);
+ Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(Epnum, Dir);
+ Ept = &InstancePtr->eps[PhyEpNum];
+ Ept->Handler = Handler;
+}
+
+/****************************************************************************/
+/**
+* Returns status of endpoint - Stalled or not
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param EpNum is USB endpoint number.
+* @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return
+* 1 - if stalled
+* 0 - if not stalled
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+ u8 PhyEpNum;
+ struct XUsbPsu_Ep *Ept;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Epnum <= (u8)16U);
+ Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+ PhyEpNum = PhysicalEp(Epnum, Dir);
+ Ept = &InstancePtr->eps[PhyEpNum];
+
+ return (s32)(!!(Ept->EpStatus & XUSBPSU_EP_STALL));
+}
+
+/****************************************************************************/
+/**
+* Checks the Data Phase and calls user Endpoint handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is a pointer to the Endpoint event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Ep *Ept;
+ struct XUsbPsu_Trb *TrbPtr;
+ u32 Length;
+ u32 Epnum;
+ u8 Dir;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Event != NULL);
+
+ Epnum = Event->Epnumber;
+ Ept = &InstancePtr->eps[Epnum];
+ Dir = Ept->Direction;
+ TrbPtr = &Ept->EpTrb;
+ Xil_AssertVoid(TrbPtr != NULL);
+
+ Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+ Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK;
+
+ if (Length == 0U) {
+ Ept->BytesTxed = Ept->RequestedBytes;
+ } else {
+ if (Dir == XUSBPSU_EP_DIR_IN) {
+ Ept->BytesTxed = Ept->RequestedBytes - Length;
+ } else if (Dir == XUSBPSU_EP_DIR_OUT) {
+ if (Ept->UnalignedTx == 1U) {
+ Ept->BytesTxed = Ept->RequestedBytes;
+ Ept->UnalignedTx = 0U;
+ }
+ }
+ }
+
+ if (Dir == XUSBPSU_EP_DIR_OUT) {
+ /* Invalidate Cache */
+ Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed);
+ }
+
+ if (Ept->Handler != NULL) {
+ Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed);
+ }
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h
new file mode 100644
index 0000000000..2998378621
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h
@@ -0,0 +1,184 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_endpoint.h
+* @addtogroup usbpsu_v1_0
+* @{
+ *
+ * This is an internal file containing the definitions for endpoints. It is
+ * included by the xusbps_endpoint.c which is implementing the endpoint
+ * functions and by xusbps_intr.c.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.0 sg 06/06/16 First release
+ *
+ *
+ ******************************************************************************/
+#ifndef XUSBPSU_ENDPOINT_H
+#define XUSBPSU_ENDPOINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xusbpsu.h"
+#include "xil_types.h"
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Device Generic Command Register */
+#define XUSBPSU_DGCMD_SET_LMP 0x00000001U
+#define XUSBPSU_DGCMD_SET_PERIODIC_PAR 0x00000002U
+#define XUSBPSU_DGCMD_XMIT_FUNCTION 0x00000003U
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x00000004U
+#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x00000005U
+
+#define XUSBPSU_DGCMD_SELECTED_FIFO_FLUSH 0x00000009U
+#define XUSBPSU_DGCMD_ALL_FIFO_FLUSH 0x0000000aU
+#define XUSBPSU_DGCMD_SET_ENDPOINT_NRDY 0x0000000cU
+#define XUSBPSU_DGCMD_RUN_SOC_BUS_LOOPBACK 0x00000010U
+
+#define XUSBPSU_DGCMD_STATUS(n) (((u32)(n) >> 15) & 1)
+#define XUSBPSU_DGCMD_CMDACT (0x00000001U << 10)
+#define XUSBPSU_DGCMD_CMDIOC (0x00000001U << 8)
+
+/* Device Generic Command Parameter Register */
+#define XUSBPSU_DGCMDPAR_FORCE_LINKPM_ACCEPT (0x00000001U << 0)
+#define XUSBPSU_DGCMDPAR_FIFO_NUM(n) ((u32)(n) << 0)
+#define XUSBPSU_DGCMDPAR_RX_FIFO (0x00000000U << 5)
+#define XUSBPSU_DGCMDPAR_TX_FIFO (0x00000001U << 5)
+#define XUSBPSU_DGCMDPAR_LOOPBACK_DIS (0x00000000U << 0)
+#define XUSBPSU_DGCMDPAR_LOOPBACK_ENA (0x00000001U << 0)
+
+/* Device Endpoint Command Register */
+#define XUSBPSU_DEPCMD_PARAM_SHIFT 16U
+#define XUSBPSU_DEPCMD_PARAM(x) ((u32)(x) << XUSBPSU_DEPCMD_PARAM_SHIFT)
+#define XUSBPSU_DEPCMD_GET_RSC_IDX(x) (((u32)(x) >> XUSBPSU_DEPCMD_PARAM_SHIFT) & \
+ (u32)0x0000007fU)
+#define XUSBPSU_DEPCMD_STATUS(x) (((u32)(x) >> 12) & (u32)0xF)
+#define XUSBPSU_DEPCMD_HIPRI_FORCERM (0x00000001U << 11)
+#define XUSBPSU_DEPCMD_CMDACT (0x00000001U << 10)
+#define XUSBPSU_DEPCMD_CMDIOC (0x00000001U << 8)
+
+#define XUSBPSU_DEPCMD_DEPSTARTCFG 0x00000009U
+#define XUSBPSU_DEPCMD_ENDTRANSFER 0x00000008U
+#define XUSBPSU_DEPCMD_UPDATETRANSFER 0x00000007U
+#define XUSBPSU_DEPCMD_STARTTRANSFER 0x00000006U
+#define XUSBPSU_DEPCMD_CLEARSTALL 0x00000005U
+#define XUSBPSU_DEPCMD_SETSTALL 0x00000004U
+#define XUSBPSU_DEPCMD_GETEPSTATE 0x00000003U
+#define XUSBPSU_DEPCMD_SETTRANSFRESOURCE 0x00000002U
+#define XUSBPSU_DEPCMD_SETEPCONFIG 0x00000001U
+
+/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
+#define XUSBPSU_DALEPENA_EP(n) (0x00000001U << (n))
+
+#define XUSBPSU_DEPCFG_INT_NUM(n) ((u32)(n) << 0)
+#define XUSBPSU_DEPCFG_XFER_COMPLETE_EN (0x00000001U << 8)
+#define XUSBPSU_DEPCFG_XFER_IN_PROGRESS_EN (0x00000001U << 9)
+#define XUSBPSU_DEPCFG_XFER_NOT_READY_EN (0x00000001U << 10)
+#define XUSBPSU_DEPCFG_FIFO_ERROR_EN (0x00000001U << 11)
+#define XUSBPSU_DEPCFG_STREAM_EVENT_EN (0x00000001U << 13)
+#define XUSBPSU_DEPCFG_BINTERVAL_M1(n) ((u32)(n) << 16)
+#define XUSBPSU_DEPCFG_STREAM_CAPABLE (0x00000001U << 24)
+#define XUSBPSU_DEPCFG_EP_NUMBER(n) ((u32)(n) << 25)
+#define XUSBPSU_DEPCFG_BULK_BASED (0x00000001U << 30)
+#define XUSBPSU_DEPCFG_FIFO_BASED (0x00000001U << 31)
+
+/* DEPCFG parameter 0 */
+#define XUSBPSU_DEPCFG_EP_TYPE(n) ((u32)(n) << 1)
+#define XUSBPSU_DEPCFG_MAX_PACKET_SIZE(n) ((u32)(n) << 3)
+#define XUSBPSU_DEPCFG_FIFO_NUMBER(n) ((u32)(n) << 17)
+#define XUSBPSU_DEPCFG_BURST_SIZE(n) ((u32)(n) << 22)
+#define XUSBPSU_DEPCFG_DATA_SEQ_NUM(n) ((u32)(n) << 26)
+/* This applies for core versions earlier than 1.94a */
+#define XUSBPSU_DEPCFG_IGN_SEQ_NUM (0x00000001U << 31)
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DEPCFG_ACTION_INIT (0x00000000U << 30)
+#define XUSBPSU_DEPCFG_ACTION_RESTORE (0x00000001U << 30)
+#define XUSBPSU_DEPCFG_ACTION_MODIFY (0x00000002U << 30)
+
+/* DEPXFERCFG parameter 0 */
+#define XUSBPSU_DEPXFERCFG_NUM_XFER_RES(n) ((u32)(n) & (u32)0xffff)
+
+#define XUSBPSU_DEPCMD_TYPE_BULK 2U
+#define XUSBPSU_DEPCMD_TYPE_INTR 3U
+
+/* TRB Length, PCM and Status */
+#define XUSBPSU_TRB_SIZE_MASK (0x00ffffffU)
+#define XUSBPSU_TRB_SIZE_LENGTH(n) ((u32)(n) & XUSBPSU_TRB_SIZE_MASK)
+#define XUSBPSU_TRB_SIZE_PCM1(n) (((u32)(n) & (u32)0x03) << 24)
+#define XUSBPSU_TRB_SIZE_TRBSTS(n) (((u32)(n) & ((u32)0x0f << 28)) >> 28)
+
+#define XUSBPSU_TRBSTS_OK 0U
+#define XUSBPSU_TRBSTS_MISSED_ISOC 1U
+#define XUSBPSU_TRBSTS_SETUP_PENDING 2U
+#define XUSBPSU_TRB_STS_XFER_IN_PROG 4U
+
+/* TRB Control */
+#define XUSBPSU_TRB_CTRL_HWO ((u32)0x00000001U << 0)
+#define XUSBPSU_TRB_CTRL_LST ((u32)0x00000001U << 1)
+#define XUSBPSU_TRB_CTRL_CHN ((u32)0x00000001U << 2)
+#define XUSBPSU_TRB_CTRL_CSP ((u32)0x00000001U << 3)
+#define XUSBPSU_TRB_CTRL_TRBCTL(n) (((u32)(n) & (u32)0x3f) << 4)
+#define XUSBPSU_TRB_CTRL_ISP_IMI (0x00000001U << 10)
+#define XUSBPSU_TRB_CTRL_IOC (0x00000001U << 11)
+#define XUSBPSU_TRB_CTRL_SID_SOFN(n) (((u32)(n) & (u32)0xffff) << 14)
+
+#define XUSBPSU_TRBCTL_NORMAL XUSBPSU_TRB_CTRL_TRBCTL(1)
+#define XUSBPSU_TRBCTL_CONTROL_SETUP XUSBPSU_TRB_CTRL_TRBCTL(2)
+#define XUSBPSU_TRBCTL_CONTROL_STATUS2 XUSBPSU_TRB_CTRL_TRBCTL(3)
+#define XUSBPSU_TRBCTL_CONTROL_STATUS3 XUSBPSU_TRB_CTRL_TRBCTL(4)
+#define XUSBPSU_TRBCTL_CONTROL_DATA XUSBPSU_TRB_CTRL_TRBCTL(5)
+#define XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST XUSBPSU_TRB_CTRL_TRBCTL(6)
+#define XUSBPSU_TRBCTL_ISOCHRONOUS XUSBPSU_TRB_CTRL_TRBCTL(7)
+#define XUSBPSU_TRBCTL_LINK_TRB XUSBPSU_TRB_CTRL_TRBCTL(8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPSU_ENDPOINT_H */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c
new file mode 100644
index 0000000000..41a9b8c7ac
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xusbpsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUsbPsu_Config XUsbPsu_ConfigTable[] =
+{
+ {
+ XPAR_PSU_USB_0_DEVICE_ID,
+ XPAR_PSU_USB_0_BASEADDR
+ }
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h
new file mode 100644
index 0000000000..db612b00fc
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h
@@ -0,0 +1,363 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_hw.h
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.0 sg 06/06/16 First release
+*
+*
+*
+*****************************************************************************/
+
+#ifndef XUSBPSU_HW_H /* Prevent circular inclusions */
+#define XUSBPSU_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+/************************** Constant Definitions ****************************/
+
+/**@name Register offsets
+ *
+ * The following constants provide access to each of the registers of the
+ * USBPSU device.
+ * @{
+ */
+
+/**/
+#define XUSBPSU_PORTSC_30 0x430
+#define XUSBPSU_PORTMSC_30 0x434
+
+/* XUSBPSU registers memory space boundries */
+#define XUSBPSU_GLOBALS_REGS_START 0xc100
+#define XUSBPSU_GLOBALS_REGS_END 0xc6ff
+#define XUSBPSU_DEVICE_REGS_START 0xc700
+#define XUSBPSU_DEVICE_REGS_END 0xcbff
+#define XUSBPSU_OTG_REGS_START 0xcc00
+#define XUSBPSU_OTG_REGS_END 0xccff
+
+/* Global Registers */
+#define XUSBPSU_GSBUSCFG0 0xc100
+#define XUSBPSU_GSBUSCFG1 0xc104
+#define XUSBPSU_GTXTHRCFG 0xc108
+#define XUSBPSU_GRXTHRCFG 0xc10c
+#define XUSBPSU_GCTL 0xc110
+#define XUSBPSU_GEVTEN 0xc114
+#define XUSBPSU_GSTS 0xc118
+#define XUSBPSU_GSNPSID 0xc120
+#define XUSBPSU_GGPIO 0xc124
+#define XUSBPSU_GUID 0xc128
+#define XUSBPSU_GUCTL 0xc12c
+#define XUSBPSU_GBUSERRADDR0 0xc130
+#define XUSBPSU_GBUSERRADDR1 0xc134
+#define XUSBPSU_GPRTBIMAP0 0xc138
+#define XUSBPSU_GPRTBIMAP1 0xc13c
+#define XUSBPSU_GHWPARAMS0_OFFSET 0xc140U
+#define XUSBPSU_GHWPARAMS1_OFFSET 0xc144U
+#define XUSBPSU_GHWPARAMS2_OFFSET 0xc148U
+#define XUSBPSU_GHWPARAMS3_OFFSET 0xc14cU
+#define XUSBPSU_GHWPARAMS4_OFFSET 0xc150U
+#define XUSBPSU_GHWPARAMS5_OFFSET 0xc154U
+#define XUSBPSU_GHWPARAMS6_OFFSET 0xc158U
+#define XUSBPSU_GHWPARAMS7_OFFSET 0xc15cU
+#define XUSBPSU_GDBGFIFOSPACE 0xc160
+#define XUSBPSU_GDBGLTSSM 0xc164
+#define XUSBPSU_GPRTBIMAP_HS0 0xc180
+#define XUSBPSU_GPRTBIMAP_HS1 0xc184
+#define XUSBPSU_GPRTBIMAP_FS0 0xc188
+#define XUSBPSU_GPRTBIMAP_FS1 0xc18c
+
+#define XUSBPSU_GUSB2PHYCFG(n) ((u32)0xc200 + ((u32)(n) * (u32)0x04))
+#define XUSBPSU_GUSB2I2CCTL(n) ((u32)0xc240 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GUSB2PHYACC(n) ((u32)0xc280 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GUSB3PIPECTL(n) ((u32)0xc2c0 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GTXFIFOSIZ(n) ((u32)0xc300 + ((u32)(n) * (u32)0x04))
+#define XUSBPSU_GRXFIFOSIZ(n) ((u32)0xc380 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GEVNTADRLO(n) ((u32)0xc400 + ((u32)(n) * (u32)0x10))
+#define XUSBPSU_GEVNTADRHI(n) ((u32)0xc404 + ((u32)(n) * (u32)0x10))
+#define XUSBPSU_GEVNTSIZ(n) ((u32)0xc408 + ((u32)(n) * (u32)0x10))
+#define XUSBPSU_GEVNTCOUNT(n) ((u32)0xc40c + ((u32)(n) * (u32)0x10))
+
+#define XUSBPSU_GHWPARAMS8 0x0000c600U
+
+/* Device Registers */
+#define XUSBPSU_DCFG 0x0000c700U
+#define XUSBPSU_DCTL 0x0000c704U
+#define XUSBPSU_DEVTEN 0x0000c708U
+#define XUSBPSU_DSTS 0x0000c70cU
+#define XUSBPSU_DGCMDPAR 0x0000c710U
+#define XUSBPSU_DGCMD 0x0000c714U
+#define XUSBPSU_DALEPENA 0x0000c720U
+#define XUSBPSU_DEPCMDPAR2(n) ((u32)0xc800 + ((u32)n * (u32)0x10))
+#define XUSBPSU_DEPCMDPAR1(n) ((u32)0xc804 + ((u32)n * (u32)0x10))
+#define XUSBPSU_DEPCMDPAR0(n) ((u32)0xc808 + ((u32)n * (u32)0x10))
+#define XUSBPSU_DEPCMD(n) ((u32)0xc80c + ((u32)n * (u32)0x10))
+
+/* OTG Registers */
+#define XUSBPSU_OCFG 0x0000cc00U
+#define XUSBPSU_OCTL 0x0000cc04U
+#define XUSBPSU_OEVT 0xcc08U
+#define XUSBPSU_OEVTEN 0xcc0CU
+#define XUSBPSU_OSTS 0xcc10U
+
+/* Bit fields */
+
+/* Global Configuration Register */
+#define XUSBPSU_GCTL_PWRDNSCALE(n) ((n) << 19)
+#define XUSBPSU_GCTL_U2RSTECN (1 << 16)
+#define XUSBPSU_GCTL_RAMCLKSEL(x) (((x) & XUSBPSU_GCTL_CLK_MASK) << 6)
+#define XUSBPSU_GCTL_CLK_BUS (0U)
+#define XUSBPSU_GCTL_CLK_PIPE (1U)
+#define XUSBPSU_GCTL_CLK_PIPEHALF (2U)
+#define XUSBPSU_GCTL_CLK_MASK (3U)
+
+#define XUSBPSU_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
+#define XUSBPSU_GCTL_PRTCAPDIR(n) ((n) << 12)
+#define XUSBPSU_GCTL_PRTCAP_HOST 1U
+#define XUSBPSU_GCTL_PRTCAP_DEVICE 2U
+#define XUSBPSU_GCTL_PRTCAP_OTG 3U
+
+#define XUSBPSU_GCTL_CORESOFTRESET (0x00000001U << 11)
+#define XUSBPSU_GCTL_SOFITPSYNC (0x00000001U << 10)
+#define XUSBPSU_GCTL_SCALEDOWN(n) ((u32)(n) << 4)
+#define XUSBPSU_GCTL_SCALEDOWN_MASK XUSBPSU_GCTL_SCALEDOWN(3)
+#define XUSBPSU_GCTL_DISSCRAMBLE (0x00000001U << 3)
+#define XUSBPSU_GCTL_U2EXIT_LFPS (0x00000001U << 2)
+#define XUSBPSU_GCTL_GBLHIBERNATIONEN (0x00000001U << 1)
+#define XUSBPSU_GCTL_DSBLCLKGTNG (0x00000001U << 0)
+
+/* Global Status Register Device Interrupt Mask */
+#define XUSBPSU_GSTS_DEVICE_IP_MASK 0x00000040
+
+/* Global USB2 PHY Configuration Register */
+#define XUSBPSU_GUSB2PHYCFG_PHYSOFTRST (0x00000001U << 31)
+#define XUSBPSU_GUSB2PHYCFG_SUSPHY (0x00000001U << 6)
+
+/* Global USB3 PIPE Control Register */
+#define XUSBPSU_GUSB3PIPECTL_PHYSOFTRST (0x00000001U << 31)
+#define XUSBPSU_GUSB3PIPECTL_SUSPHY (0x00000001U << 17)
+
+/* Global TX Fifo Size Register */
+#define XUSBPSU_GTXFIFOSIZ_TXFDEF(n) ((u32)(n) & (u32)0xffffU)
+#define XUSBPSU_GTXFIFOSIZ_TXFSTADDR(n) ((u32)(n) & 0xffff0000U)
+
+/* Global Event Size Registers */
+#define XUSBPSU_GEVNTSIZ_INTMASK ((u32)0x00000001U << 31U)
+#define XUSBPSU_GEVNTSIZ_SIZE(n) ((u32)(n) & (u32)0xffffU)
+
+/* Global HWPARAMS1 Register */
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT(n) (((u32)(n) & ((u32)3 << 24)) >> 24)
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_NO 0U
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK 1U
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB 2U
+#define XUSBPSU_GHWPARAMS1_PWROPT(n) ((u32)(n) << 24)
+#define XUSBPSU_GHWPARAMS1_PWROPT_MASK XUSBPSU_GHWPARAMS1_PWROPT(3)
+
+/* Global HWPARAMS4 Register */
+#define XUSBPSU_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((u32)(n) & ((u32)0x0f << 13)) >> 13)
+#define XUSBPSU_MAX_HIBER_SCRATCHBUFS 15U
+
+/* Device Configuration Register */
+#define XUSBPSU_DCFG_DEVADDR(addr) ((u32)(addr) << 3)
+#define XUSBPSU_DCFG_DEVADDR_MASK XUSBPSU_DCFG_DEVADDR(0x7f)
+
+#define XUSBPSU_DCFG_SPEED_MASK 7U
+#define XUSBPSU_DCFG_SUPERSPEED 4U
+#define XUSBPSU_DCFG_HIGHSPEED 0U
+#define XUSBPSU_DCFG_FULLSPEED2 1U
+#define XUSBPSU_DCFG_LOWSPEED 2U
+#define XUSBPSU_DCFG_FULLSPEED1 3U
+
+#define XUSBPSU_DCFG_LPM_CAP (0x00000001U << 22U)
+
+/* Device Control Register */
+#define XUSBPSU_DCTL_RUN_STOP (0x00000001U << 31U)
+#define XUSBPSU_DCTL_CSFTRST ((u32)0x00000001U << 30U)
+#define XUSBPSU_DCTL_LSFTRST (0x00000001U << 29U)
+
+#define XUSBPSU_DCTL_HIRD_THRES_MASK (0x0000001fU << 24U)
+#define XUSBPSU_DCTL_HIRD_THRES(n) ((u32)(n) << 24)
+
+#define XUSBPSU_DCTL_APPL1RES (0x00000001U << 23)
+
+/* These apply for core versions 1.87a and earlier */
+#define XUSBPSU_DCTL_TRGTULST_MASK (0x0000000fU << 17)
+#define XUSBPSU_DCTL_TRGTULST(n) ((u32)(n) << 17)
+#define XUSBPSU_DCTL_TRGTULST_U2 (XUSBPSU_DCTL_TRGTULST(2))
+#define XUSBPSU_DCTL_TRGTULST_U3 (XUSBPSU_DCTL_TRGTULST(3))
+#define XUSBPSU_DCTL_TRGTULST_SS_DIS (XUSBPSU_DCTL_TRGTULST(4))
+#define XUSBPSU_DCTL_TRGTULST_RX_DET (XUSBPSU_DCTL_TRGTULST(5))
+#define XUSBPSU_DCTL_TRGTULST_SS_INACT (XUSBPSU_DCTL_TRGTULST(6))
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DCTL_KEEP_CONNECT (0x00000001U << 19)
+#define XUSBPSU_DCTL_L1_HIBER_EN (0x00000001U << 18)
+#define XUSBPSU_DCTL_CRS (0x00000001U << 17)
+#define XUSBPSU_DCTL_CSS (0x00000001U << 16)
+
+#define XUSBPSU_DCTL_INITU2ENA (0x00000001U << 12)
+#define XUSBPSU_DCTL_ACCEPTU2ENA (0x00000001U << 11)
+#define XUSBPSU_DCTL_INITU1ENA (0x00000001U << 10)
+#define XUSBPSU_DCTL_ACCEPTU1ENA (0x00000001U << 9)
+#define XUSBPSU_DCTL_TSTCTRL_MASK (0x0000000fU << 1)
+
+#define XUSBPSU_DCTL_ULSTCHNGREQ_MASK (0x0000000fU << 5)
+#define XUSBPSU_DCTL_ULSTCHNGREQ(n) (((u32)(n) << 5) & XUSBPSU_DCTL_ULSTCHNGREQ_MASK)
+
+#define XUSBPSU_DCTL_ULSTCHNG_NO_ACTION (XUSBPSU_DCTL_ULSTCHNGREQ(0))
+#define XUSBPSU_DCTL_ULSTCHNG_SS_DISABLED (XUSBPSU_DCTL_ULSTCHNGREQ(4))
+#define XUSBPSU_DCTL_ULSTCHNG_RX_DETECT (XUSBPSU_DCTL_ULSTCHNGREQ(5))
+#define XUSBPSU_DCTL_ULSTCHNG_SS_INACTIVE (XUSBPSU_DCTL_ULSTCHNGREQ(6))
+#define XUSBPSU_DCTL_ULSTCHNG_RECOVERY (XUSBPSU_DCTL_ULSTCHNGREQ(8))
+#define XUSBPSU_DCTL_ULSTCHNG_COMPLIANCE (XUSBPSU_DCTL_ULSTCHNGREQ(10))
+#define XUSBPSU_DCTL_ULSTCHNG_LOOPBACK (XUSBPSU_DCTL_ULSTCHNGREQ(11))
+
+/* Device Event Enable Register */
+#define XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN ((u32)0x00000001 << 12)
+#define XUSBPSU_DEVTEN_EVNTOVERFLOWEN ((u32)0x00000001 << 11)
+#define XUSBPSU_DEVTEN_CMDCMPLTEN ((u32)0x00000001 << 10)
+#define XUSBPSU_DEVTEN_ERRTICERREN ((u32)0x00000001 << 9)
+#define XUSBPSU_DEVTEN_SOFEN ((u32)0x00000001 << 7)
+#define XUSBPSU_DEVTEN_EOPFEN ((u32)0x00000001 << 6)
+#define XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN ((u32)0x00000001 << 5)
+#define XUSBPSU_DEVTEN_WKUPEVTEN ((u32)0x00000001 << 4)
+#define XUSBPSU_DEVTEN_ULSTCNGEN ((u32)0x00000001 << 3)
+#define XUSBPSU_DEVTEN_CONNECTDONEEN ((u32)0x00000001 << 2)
+#define XUSBPSU_DEVTEN_USBRSTEN ((u32)0x00000001 << 1)
+#define XUSBPSU_DEVTEN_DISCONNEVTEN ((u32)0x00000001 << 0)
+
+/* Device Status Register */
+#define XUSBPSU_DSTS_DCNRD (0x00000001U << 29)
+
+/* This applies for core versions 1.87a and earlier */
+#define XUSBPSU_DSTS_PWRUPREQ (0x00000001U << 24)
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DSTS_RSS (0x00000001U << 25)
+#define XUSBPSU_DSTS_SSS (0x00000001U << 24)
+
+#define XUSBPSU_DSTS_COREIDLE (0x00000001U << 23)
+#define XUSBPSU_DSTS_DEVCTRLHLT (0x00000001U << 22)
+
+#define XUSBPSU_DSTS_USBLNKST_MASK (0x0000000fU << 18)
+#define XUSBPSU_DSTS_USBLNKST(n) (((u32)(n) & XUSBPSU_DSTS_USBLNKST_MASK) >> 18)
+
+#define XUSBPSU_DSTS_RXFIFOEMPTY (0x00000001U << 17)
+
+#define XUSBPSU_DSTS_SOFFN_MASK (0x00003fffU << 3)
+#define XUSBPSU_DSTS_SOFFN(n) (((u32)(n) & XUSBPSU_DSTS_SOFFN_MASK) >> 3)
+
+#define XUSBPSU_DSTS_CONNECTSPD (0x00000007U << 0)
+
+#define XUSBPSU_DSTS_SUPERSPEED (4U << 0)
+#define XUSBPSU_DSTS_HIGHSPEED (0U << 0)
+#define XUSBPSU_DSTS_FULLSPEED2 (1U << 0)
+#define XUSBPSU_DSTS_LOWSPEED (2U << 0)
+#define XUSBPSU_DSTS_FULLSPEED1 (3U << 0)
+
+/*Portpmsc 3.0 bit field*/
+#define XUSBPSU_PORTMSC_30_FLA_MASK (1U << 16)
+#define XUSBPSU_PORTMSC_30_U2_TIMEOUT_MASK (0xffU << 8)
+#define XUSBPSU_PORTMSC_30_U2_TIMEOUT_SHIFT (8U)
+#define XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK (0xffU << 0)
+#define XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT (0U)
+
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* Read a register of the USBPS8 device. This macro provides register
+* access to all registers using the register offsets defined above.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Offset is the offset of the register to read.
+*
+* @return The contents of the register.
+*
+* @note C-style Signature:
+* u32 XUsbPsu_ReadReg(struct XUsbPsu *InstancePtr, u32 Offset);
+*
+******************************************************************************/
+#define XUsbPsu_ReadReg(InstancePtr, Offset) \
+ Xil_In32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset))
+
+/*****************************************************************************/
+/**
+*
+* Write a register of the USBPS8 device. This macro provides
+* register access to all registers using the register offsets defined above.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param RegOffset is the offset of the register to write.
+* @param Data is the value to write to the register.
+*
+* @return None.
+*
+* @note C-style Signature:
+* void XUsbPsu_WriteReg(struct XUsbPsu *InstancePtr,
+* u32 Offset,u32 Data)
+*
+******************************************************************************/
+#define XUsbPsu_WriteReg(InstancePtr, Offset, Data) \
+ Xil_Out32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro. */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c
new file mode 100644
index 0000000000..85baab0f82
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c
@@ -0,0 +1,434 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_intr.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 sg 06/06/16 First release
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+* Endpoint interrupt handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is endpoint Event occured in the core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Epevt *Event)
+{
+ struct XUsbPsu_Ep *Ept;
+ u32 Epnum;
+
+ Epnum = Event->Epnumber;
+ Ept = &InstancePtr->eps[Epnum];
+
+ if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == (u32)0U) {
+ return;
+ }
+
+ if ((Epnum == (u32)0) || (Epnum == (u32)1)) {
+ XUsbPsu_Ep0Intr(InstancePtr, Event);
+ return;
+ }
+
+ /* Handle other end point events */
+ switch (Event->Endpoint_Event) {
+ case XUSBPSU_DEPEVT_XFERCOMPLETE:
+ XUsbPsu_EpXferComplete(InstancePtr, Event);
+ break;
+
+ case XUSBPSU_DEPEVT_XFERNOTREADY:
+ break;
+
+ default:
+ /* Made for Misra-C Compliance. */
+ break;
+ }
+}
+
+/****************************************************************************/
+/**
+* Disconnect Interrupt handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_INITU1ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ RegVal &= ~XUSBPSU_DCTL_INITU2ENA;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+ InstancePtr->IsConfigDone = 0U;
+ InstancePtr->Speed = XUSBPSU_SPEED_UNKNOWN;
+}
+
+/****************************************************************************/
+/**
+* Reset Interrupt handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+ u32 Index;
+
+ InstancePtr->State = XUSBPSU_STATE_DEFAULT;
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+ RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+ InstancePtr->TestMode = 0U;
+
+ for (Index = 0U; Index < (InstancePtr->NumInEps + InstancePtr->NumOutEps);
+ Index++)
+ {
+ InstancePtr->eps[Index].EpStatus = 0U;
+ }
+
+ InstancePtr->IsConfigDone = 0U;
+
+ /* Reset device address to zero */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+ RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+}
+
+/****************************************************************************/
+/**
+* Connection Done Interrupt handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr)
+{
+ u32 RegVal;
+ u16 Size;
+ u8 Speed;
+
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
+ Speed = (u8)(RegVal & XUSBPSU_DSTS_CONNECTSPD);
+ InstancePtr->Speed = Speed;
+
+ switch (Speed) {
+ case XUSBPSU_DCFG_SUPERSPEED:
+#ifdef XUSBPSU_DEBUG
+ xil_printf("Super Speed\r\n");
+#endif
+ Size = 512U;
+ InstancePtr->Speed = XUSBPSU_SPEED_SUPER;
+ break;
+
+ case XUSBPSU_DCFG_HIGHSPEED:
+#ifdef XUSBPSU_DEBUG
+ xil_printf("High Speed\r\n");
+#endif
+ Size = 64U;
+ InstancePtr->Speed = XUSBPSU_SPEED_HIGH;
+ break;
+
+ case XUSBPSU_DCFG_FULLSPEED2:
+ case XUSBPSU_DCFG_FULLSPEED1:
+#ifdef XUSBPSU_DEBUG
+ xil_printf("Full Speed\r\n");
+#endif
+ Size = 64U;
+ InstancePtr->Speed = XUSBPSU_SPEED_FULL;
+ break;
+
+ case XUSBPSU_DCFG_LOWSPEED:
+#ifdef XUSBPSU_DEBUG
+ xil_printf("Low Speed\r\n");
+#endif
+ Size = 64U;
+ InstancePtr->Speed = XUSBPSU_SPEED_LOW;
+ break;
+ default :
+ Size = 64U;
+ break;
+ }
+
+ (void)XUsbPsu_EnableControlEp(InstancePtr, Size);
+ (void)XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Link Status Change Interrupt handler.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param EvtInfo is Event information.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr, u32 EvtInfo)
+{
+ u32 State = EvtInfo & (u32)XUSBPSU_LINK_STATE_MASK;
+ InstancePtr->LinkState = (u8)State;
+}
+
+/****************************************************************************/
+/**
+* Interrupt handler for device specific events.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is the Device Event occured in core.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr,
+ const struct XUsbPsu_Event_Devt *Event)
+{
+
+ switch (Event->Type) {
+ case XUSBPSU_DEVICE_EVENT_DISCONNECT:
+ XUsbPsu_DisconnectIntr(InstancePtr);
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_RESET:
+ XUsbPsu_ResetIntr(InstancePtr);
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_CONNECT_DONE:
+ XUsbPsu_ConnDoneIntr(InstancePtr);
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_WAKEUP:
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_HIBER_REQ:
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE:
+ XUsbPsu_LinkStsChangeIntr(InstancePtr,
+ Event->Event_Info);
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_EOPF:
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_SOF:
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_ERRATIC_ERROR:
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_CMD_CMPL:
+ break;
+
+ case XUSBPSU_DEVICE_EVENT_OVERFLOW:
+ break;
+
+ default:
+ /* Made for Misra-C Compliance. */
+ break;
+ }
+}
+
+/****************************************************************************/
+/**
+* Processes an Event entry in Event Buffer.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @param Event is the Event entry.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_EventHandler(struct XUsbPsu *InstancePtr,
+ const union XUsbPsu_Event *Event)
+{
+
+ if (Event->Type.Is_DevEvt == 0U) {
+ /* End point Specific Event */
+ XUsbPsu_EpInterrupt(InstancePtr, &Event->Epevt);
+ return;
+ }
+
+ switch (Event->Type.Type) {
+ case XUSBPSU_EVENT_TYPE_DEV:
+ /* Device Specific Event */
+ XUsbPsu_DevInterrupt(InstancePtr, &Event->Devt);
+ break;
+ /* Carkit and I2C events not supported now */
+ default:
+ /* Made for Misra-C Compliance. */
+ break;
+ }
+}
+
+/****************************************************************************/
+/**
+* Processes events in an Event Buffer.
+*
+* @param InstancePtr is a pointer to the XUsbPsu instance.
+* @bus Event buffer number.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr)
+{
+ struct XUsbPsu_EvtBuffer *Evt;
+ union XUsbPsu_Event Event = {0};
+
+ Evt = &InstancePtr->Evt;
+
+ Xil_DCacheInvalidateRange((INTPTR)Evt->BuffAddr,
+ (u32)XUSBPSU_EVENT_BUFFERS_SIZE);
+
+ while (Evt->Count > 0) {
+ Event.Raw = *(UINTPTR *)(Evt->BuffAddr + Evt->Offset);
+
+ /*
+ * Process the event received
+ */
+ XUsbPsu_EventHandler(InstancePtr, &Event);
+
+ Evt->Offset = (Evt->Offset + 4U) % XUSBPSU_EVENT_BUFFERS_SIZE;
+ Evt->Count -= 4;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 4U);
+ }
+
+ Evt->Flags &= ~XUSBPSU_EVENT_PENDING;
+}
+
+/****************************************************************************/
+/**
+* Main Interrupt Handler.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr)
+{
+ struct XUsbPsu *InstancePtr;
+ struct XUsbPsu_EvtBuffer *Evt;
+ u32 Count;
+ u32 RegVal;
+
+ InstancePtr = XUsbPsuInstancePtr;
+
+ Evt = &InstancePtr->Evt;
+
+ Count = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0));
+ Count &= XUSBPSU_GEVNTCOUNT_MASK;
+ /*
+ * As per data book software should only process Events if Event count
+ * is greater than zero.
+ */
+ if (Count == 0U) {
+ return;
+ }
+
+ Evt->Count = Count;
+ Evt->Flags |= XUSBPSU_EVENT_PENDING;
+
+ /* Mask event interrupt */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0));
+ RegVal |= XUSBPSU_GEVNTSIZ_INTMASK;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal);
+
+ /* Processes events in an Event Buffer */
+ XUsbPsu_EventBufferHandler(InstancePtr);
+
+ /* Unmask event interrupt */
+ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0));
+ RegVal &= ~XUSBPSU_GEVNTSIZ_INTMASK;
+ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal);
+}
+
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c
new file mode 100644
index 0000000000..c172c5d697
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_sinit.h
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 sg 06/06/16 First release
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+extern XUsbPsu_Config XUsbPsu_ConfigTable[];
+
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XUsbPsu_Config *XUsbPsu_LookupConfig(u16 DeviceId)
+{
+ XUsbPsu_Config *CfgPtr = NULL;
+ u32 i;
+
+ for (i = 0U; i < (u32)XPAR_XUSBPSU_NUM_INSTANCES; i++) {
+ if (XUsbPsu_ConfigTable[i].DeviceId == DeviceId) {
+ CfgPtr = &XUsbPsu_ConfigTable[i];
+ break;
+ }
+ }
+
+ return (XUsbPsu_Config *)(CfgPtr);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
index 5147be6760..6ea6b192b9 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c
index 33202264db..194aac12ea 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss
index 5a742ad930..76354534a0 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss
@@ -4,7 +4,7 @@
BEGIN OS
PARAMETER OS_NAME = standalone
- PARAMETER OS_VER = 5.4
+ PARAMETER OS_VER = 6.1
PARAMETER PROC_INSTANCE = psu_cortexr5_0
PARAMETER stdin = psu_uart_0
PARAMETER stdout = psu_uart_0
@@ -15,13 +15,12 @@ BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu_cortexr5
PARAMETER DRIVER_VER = 1.1
PARAMETER HW_INSTANCE = psu_cortexr5_0
- PARAMETER extra_compiler_flags = -g -DARMR5 -mfpu=vfpv3-d16
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.5
PARAMETER HW_INSTANCE = psu_acpu_gic
END
@@ -117,31 +116,31 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = sysmonpsu
- PARAMETER DRIVER_VER = 1.0
+ PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = psu_ams
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
PARAMETER HW_INSTANCE = psu_apm_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
PARAMETER HW_INSTANCE = psu_apm_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
PARAMETER HW_INSTANCE = psu_apm_2
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
PARAMETER HW_INSTANCE = psu_apm_5
END
@@ -151,15 +150,9 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = psu_apu
END
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_bbram_0
-END
-
BEGIN DRIVER
PARAMETER DRIVER_NAME = canps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
PARAMETER HW_INSTANCE = psu_can_1
END
@@ -177,7 +170,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = coresightps_dcc
- PARAMETER DRIVER_VER = 1.2
+ PARAMETER DRIVER_VER = 1.3
PARAMETER HW_INSTANCE = psu_coresight_0
END
@@ -201,7 +194,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = csudma
- PARAMETER DRIVER_VER = 1.0
+ PARAMETER DRIVER_VER = 1.1
PARAMETER HW_INSTANCE = psu_csudma
END
@@ -254,8 +247,8 @@ BEGIN DRIVER
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_NAME = ddrcpsu
+ PARAMETER DRIVER_VER = 1.1
PARAMETER HW_INSTANCE = psu_ddrc_0
END
@@ -279,7 +272,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = emacps
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.3
PARAMETER HW_INSTANCE = psu_ethernet_3
END
@@ -375,22 +368,16 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.4
PARAMETER HW_INSTANCE = psu_i2c_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.4
PARAMETER HW_INSTANCE = psu_i2c_1
END
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_iou_s
-END
-
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
@@ -417,13 +404,13 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ipipsu
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_VER = 2.1
PARAMETER HW_INSTANCE = psu_ipi_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ipipsu
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_VER = 2.1
PARAMETER HW_INSTANCE = psu_ipi_2
END
@@ -469,12 +456,6 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = psu_ocm_ram_0
END
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_ocm_ram_1
-END
-
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
@@ -499,6 +480,12 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = psu_pcie_dma
END
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_pcie_low
+END
+
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
@@ -511,15 +498,9 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = psu_pmu_iomodule
END
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_pmu_ram
-END
-
BEGIN DRIVER
PARAMETER DRIVER_NAME = qspipsu
- PARAMETER DRIVER_VER = 1.0
+ PARAMETER DRIVER_VER = 1.3
PARAMETER HW_INSTANCE = psu_qspi_0
END
@@ -535,36 +516,12 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = psu_r5_0_atcm
END
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_r5_0_atcm_lockstep
-END
-
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = psu_r5_0_btcm
END
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_r5_0_btcm_lockstep
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_r5_1_atcm
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_r5_1_btcm
-END
-
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
@@ -579,7 +536,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.5
PARAMETER HW_INSTANCE = psu_rcpu_gic
END
@@ -597,7 +554,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = rtcpsu
- PARAMETER DRIVER_VER = 1.2
+ PARAMETER DRIVER_VER = 1.3
PARAMETER HW_INSTANCE = psu_rtc
END
@@ -609,7 +566,7 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = sdps
- PARAMETER DRIVER_VER = 2.7
+ PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_sd_1
END
@@ -639,43 +596,43 @@ END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
PARAMETER HW_INSTANCE = psu_ttc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
PARAMETER HW_INSTANCE = psu_ttc_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
PARAMETER HW_INSTANCE = psu_ttc_2
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
PARAMETER HW_INSTANCE = psu_ttc_3
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.3
PARAMETER HW_INSTANCE = psu_uart_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.3
PARAMETER HW_INSTANCE = psu_uart_1
END
BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_NAME = usbpsu
+ PARAMETER DRIVER_VER = 1.1
PARAMETER HW_INSTANCE = psu_usb_0
END
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c
index aa923f4f9f..e9d6479165 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c
index a082ce0fda..b478e5d051 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c
index 219b80d7f6..0c8b226fc8 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src/xintc_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src/xintc_g.c
index 85c993d2dd..f44563f9f9 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src/xintc_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src/xintc_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h
index 4dd178f041..8671e3fbe5 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h
index fb9e563395..17fa893704 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c
index 51801c5eb7..0c9c7875de 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v4_1/src/xtmrctr_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v4_1/src/xtmrctr_g.c
index 9f75b97635..464f2099ee 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v4_1/src/xtmrctr_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v4_1/src/xtmrctr_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c
index 1edd414e36..90a346f75b 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.cproject b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.cproject
index dc2b710354..cd548fd9fa 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.cproject
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.cproject
@@ -116,7 +116,7 @@
-
+