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Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM GCC ports to assist with link time optimisation.

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This commit is contained in:
Richard Barry
2019-04-21 20:15:34 +00:00
parent 606845492b
commit 84377442fc
11 changed files with 17 additions and 0 deletions
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2
FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
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@ -205,5 +205,7 @@ number of bits implemented by the interrupt controller. */
#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#endif /* PORTMACRO_H */

2
FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
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@ -202,5 +202,7 @@ number of bits implemented by the interrupt controller. */
#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#endif /* PORTMACRO_H */

2
FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
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@ -107,6 +107,8 @@ extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__((naked)
#define portNOP()
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}
#endif

1
FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
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@ -233,6 +233,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
}
/*-----------------------------------------------------------*/
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}

1
FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
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@ -291,6 +291,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
}
/*-----------------------------------------------------------*/
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}

1
FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
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@ -233,6 +233,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
}
/*-----------------------------------------------------------*/
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}

1
FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
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@ -291,6 +291,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
}
/*-----------------------------------------------------------*/
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}

1
FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
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@ -237,6 +237,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
}
/*-----------------------------------------------------------*/
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}

2
FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
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@ -189,5 +189,7 @@ number of bits implemented by the interrupt controller. */
#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#endif /* PORTMACRO_H */

2
FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
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@ -164,6 +164,8 @@ void vPortTaskUsesFPU( void );
#define portNOP() __asm volatile( "NOP" )
#define portINLINE __inline
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
} /* extern C */
#endif

2
FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h
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@ -144,6 +144,8 @@ not necessary for to use this port. They are defined so the common demo files
#define portFORCE_INLINE inline __attribute__(( always_inline))
#endif
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}
#endif