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Use chacheable RAM in IAR project for MPU_M7_NUCLEO_H743ZI2 project (#193)

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This change updates the IAR project for Nucleo H743ZI2 to use the
cacheable DTC RAM and enables L1 cache. In order to ensure the correct
functioning of cache, the project sets configTEX_S_C_B_SRAM in
FreeRTOSConfig.h to not mark the RAM as shareable.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Gaurav-Aggarwal-AWS
2020-08-09 22:21:44 -07:00
committed by GitHub
parent f3e43556f9
commit 157a7fc39f
3 changed files with 17 additions and 3 deletions
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5
FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Config/FreeRTOSConfig.h
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@ -135,4 +135,9 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
* configTOTAL_MPU_REGIONS correctly. */ * configTOTAL_MPU_REGIONS correctly. */
#define configTOTAL_MPU_REGIONS 16 #define configTOTAL_MPU_REGIONS 16
/* The default TEX,S,C,B setting marks the SRAM as shareable and as a result,
* disables cache. Do not mark the SRAM as shareable because caching is being
* used. TEX=0, S=0, C=1, B=1. */
#define configTEX_S_C_B_SRAM ( 0x03UL )
#endif /* FREERTOS_CONFIG_H */ #endif /* FREERTOS_CONFIG_H */

2
FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewp
View File

@ -782,7 +782,7 @@
</option> </option>
<option> <option>
<name>IlinkIcfFile</name> <name>IlinkIcfFile</name>
<state>$PROJ_DIR$\stm32h743xx_flash.icf</state> <state>$PROJ_DIR$\stm32h743xx_flash_dtcram.icf</state>
</option> </option>
<option> <option>
<name>IlinkIcfFileSlave</name> <name>IlinkIcfFileSlave</name>

13
FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/ST_Code/Core/Src/main.c
View File

@ -85,12 +85,21 @@ static void MX_USART3_UART_Init(void);
static void MX_USB_OTG_FS_PCD_Init(void); static void MX_USB_OTG_FS_PCD_Init(void);
/* USER CODE BEGIN PFP */ /* USER CODE BEGIN PFP */
static void CPU_CACHE_Enable(void);
/* USER CODE END PFP */ /* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/ /* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */ /* USER CODE BEGIN 0 */
static void CPU_CACHE_Enable(void)
{
/* Enable I-Cache */
SCB_EnableICache();
/* Enable D-Cache */
SCB_EnableDCache();
}
/* USER CODE END 0 */ /* USER CODE END 0 */
/** /**
@ -100,7 +109,7 @@ static void MX_USB_OTG_FS_PCD_Init(void);
int main(void) int main(void)
{ {
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
CPU_CACHE_Enable();
/* USER CODE END 1 */ /* USER CODE END 1 */