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Update MPS430X ports so the sleep mode bits are cleared on exit from the tick interrupt.

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Update heap_4.c.
This commit is contained in:
Richard Barry
2012-08-11 20:57:11 +00:00
parent 59c9044de1
commit 054b018d0e
5 changed files with 29 additions and 32 deletions
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1
Source/portable/CCS/MSP430X/port.c
View File

@ -213,6 +213,7 @@ interrupt void vTickISREntry( void )
{ {
extern void vPortTickISR( void ); extern void vPortTickISR( void );
__bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
#if configUSE_PREEMPTION == 1 #if configUSE_PREEMPTION == 1
extern void vPortPreemptiveTickISR( void ); extern void vPortPreemptiveTickISR( void );
vPortPreemptiveTickISR(); vPortPreemptiveTickISR();

6
Source/portable/CCS/MSP430X/portext.asm
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@ -88,12 +88,6 @@ portRESTORE_CONTEXT .macro
pop_x r15 pop_x r15
mov.w r15, &usCriticalNesting mov.w r15, &usCriticalNesting
popm_x #12, r15 popm_x #12, r15
;The last thing on the stack will be the status register.
;Ensure the power down bits are clear ready for the next
;time this power down register is popped from the stack.
bic.w #0xf0, 0( sp )
pop.w sr pop.w sr
ret_x ret_x
.endm .endm

1
Source/portable/IAR/MSP430X/port.c
View File

@ -214,6 +214,7 @@ __interrupt __raw void vTickISREntry( void )
{ {
extern void vPortTickISR( void ); extern void vPortTickISR( void );
__bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
vPortTickISR(); vPortTickISR();
} }

38
Source/portable/IAR/MSP430X/portext.s43
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@ -95,12 +95,6 @@ portRESTORE_CONTEXT macro
pop_x r15 pop_x r15
mov.w r15, &usCriticalNesting mov.w r15, &usCriticalNesting
popm_x #12, r15 popm_x #12, r15
/* The last thing on the stack will be the status register.
Ensure the power down bits are clear ready for the next
time this power down register is popped from the stack. */
bic.w #0xf0, 0( sp )
pop.w sr pop.w sr
reta reta
endm endm
@ -115,23 +109,25 @@ portRESTORE_CONTEXT macro
* *
* If the preemptive scheduler is in use a context switch can also occur. * If the preemptive scheduler is in use a context switch can also occur.
*/ */
RSEG CODE RSEG CODE
EVEN EVEN
vPortTickISR: vPortTickISR:
/* The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs /* The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs
to save it manually before it gets modified (interrupts get disabled). */ to save it manually before it gets modified (interrupts get disabled).
Entering through this interrupt means the SR is already on the stack, but
this keeps the stack frames identical. */
push.w sr push.w sr
portSAVE_CONTEXT portSAVE_CONTEXT
calla #vTaskIncrementTick calla #vTaskIncrementTick
#if configUSE_PREEMPTION == 1 #if configUSE_PREEMPTION == 1
calla #vTaskSwitchContext calla #vTaskSwitchContext
#endif #endif
portRESTORE_CONTEXT portRESTORE_CONTEXT
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -139,21 +135,21 @@ vPortTickISR:
* Manual context switch called by the portYIELD() macro. * Manual context switch called by the portYIELD() macro.
*/ */
EVEN EVEN
vPortYield: vPortYield:
/* The sr needs saving before it is modified. */ /* The sr needs saving before it is modified. */
push.w sr push.w sr
/* Now the SR is stacked we can disable interrupts. */ /* Now the SR is stacked we can disable interrupts. */
dint dint
nop nop
/* Save the context of the current task. */ /* Save the context of the current task. */
portSAVE_CONTEXT portSAVE_CONTEXT
/* Select the next task to run. */ /* Select the next task to run. */
calla #vTaskSwitchContext calla #vTaskSwitchContext
/* Restore the context of the new task. */ /* Restore the context of the new task. */
portRESTORE_CONTEXT portRESTORE_CONTEXT
@ -165,7 +161,7 @@ vPortYield:
* the context of the first task. * the context of the first task.
*/ */
EVEN EVEN
xPortStartScheduler: xPortStartScheduler:
/* Setup the hardware to generate the tick. Interrupts are disabled /* Setup the hardware to generate the tick. Interrupts are disabled
@ -175,6 +171,6 @@ xPortStartScheduler:
/* Restore the context of the first task that is going to run. */ /* Restore the context of the first task that is going to run. */
portRESTORE_CONTEXT portRESTORE_CONTEXT
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
END END

15
Source/portable/MemMang/heap_4.c
View File

@ -356,7 +356,7 @@ unsigned char *puc;
} }
#define INCLUDE_TEST_CODE 1 #define INCLUDE_TEST_CODE 0
#if INCLUDE_TEST_CODE == 1 #if INCLUDE_TEST_CODE == 1
#define heapMAX_TEST_BLOCKS 6 #define heapMAX_TEST_BLOCKS 6
@ -366,6 +366,7 @@ void vTestHeap4( void )
void *pvReturned; void *pvReturned;
static void *pvUsedBlocks[ heapMAX_TEST_BLOCKS ]; static void *pvUsedBlocks[ heapMAX_TEST_BLOCKS ];
unsigned long ulIndex = 0, ulSize, ulRandSample; unsigned long ulIndex = 0, ulSize, ulRandSample;
size_t xSize1, xSize2, xSize3;
static const unsigned long ulCombinations[ 6 ][ 3 ] = static const unsigned long ulCombinations[ 6 ][ 3 ] =
{ {
{ 0, 1, 2 }, { 0, 1, 2 },
@ -530,13 +531,17 @@ static const unsigned long ulCombinations[ 6 ][ 3 ] =
} }
/* Do the same, but using random block sizes. */ /* Do the same, but using random block sizes. */
for( ulRandSample = 0; ulRandSample < 0x5ffff; ulRandSample++ ) for( ulRandSample = 0; ulRandSample < 0xffffffUL; ulRandSample++ )
{ {
xSize1 = rand();
xSize2 = rand();
xSize3 = rand();
for( ulIndex = 0; ulIndex < 6; ulIndex++ ) for( ulIndex = 0; ulIndex < 6; ulIndex++ )
{ {
pvUsedBlocks[ 0 ] = pvPortMalloc( rand() ); pvUsedBlocks[ 0 ] = pvPortMalloc( xSize1 );
pvUsedBlocks[ 1 ] = pvPortMalloc( rand() ); pvUsedBlocks[ 1 ] = pvPortMalloc( xSize2 );
pvUsedBlocks[ 2 ] = pvPortMalloc( rand() ); pvUsedBlocks[ 2 ] = pvPortMalloc( xSize3 );
vPortFree( pvUsedBlocks[ ulCombinations[ ulIndex ][ 0 ] ] ); vPortFree( pvUsedBlocks[ ulCombinations[ ulIndex ][ 0 ] ] );
vPortFree( pvUsedBlocks[ ulCombinations[ ulIndex ][ 1 ] ] ); vPortFree( pvUsedBlocks[ ulCombinations[ ulIndex ][ 1 ] ] );