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https://github.com/espressif/ESP8266_RTOS_SDK.git
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68e990c99f
Make it easy for other OS platform to use these code. If users want to add other OSes, they only should add 3 files: 1. "port.c": init task stack and switch task function 2. "osi.c": wrapper APIs to FreeRTOS from other OSes 3. "heap.c": wrapper APIs for other OSes' heap APIs
145 lines
5.6 KiB
ArmAsm
145 lines
5.6 KiB
ArmAsm
/*******************************************************************************
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Copyright (c) 2006-2009 by Tensilica Inc. ALL RIGHTS RESERVED.
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These coded instructions, statements, and computer programs are the
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copyrighted works and confidential proprietary information of Tensilica Inc.
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They may not be modified, copied, reproduced, distributed, or disclosed to
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third parties in any manner, medium, or form, in whole or in part, without
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the prior written consent of Tensilica Inc.
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--------------------------------------------------------------------------------
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XTENSA CONTEXT SAVE AND RESTORE ROUTINES
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Low-level Call0 functions for handling generic context save and restore of
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registers not specifically addressed by the interrupt vectors and handlers.
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Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
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Except for the calls to RTOS functions, this code is generic to Xtensa.
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Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
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save regs (A12-A15), which is always the case if the handlers are coded in C.
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However A12, A13 are made available as scratch registers for interrupt dispatch
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code, so are presumed saved anyway, and are always restored even in Call0 ABI.
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Only A14, A15 are truly handled as callee-save regs.
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Because Xtensa is a configurable architecture, this port supports all user
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generated configurations (except restrictions stated in the release notes).
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This is accomplished by conditional compilation using macros and functions
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defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
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Only the processor state included in your configuration is saved and restored,
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including any processor state added by user configuration options or TIE.
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*******************************************************************************/
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/* Warn nicely if this file gets named with a lowercase .s instead of .S: */
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#define NOERROR #
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NOERROR: .error "C preprocessor needed for this file: make sure its filename\
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ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
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#include "freertos/xtensa_rtos.h"
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.section .text
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/*******************************************************************************
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_xt_context_save
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!! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
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Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
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interrupt stack frame defined in xtensa_rtos.h.
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Its counterpart is _xt_context_restore (which also restores A12, A13).
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Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
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This function preserves A12 & A13 in order to provide the caller with 2 scratch
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regs that need not be saved over the call to this function. The choice of which
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2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
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to avoid moving data more than necessary. Caller can assign regs accordingly.
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Entry Conditions:
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A0 = Return address in caller.
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A1 = Stack pointer of interrupted thread or handler ("interruptee").
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Original A12, A13 have already been saved in the interrupt stack frame.
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Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the
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point of interruption.
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If windowed ABI, PS.EXCM = 1 (exceptions disabled).
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Exit conditions:
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A0 = Return address in caller.
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A1 = Stack pointer of interrupted thread or handler ("interruptee").
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A12, A13 as at entry (preserved).
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If windowed ABI, PS.EXCM = 1 (exceptions disabled).
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*******************************************************************************/
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.global _xt_context_save
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.type _xt_context_save,@function
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.align 4
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_xt_context_save:
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s32i a2, sp, XT_STK_A2
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s32i a3, sp, XT_STK_A3
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s32i a4, sp, XT_STK_A4
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s32i a5, sp, XT_STK_A5
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s32i a6, sp, XT_STK_A6
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s32i a7, sp, XT_STK_A7
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s32i a8, sp, XT_STK_A8
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s32i a9, sp, XT_STK_A9
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s32i a10, sp, XT_STK_A10
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s32i a11, sp, XT_STK_A11
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rsr a3, SAR
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s32i a3, sp, XT_STK_SAR
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ret
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/*******************************************************************************
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_xt_context_restore
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!! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
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Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
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ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt
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stack frame defined in xtensa_rtos.h .
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Its counterpart is _xt_context_save (whose caller saved A12, A13).
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Caller is responsible to restore PC, PS, A0, A1 (SP).
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Entry Conditions:
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A0 = Return address in caller.
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A1 = Stack pointer of interrupted thread or handler ("interruptee").
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Exit conditions:
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A0 = Return address in caller.
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A1 = Stack pointer of interrupted thread or handler ("interruptee").
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Other processor state except PC, PS, A0, A1 (SP), is as at the point
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of interruption.
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*******************************************************************************/
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.global _xt_context_restore
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.type _xt_context_restore,@function
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.align 4
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_xt_context_restore:
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l32i a3, sp, XT_STK_SAR
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l32i a2, sp, XT_STK_A2
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wsr a3, SAR
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l32i a3, sp, XT_STK_A3
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l32i a4, sp, XT_STK_A4
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l32i a5, sp, XT_STK_A5
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l32i a6, sp, XT_STK_A6
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l32i a7, sp, XT_STK_A7
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l32i a8, sp, XT_STK_A8
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l32i a9, sp, XT_STK_A9
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l32i a10, sp, XT_STK_A10
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l32i a11, sp, XT_STK_A11
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/*
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Call0 ABI callee-saved regs a12-15 do not need to be restored here.
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However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(),
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so need to be restored anyway, despite being callee-saved in Call0.
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*/
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l32i a12, sp, XT_STK_A12
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l32i a13, sp, XT_STK_A13
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ret
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