mirror of
https://github.com/espressif/ESP8266_RTOS_SDK.git
synced 2025-05-22 01:27:11 +08:00
448 lines
12 KiB
C
448 lines
12 KiB
C
// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include "esp_err.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SPI_NUM_MAX 2
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/* SPI bus CPOL and CPHA definition */
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#define SPI_CPOL_LOW 0
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#define SPI_CPOL_HIGH 1
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#define SPI_CPHA_LOW 0
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#define SPI_CPHA_HIGH 1
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/* SPI bus data sequence definition */
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#define SPI_BIT_ORDER_MSB_FIRST 1
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#define SPI_BIT_ORDER_LSB_FIRST 0
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#define SPI_BYTE_ORDER_MSB_FIRST 1
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#define SPI_BYTE_ORDER_LSB_FIRST 0
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/* SPI default bus interface parameter definition */
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#define SPI_DEFAULT_INTERFACE 0x1F0 /* CS_EN:1, MISO_EN:1, MOSI_EN:1, BYTE_TX_ORDER:1, BYTE_TX_ORDER:1, BIT_RX_ORDER:0, BIT_TX_ORDER:0, CPHA:0, CPOL:0 */
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/* SPI master default interrupt enable definition */
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#define SPI_MASTER_DEFAULT_INTR_ENABLE 0x10 /* TRANS_DONE: true, WRITE_STATUS: false, READ_STATUS: false, WRITE_BUFFER: false, READ_BUFFER: false */
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/* SPI slave default interrupt enable definition */
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#define SPI_SLAVE_DEFAULT_INTR_ENABLE 0x0F /* TRANS_DONE: false, WRITE_STATUS: true, READ_STATUS: true, WRITE_BUFFER: true, READ_BUFFER: ture */
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/* SPI event definition */
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#define SPI_INIT_EVENT 0
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#define SPI_TRANS_START_EVENT 1
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#define SPI_TRANS_DONE_EVENT 2
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#define SPI_DEINIT_EVENT 3
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/* SPI data cmd definition */
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#define SPI_MASTER_WRITE_DATA_TO_SLAVE_CMD 2
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#define SPI_MASTER_READ_DATA_FROM_SLAVE_CMD 3
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/* SPI status cmd definition */
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#define SPI_MASTER_WRITE_STATUS_TO_SLAVE_CMD 1
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#define SPI_MASTER_READ_STATUS_FROM_SLAVE_CMD 4
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/* SPI slave transfer done interrupt status definition */
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#define SPI_SLV_RD_BUF_DONE (BIT(0))
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#define SPI_SLV_WR_BUF_DONE (BIT(1))
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#define SPI_SLV_RD_STA_DONE (BIT(2))
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#define SPI_SLV_WR_STA_DONE (BIT(3))
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#define SPI_TRANS_DONE (BIT(4))
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typedef void (*spi_event_callback_t)(int event, void *arg);
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/**
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* @brief SPI peripheral enumeration
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*
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* @note ESP8266 has two hardware SPI, CSPI and HSPI. Currently, HSPI can be used arbitrarily.
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*/
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typedef enum {
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CSPI_HOST = 0,
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HSPI_HOST
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} spi_host_t;
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/**
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* @brief SPI clock division factor enumeration
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*/
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typedef enum {
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SPI_2MHz_DIV = 40,
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SPI_4MHz_DIV = 20,
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SPI_5MHz_DIV = 16,
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SPI_8MHz_DIV = 10,
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SPI_10MHz_DIV = 8,
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SPI_16MHz_DIV = 5,
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SPI_20MHz_DIV = 4,
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SPI_40MHz_DIV = 2,
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SPI_80MHz_DIV = 1,
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} spi_clk_div_t;
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/**
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* @brief SPI working mode enumeration
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*/
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typedef enum {
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SPI_MASTER_MODE,
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SPI_SLAVE_MODE
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} spi_mode_t;
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/**
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* @brief SPI interrupt enable union type definition
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*/
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typedef union {
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struct {
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uint32_t read_buffer: 1;
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uint32_t write_buffer: 1;
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uint32_t read_status: 1;
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uint32_t write_status: 1;
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uint32_t trans_done: 1;
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uint32_t reserved5: 27;
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};
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uint32_t val;
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} spi_intr_enable_t;
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/**
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* @brief SPI bus interface parameter union type definition
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*/
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typedef union {
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struct {
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uint32_t cpol: 1; /*!< Clock Polarity */
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uint32_t cpha: 1; /*!< Clock Phase */
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uint32_t bit_tx_order: 1; /*!< Tx bit order */
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uint32_t bit_rx_order: 1; /*!< Rx bit order */
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uint32_t byte_tx_order: 1; /*!< Tx byte order */
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uint32_t byte_rx_order: 1; /*!< Rx byte order */
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uint32_t mosi_en: 1; /*!< MOSI line enable */
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uint32_t miso_en: 1; /*!< MISO line enable */
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uint32_t cs_en: 1; /*!< CS line enable */
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uint32_t reserved9: 23; /*!< resserved */
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};
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uint32_t val;
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} spi_interface_t;
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/**
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* @brief SPI transmission parameter structure type definition
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*/
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typedef struct {
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uint16_t *cmd;
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uint32_t *addr;
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uint32_t *mosi;
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uint32_t *miso;
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union {
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struct {
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uint32_t cmd: 5;
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uint32_t addr: 7;
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uint32_t mosi: 10;
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uint32_t miso: 10;
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};
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uint32_t val;
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} bits;
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} spi_trans_t;
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/**
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* @brief SPI initialization parameter structure type definition
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*/
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typedef struct {
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spi_interface_t interface;
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spi_intr_enable_t intr_enable;
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spi_event_callback_t event_cb;
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spi_mode_t mode;
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spi_clk_div_t clk_div;
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} spi_config_t;
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/**
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* @brief Get the SPI clock division factor
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param clk_div Pointer to accept clock division factor
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_get_clk_div(spi_host_t host, spi_clk_div_t *clk_div);
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/**
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* @brief Get SPI Interrupt Enable
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param intr_enable Pointer to accept interrupt enable
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_get_intr_enable(spi_host_t host, spi_intr_enable_t *intr_enable);
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/**
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* @brief Get SPI working mode
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param mode Pointer to accept working mode
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_get_mode(spi_host_t host, spi_mode_t *mode);
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/**
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* @brief Get SPI bus interface configuration
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param interface Pointer to accept bus interface configuration
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_get_interface(spi_host_t host, spi_interface_t *interface);
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/**
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* @brief Get the SPI event callback function
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param event_cb Pointer to accept event callback function
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_get_event_callback(spi_host_t host, spi_event_callback_t *event_cb);
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/**
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* @brief Set the SPI clock division factor
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param clk_div Pointer to deliver clock division factor
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_set_clk_div(spi_host_t host, spi_clk_div_t *clk_div);
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/**
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* @brief Set SPI interrupt enable
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param intr_enable Pointer to deliver interrupt enable
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_set_intr_enable(spi_host_t host, spi_intr_enable_t *intr_enable);
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/**
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* @brief Set the SPI mode of operation
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param mode Pointer to deliver working mode
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_set_mode(spi_host_t host, spi_mode_t *mode);
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/**
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* @brief Get SPI dummy bitlen
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param bitlen Pointer to accept dummy bitlen
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_get_dummy(spi_host_t host, uint16_t *bitlen);
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/**
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* @brief Set SPI dummy bitlen
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param bitlen Pointer to deliver dummy bitlen
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_set_dummy(spi_host_t host, uint16_t *bitlen);
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/**
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* @brief Set SPI bus interface configuration
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param interface Pointer to deliver bus interface configuration
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_set_interface(spi_host_t host, spi_interface_t *interface);
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/**
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* @brief Set the SPI event callback function
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*
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* @note This event_cb will be called from an ISR. So there is a stack
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* size limit (configurable as "ISR stack size" in menuconfig). This
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* limit is smaller compared to a global SPI interrupt handler due
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* to the additional level of indirection.
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param event_cb Pointer to deliver event callback function
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_set_event_callback(spi_host_t host, spi_event_callback_t *event_cb);
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/**
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* @brief Get SPI slave wr_status register
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param status Pointer to accept wr_status register
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_slave_get_status(spi_host_t host, uint32_t *status);
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/**
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* @brief Set SPI slave rd_status register
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param status Pointer to deliver rd_status register
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_slave_set_status(spi_host_t host, uint32_t *status);
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/**
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* @brief SPI data transfer function
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*
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* @note If the bit of the corresponding phase in the transmission parameter is 0, its data will not work.
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* For example: trans.bits.cmd = 0, cmd will not be transmitted
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param trans Transmission parameter structure
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_trans(spi_host_t host, spi_trans_t trans);
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/**
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* @brief Deinit the spi
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @return
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* - ESP_OK Success
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_deinit(spi_host_t host);
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/**
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* @brief Initialize the spi
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*
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* @note SPI0 has been used by FLASH and cannot be used by the user temporarily.
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param config Pointer to deliver initialize configuration parameter
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_NO_MEM malloc fail
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* - ESP_FAIL spi has been initialized
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*/
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esp_err_t spi_init(spi_host_t host, spi_config_t *config);
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#ifdef __cplusplus
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}
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#endif |