mirror of
https://github.com/espressif/ESP8266_RTOS_SDK.git
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295 lines
7.6 KiB
C
295 lines
7.6 KiB
C
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include <sys/param.h>
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#include "esp_timer.h"
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#include "esp_log.h"
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#include "esp_system.h"
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#include "esp_sleep.h"
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#include "FreeRTOS.h"
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#include "freertos/task.h"
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#include "driver/soc.h"
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#include "esp8266/timer_struct.h"
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#include "esp8266/rom_functions.h"
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#include "driver/rtc.h"
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#include "rom/uart.h"
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#include "internal/phy_init_data.h"
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#define FRC2_LOAD (0x60000620)
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#define FRC2_COUNT (0x60000624)
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#define FRC2_CTL (0x60000628)
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#define FRC2_ALARM (0x60000630)
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#define FRC2_CNTL_ENABLE BIT7
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#define FRC2_TICKS_PER_US (5)
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#define FRC2_TICKS_MAX (UINT32_MAX / 4)
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#define SLEEP_MIN_TIME (1000)
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#define SLEEP_PROC_TIME (4450)
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#define WAKEUP_EARLY_TICKS (264) // PLL and STAL wait ticks
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#define MIN_SLEEP_US (SLEEP_MIN_TIME + SLEEP_PROC_TIME)
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#define TAG "esp8266_pm"
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typedef struct pm_soc_clk {
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uint32_t ccount;
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uint32_t frc2_enable;
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uint32_t frc2_cnt;
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uint32_t wdev_cnt;
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} pm_soc_clk_t;
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static uint16_t s_lock_cnt = 1;
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static esp_sleep_mode_t s_sleep_mode = ESP_CPU_WAIT;
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static uint32_t s_sleep_wakup_triggers;
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static uint32_t s_sleep_duration;
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static inline uint32_t save_local_wdev(void)
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{
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extern uint32_t WDEV_INTEREST_EVENT;
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uint32_t reg = WDEV_INTEREST_EVENT;
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REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT);
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return reg;
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}
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static inline void restore_local_wdev(uint32_t reg)
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{
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REG_WRITE(INT_ENA_WDEV, reg);
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}
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static inline void save_soc_clk(pm_soc_clk_t *clk)
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{
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clk->ccount = soc_get_ccount();
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clk->frc2_enable = REG_READ(FRC2_CTL) & FRC2_CNTL_ENABLE;
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if (clk->frc2_enable)
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clk->frc2_cnt = REG_READ(FRC2_COUNT);
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clk->wdev_cnt = REG_READ(WDEV_COUNT_REG);
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}
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static inline uint32_t min_sleep_us(pm_soc_clk_t *clk)
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{
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const uint32_t os_idle_ticks = prvGetExpectedIdleTime();
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const int32_t os_sleep_us = ((int32_t)soc_get_ccompare() - (int32_t)clk->ccount) / g_esp_ticks_per_us +
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(os_idle_ticks ? os_idle_ticks - 1 : 0) * portTICK_RATE_MS * 1000;
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const uint32_t ccompare_sleep_us = os_sleep_us > 0 ? os_sleep_us : 0;
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if (clk->frc2_enable) {
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const uint32_t frc2_sleep_ticks = REG_READ(FRC2_ALARM) - clk->frc2_cnt;
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const uint32_t frc2_sleep_us = frc2_sleep_ticks < FRC2_TICKS_MAX ? frc2_sleep_ticks / FRC2_TICKS_PER_US : 0;
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return MIN(ccompare_sleep_us, frc2_sleep_us);
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} else {
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return ccompare_sleep_us;
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}
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}
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static inline void update_soc_clk(pm_soc_clk_t *clk, uint32_t us)
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{
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extern uint32_t WdevTimOffSet;
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const uint32_t os_ccount = us * g_esp_ticks_per_us + clk->ccount;
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if (os_ccount >= _xt_tick_divisor)
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soc_set_ccompare(os_ccount + 32);
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soc_set_ccount(os_ccount);
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if (clk->frc2_enable) {
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const uint32_t frc2_cnt = us * FRC2_TICKS_PER_US + clk->frc2_cnt - 1;
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REG_WRITE(FRC2_LOAD, frc2_cnt);
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}
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uint32_t wdev_us;
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uint32_t wdev_cnt = REG_READ(WDEV_COUNT_REG);
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if (clk->wdev_cnt < wdev_cnt)
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wdev_us = us - (wdev_cnt - clk->wdev_cnt);
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else
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wdev_us = us - (UINT32_MAX - clk->wdev_cnt + wdev_cnt);
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WdevTimOffSet += wdev_us;
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}
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static int cpu_is_wait_mode(void)
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{
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return (s_sleep_mode == ESP_CPU_WAIT) || s_lock_cnt;
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}
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void esp_wifi_hw_open(void)
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{
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phy_open_rf();
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}
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void esp_wifi_hw_close(void)
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{
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phy_close_rf();
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}
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rtc_cpu_freq_t rtc_clk_cpu_freq_get(void)
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{
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rtc_cpu_freq_t freq;
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uint32_t reg = REG_READ(DPORT_CTL_REG);
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if (reg & DPORT_CTL_DOUBLE_CLK)
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freq = RTC_CPU_FREQ_160M;
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else
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freq = RTC_CPU_FREQ_80M;
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return freq;
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}
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void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
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{
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if (RTC_CPU_FREQ_80M == cpu_freq)
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REG_CLR_BIT(DPORT_CTL_REG, DPORT_CTL_DOUBLE_CLK);
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else
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REG_SET_BIT(DPORT_CTL_REG, DPORT_CTL_DOUBLE_CLK);
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}
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esp_err_t esp_sleep_enable_timer_wakeup(uint32_t time_in_us)
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{
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if (time_in_us <= MIN_SLEEP_US)
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return ESP_ERR_INVALID_ARG;
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s_sleep_duration = time_in_us - SLEEP_PROC_TIME;
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s_sleep_wakup_triggers |= RTC_TIMER_TRIG_EN;
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return ESP_OK;
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}
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esp_err_t esp_sleep_enable_gpio_wakeup(void)
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{
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s_sleep_wakup_triggers |= RTC_GPIO_TRIG_EN;
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return ESP_OK;
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}
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esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
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{
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// For most of sources it is enough to set trigger mask in local
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// configuration structure. The actual RTC wake up options
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// will be updated by esp_sleep_start().
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if (source == ESP_SLEEP_WAKEUP_ALL) {
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s_sleep_wakup_triggers = 0;
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} else if (ESP_SLEEP_WAKEUP_TIMER == source) {
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s_sleep_wakup_triggers &= ~RTC_TIMER_TRIG_EN;
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s_sleep_duration = 0;
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} else if (ESP_SLEEP_WAKEUP_GPIO == source) {
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s_sleep_wakup_triggers &= ~RTC_GPIO_TRIG_EN;
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} else {
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ESP_LOGE(TAG, "Incorrect wakeup source (%d) to disable.", (int) source);
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return ESP_ERR_INVALID_STATE;
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}
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return ESP_OK;
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}
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esp_err_t esp_light_sleep_start(void)
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{
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uint32_t period = pm_rtc_clock_cali_proc();
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const uint32_t sleep_rtc_ticks = pm_usec2rtc(s_sleep_duration, period);
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const rtc_cpu_freq_t cpu_freq = rtc_clk_cpu_freq_get();
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if (sleep_rtc_ticks > WAKEUP_EARLY_TICKS + 1) {
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rtc_lightsleep_init();
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pm_set_sleep_cycles(sleep_rtc_ticks - WAKEUP_EARLY_TICKS);
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rtc_light_sleep_start(s_sleep_wakup_triggers, 0);
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rtc_wakeup_init();
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rtc_clk_cpu_freq_set(cpu_freq);
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return ESP_OK;
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}
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return ESP_ERR_INVALID_STATE;
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}
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void esp_sleep_lock(void)
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{
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const esp_irqflag_t irqflag = soc_save_local_irq();
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s_lock_cnt++;
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soc_restore_local_irq(irqflag);
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}
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void esp_sleep_unlock(void)
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{
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const esp_irqflag_t irqflag = soc_save_local_irq();
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s_lock_cnt--;
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soc_restore_local_irq(irqflag);
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}
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void esp_sleep_set_mode(esp_sleep_mode_t mode)
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{
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s_sleep_mode = mode;
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}
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void esp_sleep_start(void)
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{
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if (cpu_is_wait_mode()) {
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soc_wait_int();
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return ;
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}
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uart_tx_wait_idle(0);
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uart_tx_wait_idle(1);
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int cpu_wait = 1;
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pm_soc_clk_t clk;
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const esp_irqflag_t irqflag = soc_save_local_irq();
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const uint32_t wdevflag = save_local_wdev();
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if (cpu_is_wait_mode()) {
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cpu_wait = 0;
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goto exit;
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}
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save_soc_clk(&clk);
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const uint32_t sleep_us = min_sleep_us(&clk);
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if (sleep_us > MIN_SLEEP_US) {
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uint32_t period = pm_rtc_clock_cali_proc();
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const uint32_t sleep_rtc_ticks = pm_usec2rtc(sleep_us - SLEEP_PROC_TIME, period);
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if (sleep_rtc_ticks > WAKEUP_EARLY_TICKS + 1) {
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const rtc_cpu_freq_t cpu_freq = rtc_clk_cpu_freq_get();
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rtc_lightsleep_init();
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pm_set_sleep_cycles(sleep_rtc_ticks - WAKEUP_EARLY_TICKS);
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rtc_light_sleep_start(s_sleep_wakup_triggers | RTC_TIMER_TRIG_EN, 0);
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rtc_wakeup_init();
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rtc_clk_cpu_freq_set(cpu_freq);
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update_soc_clk(&clk, sleep_us);
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cpu_wait = 0;
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}
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}
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exit:
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restore_local_wdev(wdevflag);
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soc_restore_local_irq(irqflag);
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if (cpu_wait)
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soc_wait_int();
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}
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