mirror of
https://github.com/espressif/ESP8266_RTOS_SDK.git
synced 2025-05-23 18:18:36 +08:00
146 lines
4.2 KiB
C
146 lines
4.2 KiB
C
// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include "esp8266/eagle_soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ESP8266 I2S Register Definitions */
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typedef volatile struct {
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uint32_t tx_fifo;
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uint32_t rx_fifo;
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union {
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struct {
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uint32_t tx_reset: 1;
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uint32_t rx_reset: 1;
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uint32_t tx_fifo_reset: 1;
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uint32_t rx_fifo_reset: 1;
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uint32_t tx_slave_mod: 1;
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uint32_t rx_slave_mod: 1;
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uint32_t right_first: 1;
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uint32_t msb_right: 1;
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uint32_t tx_start: 1;
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uint32_t rx_start: 1;
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uint32_t tx_msb_shift: 1;
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uint32_t rx_msb_shift: 1;
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uint32_t bits_mod: 4;
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uint32_t clkm_div_num: 6;
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uint32_t bck_div_num: 6;
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} conf;
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union {
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struct {
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uint32_t rx_take_data: 1;
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uint32_t tx_put_data: 1;
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uint32_t rx_wfull: 1;
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uint32_t rx_rempty: 1;
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uint32_t tx_wfull: 1;
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uint32_t tx_rempty: 1;
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uint32_t reserved6: 26;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t rx_take_data: 1;
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uint32_t tx_put_data: 1;
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uint32_t rx_wfull: 1;
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uint32_t rx_rempty: 1;
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uint32_t tx_wfull: 1;
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uint32_t tx_rempty: 1;
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uint32_t reserved6: 26;
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};
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uint32_t val;
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} int_st;
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union {
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struct {
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uint32_t rx_take_data: 1;
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uint32_t tx_put_data: 1;
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uint32_t rx_wfull: 1;
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uint32_t rx_rempty: 1;
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uint32_t tx_wfull: 1;
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uint32_t tx_rempty: 1;
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uint32_t reserved6: 26;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t rx_take_data: 1;
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uint32_t tx_put_data: 1;
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uint32_t rx_wfull: 1;
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uint32_t rx_rempty: 1;
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uint32_t tx_wfull: 1;
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uint32_t tx_rempty: 1;
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uint32_t reserved6: 26;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t tx_bck_in_delay: 2;
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uint32_t tx_ws_in_delay: 2;
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uint32_t rx_bck_in_delay: 2;
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uint32_t rx_ws_in_delay: 2;
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uint32_t rx_sd_in_delay: 2;
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uint32_t tx_bck_out_delay: 2;
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uint32_t tx_ws_out_delay: 2;
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uint32_t tx_sd_out_delay: 2;
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uint32_t rx_ws_out_delay: 2;
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uint32_t rx_bck_out_delay: 2;
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uint32_t tx_dsync_sw: 1;
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uint32_t rx_dsync_sw: 1;
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uint32_t tx_bck_in_inv: 1;
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uint32_t reserved23: 9;
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};
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uint32_t val;
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} timing;
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union {
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struct {
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uint32_t rx_data_num: 6;
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uint32_t tx_data_num: 6;
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uint32_t dscr_en: 1;
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uint32_t tx_fifo_mod: 3;
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uint32_t rx_fifo_mod: 3;
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uint32_t reserved19: 13;
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};
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uint32_t val;
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} fifo_conf;
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uint32_t rx_eof_num;
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uint32_t conf_single_data;
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union {
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struct {
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uint32_t tx_chan_mod: 3;
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uint32_t rx_chan_mod: 2;
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uint32_t reserved5: 27;
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};
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uint32_t val;
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} conf_chan;
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} i2s_struct_t;
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extern volatile i2s_struct_t I2S0;
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#ifdef __cplusplus
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}
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#endif /* end of __cplusplus */
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