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https://github.com/espressif/ESP8266_RTOS_SDK.git
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fix spelling mistake, reported by ly0
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Espressif Systems
44
examples/driver_lib/driver/Makefile
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44
examples/driver_lib/driver/Makefile
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#############################################################
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# Required variables for each makefile
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# Discard this section from all parent makefiles
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# Expected variables (with automatic defaults):
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# CSRCS (all "C" files in the dir)
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# SUBDIRS (all subdirs with a Makefile)
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# GEN_LIBS - list of libs to be generated ()
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# GEN_IMAGES - list of images to be generated ()
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# COMPONENTS_xxx - a list of libs/objs in the form
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# subdir/lib to be extracted and rolled up into
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# a generated lib/image xxx.a ()
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#
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ifndef PDIR
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GEN_LIBS = libdriver.a
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endif
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#############################################################
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# Configuration i.e. compile options etc.
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# Target specific stuff (defines etc.) goes in here!
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# Generally values applying to a tree are captured in the
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# makefile at its root level - these are then overridden
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# for a subtree within the makefile rooted therein
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#
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#DEFINES +=
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#############################################################
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# Recursion Magic - Don't touch this!!
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#
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# Each subtree potentially has an include directory
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# corresponding to the common APIs applicable to modules
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# rooted at that subtree. Accordingly, the INCLUDE PATH
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# of a module can only contain the include directories up
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# its parent path, and not its siblings
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#
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# Required for each makefile to inherit from the parent
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#
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INCLUDES := $(INCLUDES) -I $(PDIR)include
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INCLUDES += -I ./
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PDIR := ../$(PDIR)
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sinclude $(PDIR)Makefile
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207
examples/driver_lib/driver/gpio.c
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207
examples/driver_lib/driver/gpio.c
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@ -0,0 +1,207 @@
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/*
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* Copyright (C) 2014 -2016 Espressif System
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*
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*/
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#include "espressif/esp_common.h"
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#include "freertos/portmacro.h"
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#include "gpio.h"
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void ICACHE_FLASH_ATTR
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gpio_config(GPIO_ConfigTypeDef *pGPIOConfig)
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{
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uint16 gpio_pin_mask = pGPIOConfig->GPIO_Pin;
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uint32 io_reg;
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uint8 io_num = 0;
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uint32 pin_reg;
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if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Input) {
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GPIO_AS_INPUT(gpio_pin_mask);
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} else if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Output) {
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GPIO_AS_OUTPUT(gpio_pin_mask);
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}
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do {
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if ((gpio_pin_mask >> io_num) & 0x1) {
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io_reg = GPIO_PIN_REG(io_num);
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if ((0x1 << io_num) & (GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_4 | GPIO_Pin_5)) {
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PIN_FUNC_SELECT(io_reg, 0);
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} else {
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PIN_FUNC_SELECT(io_reg, 3);
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}
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if (pGPIOConfig->GPIO_Pullup) {
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PIN_PULLUP_EN(io_reg);
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} else {
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PIN_PULLUP_DIS(io_reg);
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}
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if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Out_OD) {
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portENTER_CRITICAL();
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(io_num));
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pin_reg &= (~GPIO_PIN_DRIVER_MASK);
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pin_reg |= (GPIO_PAD_DRIVER_ENABLE << GPIO_PIN_DRIVER_LSB);
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GPIO_REG_WRITE(GPIO_PIN_ADDR(io_num), pin_reg);
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portEXIT_CRITICAL();
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} else if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Sigma_Delta) {
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portENTER_CRITICAL();
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(io_num));
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pin_reg &= (~GPIO_PIN_SOURCE_MASK);
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pin_reg |= (0x1 << GPIO_PIN_SOURCE_LSB);
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GPIO_REG_WRITE(GPIO_PIN_ADDR(io_num), pin_reg);
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GPIO_REG_WRITE(GPIO_SIGMA_DELTA_ADDRESS, SIGMA_DELTA_ENABLE);
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portEXIT_CRITICAL();
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}
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gpio_pin_intr_state_set(io_num, pGPIOConfig->GPIO_IntrType);
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}
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io_num++;
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} while (io_num < 16);
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}
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/*
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* Change GPIO pin output by setting, clearing, or disabling pins.
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* In general, it is expected that a bit will be set in at most one
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* of these masks. If a bit is clear in all masks, the output state
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* remains unchanged.
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*
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* There is no particular ordering guaranteed; so if the order of
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* writes is significant, calling code should divide a single call
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* into multiple calls.
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*/
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void ICACHE_FLASH_ATTR
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gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, uint32 disable_mask)
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{
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GPIO_REG_WRITE(GPIO_OUT_W1TS_ADDRESS, set_mask);
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GPIO_REG_WRITE(GPIO_OUT_W1TC_ADDRESS, clear_mask);
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GPIO_REG_WRITE(GPIO_ENABLE_W1TS_ADDRESS, enable_mask);
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GPIO_REG_WRITE(GPIO_ENABLE_W1TC_ADDRESS, disable_mask);
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}
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/*
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* Sample the value of GPIO input pins and returns a bitmask.
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*/
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uint32 ICACHE_FLASH_ATTR
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gpio_input_get(void)
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{
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return GPIO_REG_READ(GPIO_IN_ADDRESS);
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}
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/*
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* Register an application-specific interrupt handler for GPIO pin
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* interrupts. Once the interrupt handler is called, it will not
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* be called again until after a call to gpio_intr_ack. Any GPIO
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* interrupts that occur during the interim are masked.
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*
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* The application-specific handler is called with a mask of
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* pending GPIO interrupts. After processing pin interrupts, the
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* application-specific handler may wish to use gpio_intr_pending
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* to check for any additional pending interrupts before it returns.
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*/
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void ICACHE_FLASH_ATTR
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gpio_intr_handler_register(void *fn)
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{
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_xt_isr_attach(ETS_GPIO_INUM, fn);
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}
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/*
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only highlevel and lowlevel intr can use for wakeup
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*/
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void ICACHE_FLASH_ATTR
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gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state)
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{
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uint32 pin_reg;
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if ((intr_state == GPIO_PIN_INTR_LOLEVEL) || (intr_state == GPIO_PIN_INTR_HILEVEL)) {
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portENTER_CRITICAL();
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(i));
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pin_reg &= (~GPIO_PIN_INT_TYPE_MASK);
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pin_reg |= (intr_state << GPIO_PIN_INT_TYPE_LSB);
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pin_reg |= GPIO_PIN_WAKEUP_ENABLE_SET(GPIO_WAKEUP_ENABLE);
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GPIO_REG_WRITE(GPIO_PIN_ADDR(i), pin_reg);
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portEXIT_CRITICAL();
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}
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}
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void ICACHE_FLASH_ATTR
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gpio_pin_wakeup_disable(void)
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{
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uint8 i;
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uint32 pin_reg;
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for (i = 0; i < GPIO_PIN_COUNT; i++) {
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(i));
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if (pin_reg & GPIO_PIN_WAKEUP_ENABLE_MASK) {
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pin_reg &= (~GPIO_PIN_INT_TYPE_MASK);
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pin_reg |= (GPIO_PIN_INTR_DISABLE << GPIO_PIN_INT_TYPE_LSB);
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pin_reg &= ~(GPIO_PIN_WAKEUP_ENABLE_SET(GPIO_WAKEUP_ENABLE));
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GPIO_REG_WRITE(GPIO_PIN_ADDR(i), pin_reg);
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}
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}
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}
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void ICACHE_FLASH_ATTR
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gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state)
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{
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uint32 pin_reg;
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portENTER_CRITICAL();
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(i));
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pin_reg &= (~GPIO_PIN_INT_TYPE_MASK);
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pin_reg |= (intr_state << GPIO_PIN_INT_TYPE_LSB);
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GPIO_REG_WRITE(GPIO_PIN_ADDR(i), pin_reg);
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portEXIT_CRITICAL();
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}
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void ICACHE_FLASH_ATTR
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gpio16_output_conf(void)
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{
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WRITE_PERI_REG(PAD_XPD_DCDC_CONF,
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(READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32)0x1); // mux configuration for XPD_DCDC to output rtc_gpio0
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WRITE_PERI_REG(RTC_GPIO_CONF,
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(READ_PERI_REG(RTC_GPIO_CONF) & (uint32)0xfffffffe) | (uint32)0x0); //mux configuration for out enable
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WRITE_PERI_REG(RTC_GPIO_ENABLE,
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(READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe) | (uint32)0x1); //out enable
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}
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void ICACHE_FLASH_ATTR
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gpio16_output_set(uint8 value)
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{
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WRITE_PERI_REG(RTC_GPIO_OUT,
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(READ_PERI_REG(RTC_GPIO_OUT) & (uint32)0xfffffffe) | (uint32)(value & 1));
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}
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void ICACHE_FLASH_ATTR
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gpio16_input_conf(void)
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{
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WRITE_PERI_REG(PAD_XPD_DCDC_CONF,
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(READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32)0x1); // mux configuration for XPD_DCDC and rtc_gpio0 connection
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WRITE_PERI_REG(RTC_GPIO_CONF,
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(READ_PERI_REG(RTC_GPIO_CONF) & (uint32)0xfffffffe) | (uint32)0x0); //mux configuration for out enable
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WRITE_PERI_REG(RTC_GPIO_ENABLE,
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READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe); //out disable
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}
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uint8 ICACHE_FLASH_ATTR
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gpio16_input_get(void)
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{
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return (uint8)(READ_PERI_REG(RTC_GPIO_IN_DATA) & 1);
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}
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