From f8c69be47750cfbd840c2247ecde2289872f7e26 Mon Sep 17 00:00:00 2001 From: Dong Heng Date: Tue, 10 Jul 2018 19:51:12 +0800 Subject: [PATCH 1/3] feat(spi_flash): Add feature to support flash address and memory address no align writing --- components/spi_flash/include/spi_flash.h | 2 + components/spi_flash/src/spi_flash.c | 147 +++++++++++++++-------- 2 files changed, 99 insertions(+), 50 deletions(-) diff --git a/components/spi_flash/include/spi_flash.h b/components/spi_flash/include/spi_flash.h index f6a83319..28ae64c0 100644 --- a/components/spi_flash/include/spi_flash.h +++ b/components/spi_flash/include/spi_flash.h @@ -30,6 +30,8 @@ extern "C" { #define SPI_FLASH_SEC_SIZE 4096 /**< SPI Flash sector size */ +#define SPI_READ_BUF_MAX 64 + #ifdef CONFIG_ENABLE_FLASH_MMAP /** * @brief Enumeration which specifies memory space requested in an mmap call diff --git a/components/spi_flash/src/spi_flash.c b/components/spi_flash/src/spi_flash.c index b7e99e21..275fa908 100644 --- a/components/spi_flash/src/spi_flash.c +++ b/components/spi_flash/src/spi_flash.c @@ -100,6 +100,9 @@ #define FLASH_ALIGN_BYTES 4 #define FLASH_ALIGN(addr) ((((size_t)addr) + (FLASH_ALIGN_BYTES - 1)) & (~(FLASH_ALIGN_BYTES - 1))) +#define FLASH_ALIGN_BEFORE(addr) (FLASH_ALIGN(addr) - 4) +#define NOT_ALIGN(addr) (((size_t)addr) & (FLASH_ALIGN_BYTES - 1)) +#define IS_ALIGN(addr) (NOT_ALIGN(addr) == 0) enum GD25Q32C_status { GD25Q32C_STATUS1=0, @@ -129,6 +132,7 @@ extern uint32_t esp_get_time(); bool IRAM_ATTR spi_user_cmd(spi_cmd_dir_t mode, spi_cmd_t *p_cmd); bool special_flash_read_status(uint8_t command, uint32_t* status, int len); bool special_flash_write_status(uint8_t command, uint32_t status, int len, bool write_en); +esp_err_t spi_flash_read(size_t src_addr, void *dest, size_t size); uint8_t en25q16x_read_sfdp(); extern void pp_soft_wdt_feed(void); @@ -148,7 +152,7 @@ uint8_t FlashIsOnGoing = 0; const char *TAG = "spi_flash"; -static esp_err_t IRAM_ATTR SPIWrite(uint32_t target, uint32_t *src_addr, size_t len) +esp_err_t IRAM_ATTR SPIWrite(uint32_t target, uint32_t *src_addr, size_t len) { uint32_t page_size; uint32_t pgm_len, pgm_num; @@ -481,17 +485,30 @@ static esp_err_t IRAM_ATTR spi_flash_write_raw(size_t dest_addr, const void *src esp_err_t IRAM_ATTR spi_flash_write(size_t dest_addr, const void *src, size_t size) { +#undef FLASH_WRITE #define FLASH_WRITE(dest, src, size) \ { \ ret = spi_flash_write_raw(dest, src, size); \ pp_soft_wdt_feed(); \ - if (ret) \ - goto exit; \ + if (ret) { \ + return ret; \ + } \ +} + +#undef FLASH_READ +#define FLASH_READ(dest, src, size) \ +{ \ + ret = spi_flash_read(dest, src, size); \ + if (ret) { \ + return ret; \ + } \ } esp_err_t ret = ESP_ERR_FLASH_OP_FAIL; - uint32_t *tmp; - size_t before_wbytes, align_wbytes; + uint8_t *tmp = (uint8_t *)src; + + if (!size) + return ESP_OK; if (src == NULL) { return ESP_ERR_FLASH_OP_FAIL; @@ -501,41 +518,54 @@ esp_err_t IRAM_ATTR spi_flash_write(size_t dest_addr, const void *src, size_t si return ESP_ERR_FLASH_OP_FAIL; } - if (IS_FLASH(src)) { - tmp = wifi_malloc(size, OSI_MALLOC_CAP_32BIT); - if (!tmp) { - return ESP_ERR_NO_MEM; + if (NOT_ALIGN(dest_addr) + || NOT_ALIGN(tmp) + || NOT_ALIGN(size) + || IS_FLASH(src)) { + uint8_t buf[SPI_READ_BUF_MAX]; + + if (NOT_ALIGN(dest_addr)) { + size_t r_addr = FLASH_ALIGN_BEFORE(dest_addr); + size_t c_off = dest_addr - r_addr; + size_t wbytes = FLASH_ALIGN_BYTES - c_off; + + wbytes = wbytes > size ? size : wbytes; + + FLASH_READ(r_addr, buf, FLASH_ALIGN_BYTES); + memcpy(&buf[c_off], tmp, wbytes); + FLASH_WRITE(r_addr, buf, FLASH_ALIGN_BYTES); + + dest_addr += wbytes; + tmp += wbytes; + size -= wbytes; } - memcpy(tmp, src, size); - } else - tmp = (uint32_t *)src; - before_wbytes = FLASH_ALIGN(tmp) == (size_t)tmp ? 0 : FLASH_ALIGN(tmp) - (size_t)tmp; - align_wbytes = size - before_wbytes; + while (size > 0) { + size_t len = size >= SPI_READ_BUF_MAX ? SPI_READ_BUF_MAX : size; + size_t wlen = FLASH_ALIGN(len); - if (before_wbytes) { - uint8_t load_buf[FLASH_ALIGN_BYTES]; + if (wlen != len) { + size_t l_b = wlen - FLASH_ALIGN_BYTES; - memcpy(load_buf, tmp, before_wbytes); - FLASH_WRITE(dest_addr, load_buf, FLASH_ALIGN_BYTES); + FLASH_READ(dest_addr + l_b, &buf[l_b], FLASH_ALIGN_BYTES); + } + + memcpy(buf, tmp, len); + + FLASH_WRITE(dest_addr, buf, wlen); + + dest_addr += len; + tmp += len; + size -= len; + } + } else { + FLASH_WRITE(dest_addr, src, size); } - if (align_wbytes) { - void *align_addr = (void *)FLASH_ALIGN(tmp); - - if (align_wbytes % FLASH_ALIGN_BYTES) - align_wbytes = (align_wbytes / FLASH_ALIGN_BYTES + 1) * FLASH_ALIGN_BYTES; - - FLASH_WRITE(dest_addr + before_wbytes, align_addr, align_wbytes); - } - -exit: - if (IS_FLASH(src)) - wifi_free(tmp); - return ret; } + /****************************************************************************** * FunctionName : spi_flash_read_raw * Description : a @@ -568,42 +598,59 @@ static esp_err_t IRAM_ATTR spi_flash_read_raw(size_t src_addr, void *dest, size_ esp_err_t IRAM_ATTR spi_flash_read(size_t src_addr, void *dest, size_t size) { +#undef FLASH_READ #define FLASH_READ(addr, dest, size) \ { \ - ret = spi_flash_read_raw(src_addr, dest, size); \ + ret = spi_flash_read_raw(addr, dest, size); \ pp_soft_wdt_feed(); \ if (ret) \ return ret; \ } esp_err_t ret; - uint8_t load_buf[FLASH_ALIGN_BYTES]; - size_t before_rbytes, after_rbytes, align_rbytes; + uint8_t *tmp = (uint8_t *)dest; - if (dest == NULL) { + if (!size) + return ESP_OK; + + if (tmp == NULL) { return ESP_ERR_FLASH_OP_FAIL; } - before_rbytes = FLASH_ALIGN(dest) == (size_t)dest ? 0 : FLASH_ALIGN(dest) - (size_t)dest; - after_rbytes = (size - before_rbytes) & (FLASH_ALIGN_BYTES - 1); - align_rbytes = size - before_rbytes - after_rbytes; + if (NOT_ALIGN(src_addr) + || NOT_ALIGN(tmp) + || NOT_ALIGN(size)) { + uint8_t buf[SPI_READ_BUF_MAX]; - if (before_rbytes) { - FLASH_READ(src_addr, load_buf, FLASH_ALIGN_BYTES); - memcpy(dest, &load_buf[FLASH_ALIGN_BYTES - before_rbytes], before_rbytes); - } + if (NOT_ALIGN(src_addr)) { + size_t r_addr = FLASH_ALIGN_BEFORE(src_addr); + size_t c_off = src_addr - r_addr; + size_t wbytes = FLASH_ALIGN_BYTES - c_off; - if (align_rbytes) { - void *align_addr = (void *)FLASH_ALIGN(dest); + wbytes = wbytes > size ? size : wbytes; - FLASH_READ(src_addr + before_rbytes, align_addr, align_rbytes); - } + FLASH_READ(r_addr, buf, FLASH_ALIGN_BYTES); + memcpy(tmp, &buf[c_off], wbytes); - if (after_rbytes) { - void *after_addr = (void *)FLASH_ALIGN((char *)dest + size - after_rbytes); + tmp += wbytes; + src_addr += wbytes; + size -= wbytes; + } - FLASH_READ(src_addr + before_rbytes + align_rbytes, load_buf, FLASH_ALIGN_BYTES); - memcpy(after_addr, load_buf, after_rbytes); + while (size) { + size_t len = size >= SPI_READ_BUF_MAX ? SPI_READ_BUF_MAX : size; + size_t wlen = FLASH_ALIGN(len); + + FLASH_READ(src_addr, buf, wlen); + + memcpy(tmp, buf, len); + + src_addr += len; + tmp += len; + size -= len; + } + } else { + FLASH_READ(src_addr, tmp, size); } return ESP_OK; From b435e1ac0dc42f6ada6f81ee93448c35f0cd7b98 Mon Sep 17 00:00:00 2001 From: Dong Heng Date: Wed, 11 Jul 2018 14:52:27 +0800 Subject: [PATCH 2/3] feat(spi_flash): Bring unit test from esp-idf --- components/spi_flash/test/component.mk | 5 + components/spi_flash/test/test_read_write.c | 268 ++++++++++++++++++++ 2 files changed, 273 insertions(+) create mode 100644 components/spi_flash/test/component.mk create mode 100644 components/spi_flash/test/test_read_write.c diff --git a/components/spi_flash/test/component.mk b/components/spi_flash/test/component.mk new file mode 100644 index 00000000..5dd172bd --- /dev/null +++ b/components/spi_flash/test/component.mk @@ -0,0 +1,5 @@ +# +#Component Makefile +# + +COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive diff --git a/components/spi_flash/test/test_read_write.c b/components/spi_flash/test/test_read_write.c new file mode 100644 index 00000000..8b1061b9 --- /dev/null +++ b/components/spi_flash/test/test_read_write.c @@ -0,0 +1,268 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Test for spi_flash_{read,write}. + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include "../cache_utils.h" +#include "soc/timer_group_struct.h" +#include "soc/timer_group_reg.h" +#include "esp_heap_caps.h" + +/* Base offset in flash for tests. */ +static size_t start; + +static void setup_tests() +{ + if (start == 0) { + const esp_partition_t *part = get_test_data_partition(); + start = part->address; + printf("Test data partition @ 0x%x\n", start); + } +} + +#ifndef CONFIG_SPI_FLASH_MINIMAL_TEST +#define CONFIG_SPI_FLASH_MINIMAL_TEST 1 +#endif + +static void fill(char *dest, int32_t start, int32_t len) +{ + for (int32_t i = 0; i < len; i++) { + *(dest + i) = (char) (start + i); + } +} + +static int cmp_or_dump(const void *a, const void *b, size_t len) +{ + int r = memcmp(a, b, len); + if (r != 0) { + for (int i = 0; i < len; i++) { + fprintf(stderr, "%02x", ((unsigned char *) a)[i]); + } + fprintf(stderr, "\n"); + for (int i = 0; i < len; i++) { + fprintf(stderr, "%02x", ((unsigned char *) b)[i]); + } + fprintf(stderr, "\n"); + } + return r; +} + +static void IRAM_ATTR test_read(int src_off, int dst_off, int len) +{ + uint32_t src_buf[16]; + char dst_buf[64], dst_gold[64]; + + fprintf(stderr, "src=%d dst=%d len=%d\n", src_off, dst_off, len); + memset(src_buf, 0xAA, sizeof(src_buf)); + fill(((char *) src_buf) + src_off, src_off, len); + ESP_ERROR_CHECK(spi_flash_erase_sector((start + src_off) / SPI_FLASH_SEC_SIZE)); + spi_flash_disable_interrupts_caches_and_other_cpu(); + esp_rom_spiflash_result_t rc = esp_rom_spiflash_write(start, src_buf, sizeof(src_buf)); + spi_flash_enable_interrupts_caches_and_other_cpu(); + TEST_ASSERT_EQUAL_INT(rc, ESP_ROM_SPIFLASH_RESULT_OK); + memset(dst_buf, 0x55, sizeof(dst_buf)); + memset(dst_gold, 0x55, sizeof(dst_gold)); + fill(dst_gold + dst_off, src_off, len); + ESP_ERROR_CHECK(spi_flash_read(start + src_off, dst_buf + dst_off, len)); + TEST_ASSERT_EQUAL_INT(cmp_or_dump(dst_buf, dst_gold, sizeof(dst_buf)), 0); +} + +TEST_CASE("Test spi_flash_read", "[spi_flash]") +{ + setup_tests(); +#if CONFIG_SPI_FLASH_MINIMAL_TEST + test_read(0, 0, 0); + test_read(0, 0, 4); + test_read(0, 0, 16); + test_read(0, 0, 64); + test_read(0, 0, 1); + test_read(0, 1, 1); + test_read(1, 0, 1); + test_read(1, 1, 1); + test_read(1, 1, 2); + test_read(1, 1, 3); + test_read(1, 1, 4); + test_read(1, 1, 5); + test_read(3, 2, 5); + test_read(0, 0, 17); + test_read(0, 1, 17); + test_read(1, 0, 17); + test_read(1, 1, 17); + test_read(1, 1, 18); + test_read(1, 1, 19); + test_read(1, 1, 20); + test_read(1, 1, 21); + test_read(3, 2, 21); + test_read(4, 4, 60); + test_read(59, 0, 5); + test_read(60, 0, 4); + test_read(60, 0, 3); + test_read(60, 0, 2); + test_read(63, 0, 1); + test_read(64, 0, 0); + test_read(59, 59, 5); + test_read(60, 60, 4); + test_read(60, 60, 3); + test_read(60, 60, 2); + test_read(63, 63, 1); + test_read(64, 64, 0); +#else + /* This will run a more thorough test but will slam flash pretty hard. */ + for (int src_off = 1; src_off < 16; src_off++) { + for (int dst_off = 0; dst_off < 16; dst_off++) { + for (int len = 0; len < 32; len++) { + test_read(dst_off, src_off, len); + } + } + } +#endif +} + +static void IRAM_ATTR test_write(int dst_off, int src_off, int len) +{ + char src_buf[64], dst_gold[64]; + uint32_t dst_buf[16]; + fprintf(stderr, "dst=%d src=%d len=%d\n", dst_off, src_off, len); + memset(src_buf, 0x55, sizeof(src_buf)); + fill(src_buf + src_off, src_off, len); + // Fills with 0xff + ESP_ERROR_CHECK(spi_flash_erase_sector((start + dst_off) / SPI_FLASH_SEC_SIZE)); + memset(dst_gold, 0xff, sizeof(dst_gold)); + if (len > 0) { + int pad_left_off = (dst_off & ~3U); + memset(dst_gold + pad_left_off, 0xff, 4); + if (dst_off + len > pad_left_off + 4 && (dst_off + len) % 4 != 0) { + int pad_right_off = ((dst_off + len) & ~3U); + memset(dst_gold + pad_right_off, 0xff, 4); + } + fill(dst_gold + dst_off, src_off, len); + } + ESP_ERROR_CHECK(spi_flash_write(start + dst_off, src_buf + src_off, len)); + spi_flash_disable_interrupts_caches_and_other_cpu(); + esp_rom_spiflash_result_t rc = esp_rom_spiflash_read(start, dst_buf, sizeof(dst_buf)); + spi_flash_enable_interrupts_caches_and_other_cpu(); + TEST_ASSERT_EQUAL_INT(rc, ESP_ROM_SPIFLASH_RESULT_OK); + TEST_ASSERT_EQUAL_INT(cmp_or_dump(dst_buf, dst_gold, sizeof(dst_buf)), 0); +} + +TEST_CASE("Test spi_flash_write", "[spi_flash]") +{ + setup_tests(); +#if CONFIG_SPI_FLASH_MINIMAL_TEST + test_write(0, 0, 0); + test_write(0, 0, 4); + test_write(0, 0, 16); + test_write(0, 0, 64); + test_write(0, 0, 1); + test_write(0, 1, 1); + test_write(1, 0, 1); + test_write(1, 1, 1); + test_write(1, 1, 2); + test_write(1, 1, 3); + test_write(1, 1, 4); + test_write(1, 1, 5); + test_write(3, 2, 5); + test_write(4, 4, 60); + test_write(59, 0, 5); + test_write(60, 0, 4); + test_write(60, 0, 3); + test_write(60, 0, 2); + test_write(63, 0, 1); + test_write(64, 0, 0); + test_write(59, 59, 5); + test_write(60, 60, 4); + test_write(60, 60, 3); + test_write(60, 60, 2); + test_write(63, 63, 1); + test_write(64, 64, 0); +#else + /* This will run a more thorough test but will slam flash pretty hard. */ + for (int dst_off = 1; dst_off < 16; dst_off++) { + for (int src_off = 0; src_off < 16; src_off++) { + for (int len = 0; len < 16; len++) { + test_write(dst_off, src_off, len); + } + } + } +#endif + /* + * Test writing from ROM, IRAM and caches. We don't know what exactly will be + * written, we're testing that there's no crash here. + * + * NB: At the moment these only support aligned addresses, because memcpy + * is not aware of the 32-but load requirements for these regions. + */ + ESP_ERROR_CHECK(spi_flash_write(start, (char *) 0x40000000, 16)); + ESP_ERROR_CHECK(spi_flash_write(start, (char *) 0x40070000, 16)); + ESP_ERROR_CHECK(spi_flash_write(start, (char *) 0x40078000, 16)); + ESP_ERROR_CHECK(spi_flash_write(start, (char *) 0x40080000, 16)); +} + +#ifdef CONFIG_SPIRAM_SUPPORT + +TEST_CASE("spi_flash_read can read into buffer in external RAM", "[spi_flash]") +{ + uint8_t* buf_ext = (uint8_t*) heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT); + TEST_ASSERT_NOT_NULL(buf_ext); + + uint8_t* buf_int = (uint8_t*) heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + TEST_ASSERT_NOT_NULL(buf_int); + + TEST_ESP_OK(spi_flash_read(0x1000, buf_int, SPI_FLASH_SEC_SIZE)); + TEST_ESP_OK(spi_flash_read(0x1000, buf_ext, SPI_FLASH_SEC_SIZE)); + + TEST_ASSERT_EQUAL(0, memcmp(buf_ext, buf_int, SPI_FLASH_SEC_SIZE)); + free(buf_ext); + free(buf_int); +} + +TEST_CASE("spi_flash_write can write from external RAM buffer", "[spi_flash]") +{ + uint32_t* buf_ext = (uint32_t*) heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT); + TEST_ASSERT_NOT_NULL(buf_ext); + + srand(0); + for (size_t i = 0; i < SPI_FLASH_SEC_SIZE / sizeof(uint32_t); i++) + { + uint32_t val = rand(); + buf_ext[i] = val; + } + + uint8_t* buf_int = (uint8_t*) heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + TEST_ASSERT_NOT_NULL(buf_int); + + /* Write to flash from buf_ext */ + const esp_partition_t *part = get_test_data_partition(); + TEST_ESP_OK(spi_flash_erase_range(part->address, SPI_FLASH_SEC_SIZE)); + TEST_ESP_OK(spi_flash_write(part->address, buf_ext, SPI_FLASH_SEC_SIZE)); + + /* Read back to buf_int and compare */ + TEST_ESP_OK(spi_flash_read(part->address, buf_int, SPI_FLASH_SEC_SIZE)); + TEST_ASSERT_EQUAL(0, memcmp(buf_ext, buf_int, SPI_FLASH_SEC_SIZE)); + + free(buf_ext); + free(buf_int); +} + +#endif // CONFIG_SPIRAM_SUPPORT From a4be553fc9a84726e3cfc1d0eb43a52509dd0264 Mon Sep 17 00:00:00 2001 From: Dong Heng Date: Wed, 11 Jul 2018 14:56:20 +0800 Subject: [PATCH 3/3] feat(spi_flash): Modify unit test for esp8266 --- components/spi_flash/test/test_read_write.c | 22 ++++++--------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/components/spi_flash/test/test_read_write.c b/components/spi_flash/test/test_read_write.c index 8b1061b9..49619e3c 100644 --- a/components/spi_flash/test/test_read_write.c +++ b/components/spi_flash/test/test_read_write.c @@ -21,13 +21,8 @@ #include #include -#include #include -#include -#include "../cache_utils.h" -#include "soc/timer_group_struct.h" -#include "soc/timer_group_reg.h" -#include "esp_heap_caps.h" +#include "esp_attr.h" /* Base offset in flash for tests. */ static size_t start; @@ -35,8 +30,7 @@ static size_t start; static void setup_tests() { if (start == 0) { - const esp_partition_t *part = get_test_data_partition(); - start = part->address; + start = 0x90000; printf("Test data partition @ 0x%x\n", start); } } @@ -77,10 +71,8 @@ static void IRAM_ATTR test_read(int src_off, int dst_off, int len) memset(src_buf, 0xAA, sizeof(src_buf)); fill(((char *) src_buf) + src_off, src_off, len); ESP_ERROR_CHECK(spi_flash_erase_sector((start + src_off) / SPI_FLASH_SEC_SIZE)); - spi_flash_disable_interrupts_caches_and_other_cpu(); - esp_rom_spiflash_result_t rc = esp_rom_spiflash_write(start, src_buf, sizeof(src_buf)); - spi_flash_enable_interrupts_caches_and_other_cpu(); - TEST_ASSERT_EQUAL_INT(rc, ESP_ROM_SPIFLASH_RESULT_OK); + esp_err_t rc = spi_flash_write(start, src_buf, sizeof(src_buf)); + TEST_ASSERT_EQUAL_INT(rc, ESP_OK); memset(dst_buf, 0x55, sizeof(dst_buf)); memset(dst_gold, 0x55, sizeof(dst_gold)); fill(dst_gold + dst_off, src_off, len); @@ -159,10 +151,8 @@ static void IRAM_ATTR test_write(int dst_off, int src_off, int len) fill(dst_gold + dst_off, src_off, len); } ESP_ERROR_CHECK(spi_flash_write(start + dst_off, src_buf + src_off, len)); - spi_flash_disable_interrupts_caches_and_other_cpu(); - esp_rom_spiflash_result_t rc = esp_rom_spiflash_read(start, dst_buf, sizeof(dst_buf)); - spi_flash_enable_interrupts_caches_and_other_cpu(); - TEST_ASSERT_EQUAL_INT(rc, ESP_ROM_SPIFLASH_RESULT_OK); + esp_err_t rc = spi_flash_read(start, dst_buf, sizeof(dst_buf)); + TEST_ASSERT_EQUAL_INT(rc, ESP_OK); TEST_ASSERT_EQUAL_INT(cmp_or_dump(dst_buf, dst_gold, sizeof(dst_buf)), 0); }