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feat(system): Add global ISR swith

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This commit is contained in:
dongheng
2019-04-24 11:11:24 +08:00
parent 556fe6b926
commit e7b8e9fa25
8 changed files with 20 additions and 38 deletions
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2
components/esp8266/include/esp8266/eagle_soc.h
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@ -123,6 +123,8 @@
#define TM1_EDGE_INT_DISABLE() CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
//}}
#define INT_ENA_WDEV 0x3ff20c18
#define WDEV_TSF0_REACH_INT (BIT(27))
//Watch dog reg {{
#define PERIPHS_WDT_BASEADDR 0x60000900

34
components/esp8266/include/rom/ets_sys.h
View File

@ -53,39 +53,9 @@ typedef enum {
CANCEL,
} STATUS;
extern char NMIIrqIsOn;
extern uint32_t WDEV_INTEREST_EVENT;
void vPortETSIntrLock(void);
#define INT_ENA_WDEV 0x3ff20c18
#define WDEV_TSF0_REACH_INT (BIT(27))
#define ETS_NMI_LOCK() \
do { \
do { \
REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT); \
} while(REG_READ(INT_ENA_WDEV) != WDEV_TSF0_REACH_INT); \
} while (0)
#define ETS_NMI_UNLOCK() \
do { \
REG_WRITE(INT_ENA_WDEV, WDEV_INTEREST_EVENT); \
} while (0)
#define ETS_INTR_LOCK() do { \
if (NMIIrqIsOn == 0) { \
vPortEnterCritical(); \
do { \
REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT); \
} while(REG_READ(INT_ENA_WDEV) != WDEV_TSF0_REACH_INT); \
} \
} while(0)
#define ETS_INTR_UNLOCK() do { \
if (NMIIrqIsOn == 0) { \
REG_WRITE(INT_ENA_WDEV, WDEV_INTEREST_EVENT); \
vPortExitCritical(); \
} \
} while(0)
void vPortETSIntrUnlock(void);
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"