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feat(structure): Re-structure some include

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This commit is contained in:
Wu Jian Gang
2018-04-08 19:51:42 +08:00
parent e0c8631ab6
commit e3cdb2dae3
31 changed files with 6 additions and 4 deletions
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126
components/esp8266/include/esp8266/eagle_soc.h Normal file
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/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _EAGLE_SOC_H_
#define _EAGLE_SOC_H_
//Register Bits{{
#define BIT31 0x80000000
#define BIT30 0x40000000
#define BIT29 0x20000000
#define BIT28 0x10000000
#define BIT27 0x08000000
#define BIT26 0x04000000
#define BIT25 0x02000000
#define BIT24 0x01000000
#define BIT23 0x00800000
#define BIT22 0x00400000
#define BIT21 0x00200000
#define BIT20 0x00100000
#define BIT19 0x00080000
#define BIT18 0x00040000
#define BIT17 0x00020000
#define BIT16 0x00010000
#define BIT15 0x00008000
#define BIT14 0x00004000
#define BIT13 0x00002000
#define BIT12 0x00001000
#define BIT11 0x00000800
#define BIT10 0x00000400
#define BIT9 0x00000200
#define BIT8 0x00000100
#define BIT7 0x00000080
#define BIT6 0x00000040
#define BIT5 0x00000020
#define BIT4 0x00000010
#define BIT3 0x00000008
#define BIT2 0x00000004
#define BIT1 0x00000002
#define BIT0 0x00000001
//}}
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#define READ_PERI_REG(addr) (*((volatile uint32 *)ETS_UNCACHED_ADDR(addr)))
#define WRITE_PERI_REG(addr, val) (*((volatile uint32 *)ETS_UNCACHED_ADDR(addr))) = (uint32)(val)
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg) & (~(mask))))
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg) | (mask)))
#define GET_PERI_REG_BITS(reg, hipos, lowpos) ((READ_PERI_REG(reg) >> (lowpos)) & ((1 << ((hipos) - (lowpos) + 1)) - 1))
#define SET_PERI_REG_BITS(reg, bit_map, value, shift) (WRITE_PERI_REG((reg), (READ_PERI_REG(reg) & (~((bit_map) << (shift)))) | ((value) << (shift)) ))
//}}
//Periheral Clock {{
#define CPU_CLK_FREQ 80 * 1000000 // unit: Hz
#define APB_CLK_FREQ CPU_CLK_FREQ
#define UART_CLK_FREQ APB_CLK_FREQ
#define TIMER_CLK_FREQ (APB_CLK_FREQ >> 8) // divided by 256
//}}
//Peripheral device base address define{{
#define PERIPHS_DPORT_BASEADDR 0x3ff00000
#define PERIPHS_RTC_BASEADDR 0x60000700
//}}
//DPORT{{
#define HOST_INF_SEL (PERIPHS_DPORT_BASEADDR + 0x28)
#define DPORT_LINK_DEVICE_SEL 0x000000FF
#define DPORT_LINK_DEVICE_SEL_S 8
#define DPORT_PERI_IO_SWAP 0x000000FF
#define DPORT_PERI_IO_SWAP_S 0
#define PERI_IO_CSPI_OVERLAP (BIT(7)) // two spi masters on cspi
#define PERI_IO_HSPI_OVERLAP (BIT(6)) // two spi masters on hspi
#define PERI_IO_HSPI_PRIO (BIT(5)) // hspi is with the higher prior
#define PERI_IO_UART1_PIN_SWAP (BIT(3)) // swap uart1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts)
#define PERI_IO_UART0_PIN_SWAP (BIT(2)) // swap uart0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts)
#define PERI_IO_SPI_PORT_SWAP (BIT(1)) // swap two spi
#define PERI_IO_UART_PORT_SWAP (BIT(0)) // swap two uart
//}}
//Interrupt remap control registers define{{
#define EDGE_INT_ENABLE_REG (PERIPHS_DPORT_BASEADDR + 0x04)
#define TM1_EDGE_INT_ENABLE() SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
#define TM1_EDGE_INT_DISABLE() CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
//}}
//RTC reg {{
#define REG_RTC_BASE PERIPHS_RTC_BASEADDR
#define RTC_SLP_VAL (REG_RTC_BASE + 0x004) // the target value of RTC_COUNTER for wakeup from light-sleep/deep-sleep
#define RTC_SLP_CNT_VAL (REG_RTC_BASE + 0x01C) // the current value of RTC_COUNTER
#define RTC_SCRATCH0 (REG_RTC_BASE + 0x030) // the register for software to save some values for watchdog reset
#define RTC_SCRATCH1 (REG_RTC_BASE + 0x034) // the register for software to save some values for watchdog reset
#define RTC_SCRATCH2 (REG_RTC_BASE + 0x038) // the register for software to save some values for watchdog reset
#define RTC_SCRATCH3 (REG_RTC_BASE + 0x03C) // the register for software to save some values for watchdog reset
#define RTC_GPIO_OUT (REG_RTC_BASE + 0x068) // used by gpio16
#define RTC_GPIO_ENABLE (REG_RTC_BASE + 0x074)
#define RTC_GPIO_IN_DATA (REG_RTC_BASE + 0x08C)
#define RTC_GPIO_CONF (REG_RTC_BASE + 0x090)
#define PAD_XPD_DCDC_CONF (REG_RTC_BASE + 0x0A0)
//}}
#endif //_EAGLE_SOC_H_

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components/esp8266/include/esp8266/esp8266.h Normal file
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/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __ESP8266_H__
#define __ESP8266_H__
#include "ets_sys.h"
#include "eagle_soc.h"
#include "gpio_register.h"
#include "pin_mux_register.h"
#include "spi_register.h"
#include "timer_register.h"
#include "uart_register.h"
#endif

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components/esp8266/include/esp8266/ets_sys.h Normal file
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/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __ETS_SYS_H__
#define __ETS_SYS_H__
/* interrupt related */
#define ETS_SPI_INUM 2
#define ETS_GPIO_INUM 4
#define ETS_UART_INUM 5
#define ETS_MAX_INUM 6
#define ETS_SOFT_INUM 7
#define ETS_WDT_INUM 8
#define ETS_FRC_TIMER1_INUM 9
extern char NMIIrqIsOn;
extern uint32 WDEV_INTEREST_EVENT;
#define INT_ENA_WDEV 0x3ff20c18
#define WDEV_TSF0_REACH_INT (BIT(27))
#define ETS_NMI_LOCK() \
do { \
char m = 10; \
do { \
REG_WRITE(INT_ENA_WDEV, 0); \
m = 10; \
for (; m > 0; m--) {} \
REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT); \
} while(0); \
} while (0)
#define ETS_NMI_UNLOCK() \
do { \
REG_WRITE(INT_ENA_WDEV, WDEV_INTEREST_EVENT); \
} while (0)
#define ETS_INTR_LOCK() do { \
if (NMIIrqIsOn == 0) { \
vPortEnterCritical(); \
char m = 10; \
do { \
REG_WRITE(INT_ENA_WDEV, 0); \
m = 10; \
for (; m > 0; m--) {} \
REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT); \
} while(0); \
} \
} while(0)
#define ETS_INTR_UNLOCK() do { \
if (NMIIrqIsOn == 0) { \
REG_WRITE(INT_ENA_WDEV, WDEV_INTEREST_EVENT); \
vPortExitCritical(); \
} \
} while(0)
#endif /* _ETS_SYS_H */

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/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _GPIO_REGISTER_H_
#define _GPIO_REGISTER_H_
#define PERIPHS_GPIO_BASEADDR 0x60000300
#define GPIO_OUT_ADDRESS 0x00
#define GPIO_BT_SEL 0x0000ffff
#define GPIO_BT_SEL_S 16
#define GPIO_OUT_DATA 0x0000ffff
#define GPIO_OUT_DATA_S 0
#define GPIO_OUT_W1TS_ADDRESS 0x04
#define GPIO_OUT_DATA_W1TS 0x0000ffff
#define GPIO_OUT_DATA_W1TS_S 0
#define GPIO_OUT_W1TC_ADDRESS 0x08
#define GPIO_OUT_DATA_W1TC 0x0000ffff
#define GPIO_OUT_DATA_W1TC_S 0
#define GPIO_OUT_DATA_MASK 0x0000ffff
#define GPIO_ENABLE_ADDRESS 0x0c
#define GPIO_SDIO_SEL 0x0000003f
#define GPIO_SDIO_SEL_S 16
#define GPIO_ENABLE_DATA 0x0000ffff
#define GPIO_ENABLE_DATA_S 0
#define GPIO_ENABLE_W1TS_ADDRESS 0x10
#define GPIO_ENABLE_DATA_W1TS 0x0000ffff
#define GPIO_ENABLE_DATA_W1TS_s 0
#define GPIO_ENABLE_W1TC_ADDRESS 0x14
#define GPIO_ENABLE_DATA_W1TC 0x0000ffff
#define GPIO_ENABLE_DATA_W1TC_S 0
#define GPIO_ENABLE_DATA_DATA_MASK 0x0000ffff
#define GPIO_IN_ADDRESS 0x18
#define GPIO_STRAPPING 0x0000ffff
#define GPIO_STRAPPING_S 16
#define GPIO_IN_DATA 0x0000ffff
#define GPIO_IN_DATA_S 0
#define GPIO_STATUS_ADDRESS 0x1c
#define GPIO_STATUS_INTERRUPT 0x0000ffff
#define GPIO_STATUS_INTERRUPT_S 0
#define GPIO_STATUS_W1TS_ADDRESS 0x20
#define GPIO_STATUS_INTERRUPT_W1TS 0x0000ffff
#define GPIO_STATUS_INTERRUPT_W1TS_S 0
#define GPIO_STATUS_W1TC_ADDRESS 0x24
#define GPIO_STATUS_INTERRUPT_W1TC 0x0000ffff
#define GPIO_STATUS_INTERRUPT_W1TC_S 0
#define GPIO_STATUS_INTERRUPT_DATA_MASK 0x0000ffff
//Region1: used for gpio config for GPIO_PIN0_ADDRESS~GPIO_PIN15_ADDRESS
#define GPIO_ID_PIN0 0
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(15)
#define GPIO_ID_NONE 0xffffffff
#define GPIO_PIN_COUNT 16
#define GPIO_PIN_CONFIG_MSB 12
#define GPIO_PIN_CONFIG_LSB 11
#define GPIO_PIN_CONFIG_MASK (0x00000003<<GPIO_PIN_CONFIG_LSB)
#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
#define GPIO_WAKEUP_ENABLE 1
#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE)
#define GPIO_PIN_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN_WAKEUP_ENABLE_MASK (0x00000001<<GPIO_PIN_WAKEUP_ENABLE_LSB)
#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
#define GPIO_PIN_INT_TYPE_MSB 9
#define GPIO_PIN_INT_TYPE_LSB 7
#define GPIO_PIN_INT_TYPE_MASK (0x00000007<<GPIO_PIN_INT_TYPE_LSB)
#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
#define GPIO_PAD_DRIVER_ENABLE 1
#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE)
#define GPIO_PIN_DRIVER_MSB 2
#define GPIO_PIN_DRIVER_LSB 2
#define GPIO_PIN_DRIVER_MASK (0x00000001<<GPIO_PIN_DRIVER_LSB)
#define GPIO_PIN_DRIVER_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_DRIVER_LSB) & GPIO_PIN_DRIVER_MASK)
#define GPIO_PIN_SOURCE_MSB 0
#define GPIO_PIN_SOURCE_LSB 0
#define GPIO_PIN_SOURCE_MASK (0x00000001<<GPIO_PIN_SOURCE_LSB)
#define GPIO_PIN_SOURCE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
#define GPIO_PIN_SOURCE_SET(x) (((x) << GPIO_PIN_SOURCE_LSB) & GPIO_PIN_SOURCE_MASK)
//end of region1
#define GPIO_PIN0_ADDRESS 0x28
#define GPIO_PIN0_CONFIG 0x00000003
#define GPIO_PIN0_CONFIG_S 11
#define GPIO_PIN0_WAKEUP_ENABLE BIT10
#define GPIO_PIN0_WAKEUP_ENABLE_S 10
#define GPIO_PIN0_INT_TYPE 0x00000007
#define GPIO_PIN0_INT_TYPE_S 7
#define GPIO_PIN0_DRIVER BIT2
#define GPIO_PIN0_DRIVER_S 2
#define GPIO_PIN0_SOURCE BIT0
#define GPIO_PIN0_SOURCE_S 0
#define GPIO_PIN1_ADDRESS 0x2c
#define GPIO_PIN1_CONFIG 0x00000003
#define GPIO_PIN1_CONFIG_S 11
#define GPIO_PIN1_WAKEUP_ENABLE BIT10
#define GPIO_PIN1_WAKEUP_ENABLE_S 10
#define GPIO_PIN1_INT_TYPE 0x00000007
#define GPIO_PIN1_INT_TYPE_S 7
#define GPIO_PIN1_DRIVER BIT2
#define GPIO_PIN1_DRIVER_S 2
#define GPIO_PIN1_SOURCE BIT0
#define GPIO_PIN1_SOURCE_S 0
#define GPIO_PIN2_ADDRESS 0x30
#define GPIO_PIN2_CONFIG 0x00000003
#define GPIO_PIN2_CONFIG_S 11
#define GPIO_PIN2_WAKEUP_ENABLE BIT10
#define GPIO_PIN2_WAKEUP_ENABLE_S 10
#define GPIO_PIN2_INT_TYPE 0x00000007
#define GPIO_PIN2_INT_TYPE_S 7
#define GPIO_PIN2_DRIVER BIT2
#define GPIO_PIN2_DRIVER_S 2
#define GPIO_PIN2_SOURCE BIT0
#define GPIO_PIN2_SOURCE_S 0
#define GPIO_PIN3_ADDRESS 0x34
#define GPIO_PIN3_CONFIG 0x00000003
#define GPIO_PIN3_CONFIG_S 11
#define GPIO_PIN3_WAKEUP_ENABLE BIT10
#define GPIO_PIN3_WAKEUP_ENABLE_S 10
#define GPIO_PIN3_INT_TYPE 0x00000007
#define GPIO_PIN3_INT_TYPE_S 7
#define GPIO_PIN3_DRIVER BIT2
#define GPIO_PIN3_DRIVER_S 2
#define GPIO_PIN3_SOURCE BIT0
#define GPIO_PIN3_SOURCE_S 0
#define GPIO_PIN4_ADDRESS 0x38
#define GPIO_PIN4_CONFIG 0x00000003
#define GPIO_PIN4_CONFIG_S 11
#define GPIO_PIN4_WAKEUP_ENABLE BIT10
#define GPIO_PIN4_WAKEUP_ENABLE_S 10
#define GPIO_PIN4_INT_TYPE 0x00000007
#define GPIO_PIN4_INT_TYPE_S 7
#define GPIO_PIN4_DRIVER BIT2
#define GPIO_PIN4_DRIVER_S 2
#define GPIO_PIN4_SOURCE BIT0
#define GPIO_PIN4_SOURCE_S 0
#define GPIO_PIN5_ADDRESS 0x3c
#define GPIO_PIN5_CONFIG 0x00000003
#define GPIO_PIN5_CONFIG_S 11
#define GPIO_PIN5_WAKEUP_ENABLE BIT10
#define GPIO_PIN5_WAKEUP_ENABLE_S 10
#define GPIO_PIN5_INT_TYPE 0x00000007
#define GPIO_PIN5_INT_TYPE_S 7
#define GPIO_PIN5_DRIVER BIT2
#define GPIO_PIN5_DRIVER_S 2
#define GPIO_PIN5_SOURCE BIT0
#define GPIO_PIN5_SOURCE_S 0
#define GPIO_PIN6_ADDRESS 0x40
#define GPIO_PIN6_CONFIG 0x00000003
#define GPIO_PIN6_CONFIG_S 11
#define GPIO_PIN6_WAKEUP_ENABLE BIT10
#define GPIO_PIN6_WAKEUP_ENABLE_S 10
#define GPIO_PIN6_INT_TYPE 0x00000007
#define GPIO_PIN6_INT_TYPE_S 7
#define GPIO_PIN6_DRIVER BIT2
#define GPIO_PIN6_DRIVER_S 2
#define GPIO_PIN6_SOURCE BIT0
#define GPIO_PIN6_SOURCE_S 0
#define GPIO_PIN7_ADDRESS 0x44
#define GPIO_PIN7_CONFIG 0x00000003
#define GPIO_PIN7_CONFIG_S 11
#define GPIO_PIN7_WAKEUP_ENABLE BIT10
#define GPIO_PIN7_WAKEUP_ENABLE_S 10
#define GPIO_PIN7_INT_TYPE 0x00000007
#define GPIO_PIN7_INT_TYPE_S 7
#define GPIO_PIN7_DRIVER BIT2
#define GPIO_PIN7_DRIVER_S 2
#define GPIO_PIN7_SOURCE BIT0
#define GPIO_PIN7_SOURCE_S 0
#define GPIO_PIN8_ADDRESS 0x48
#define GPIO_PIN8_CONFIG 0x00000003
#define GPIO_PIN8_CONFIG_S 11
#define GPIO_PIN8_WAKEUP_ENABLE BIT10
#define GPIO_PIN8_WAKEUP_ENABLE_S 10
#define GPIO_PIN8_INT_TYPE 0x00000007
#define GPIO_PIN8_INT_TYPE_S 7
#define GPIO_PIN8_DRIVER BIT2
#define GPIO_PIN8_DRIVER_S 2
#define GPIO_PIN8_SOURCE BIT0
#define GPIO_PIN8_SOURCE_S 0
#define GPIO_PIN9_ADDRESS 0x4c
#define GPIO_PIN9_CONFIG 0x00000003
#define GPIO_PIN9_CONFIG_S 11
#define GPIO_PIN9_WAKEUP_ENABLE BIT10
#define GPIO_PIN9_WAKEUP_ENABLE_S 10
#define GPIO_PIN9_INT_TYPE 0x00000007
#define GPIO_PIN9_INT_TYPE_S 7
#define GPIO_PIN9_DRIVER BIT2
#define GPIO_PIN9_DRIVER_S 2
#define GPIO_PIN9_SOURCE BIT0
#define GPIO_PIN9_SOURCE_S 0
#define GPIO_PIN10_ADDRESS 0x50
#define GPIO_PIN10_CONFIG 0x00000003
#define GPIO_PIN10_CONFIG_S 11
#define GPIO_PIN10_WAKEUP_ENABLE BIT10
#define GPIO_PIN10_WAKEUP_ENABLE_S 10
#define GPIO_PIN10_INT_TYPE 0x00000007
#define GPIO_PIN10_INT_TYPE_S 7
#define GPIO_PIN10_DRIVER BIT2
#define GPIO_PIN10_DRIVER_S 2
#define GPIO_PIN10_SOURCE BIT0
#define GPIO_PIN10_SOURCE_S 0
#define GPIO_PIN11_ADDRESS 0x54
#define GPIO_PIN11_CONFIG 0x00000003
#define GPIO_PIN11_CONFIG_S 11
#define GPIO_PIN11_WAKEUP_ENABLE BIT10
#define GPIO_PIN11_WAKEUP_ENABLE_S 10
#define GPIO_PIN11_INT_TYPE 0x00000007
#define GPIO_PIN11_INT_TYPE_S 7
#define GPIO_PIN11_DRIVER BIT2
#define GPIO_PIN11_DRIVER_S 2
#define GPIO_PIN11_SOURCE BIT0
#define GPIO_PIN11_SOURCE_S 0
#define GPIO_PIN12_ADDRESS 0x58
#define GPIO_PIN12_CONFIG 0x00000003
#define GPIO_PIN12_CONFIG_S 11
#define GPIO_PIN12_WAKEUP_ENABLE BIT10
#define GPIO_PIN12_WAKEUP_ENABLE_S 10
#define GPIO_PIN12_INT_TYPE 0x00000007
#define GPIO_PIN12_INT_TYPE_S 7
#define GPIO_PIN12_DRIVER BIT2
#define GPIO_PIN12_DRIVER_S 2
#define GPIO_PIN12_SOURCE BIT0
#define GPIO_PIN12_SOURCE_S 0
#define GPIO_PIN13_ADDRESS 0x5c
#define GPIO_PIN13_CONFIG 0x00000003
#define GPIO_PIN13_CONFIG_S 11
#define GPIO_PIN13_WAKEUP_ENABLE BIT10
#define GPIO_PIN13_WAKEUP_ENABLE_S 10
#define GPIO_PIN13_INT_TYPE 0x00000007
#define GPIO_PIN13_INT_TYPE_S 7
#define GPIO_PIN13_DRIVER BIT2
#define GPIO_PIN13_DRIVER_S 2
#define GPIO_PIN13_SOURCE BIT0
#define GPIO_PIN13_SOURCE_S 0
#define GPIO_PIN14_ADDRESS 0x60
#define GPIO_PIN14_CONFIG 0x00000003
#define GPIO_PIN14_CONFIG_S 11
#define GPIO_PIN14_WAKEUP_ENABLE BIT10
#define GPIO_PIN14_WAKEUP_ENABLE_S 10
#define GPIO_PIN14_INT_TYPE 0x00000007
#define GPIO_PIN14_INT_TYPE_S 7
#define GPIO_PIN14_DRIVER BIT2
#define GPIO_PIN14_DRIVER_S 2
#define GPIO_PIN14_SOURCE BIT0
#define GPIO_PIN14_SOURCE_S 0
#define GPIO_PIN15_ADDRESS 0x64
#define GPIO_PIN15_CONFIG 0x00000003
#define GPIO_PIN15_CONFIG_S 11
#define GPIO_PIN15_WAKEUP_ENABLE BIT10
#define GPIO_PIN15_WAKEUP_ENABLE_S 10
#define GPIO_PIN15_INT_TYPE 0x00000007
#define GPIO_PIN15_INT_TYPE_S 7
#define GPIO_PIN15_DRIVER BIT2
#define GPIO_PIN15_DRIVER_S 2
#define GPIO_PIN15_SOURCE BIT0
#define GPIO_PIN15_SOURCE_S 0
#define GPIO_SIGMA_DELTA_ADDRESS 0x68
#define SIGMA_DELTA_ENABLE BIT16
#define SIGMA_DELTA_ENABLE_S 16
#define SIGMA_DELTA_PRESCALAR 0x000000ff
#define SIGMA_DELTA_PRESCALAR_S 8
#define SIGMA_DELTA_TARGET 0x000000ff
#define SIGMA_DELTA_TARGET_S 0
#define GPIO_RTC_CALIB_SYNC_ADDRESS 0x6c
#define RTC_CALIB_START BIT31
#define RTC_CALIB_START_S 31
#define RTC_PERIOD_NUM 0x000003ff
#define RTC_PERIOD_NUM_S 0
#define GPIO_RTC_CALIB_VALUE_ADDRESS 0x70
#define RTC_CALIB_RDY BIT31
#define RTC_CALIB_RDY_S 31
#define RTC_CALIB_RDY_REAL BIT30
#define RTC_CALIB_RDY_REAL_S 30
#define RTC_CALIB_VALUE 0x000fffff
#define RTC_CALIB_VALUE_S 0
#define GPIO_REG_READ(reg) READ_PERI_REG(PERIPHS_GPIO_BASEADDR + reg)
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(PERIPHS_GPIO_BASEADDR + reg, val)
#endif

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/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
#include "eagle_soc.h"
#define PERIPHS_IO_MUX 0x60000800
#define PERIPHS_IO_MUX_FUNC 0x13
#define PERIPHS_IO_MUX_FUNC_S 4
#define PERIPHS_IO_MUX_PULLUP BIT7
#define PERIPHS_IO_MUX_PULLDWN BIT6
#define PERIPHS_IO_MUX_SLEEP_PULLUP BIT3
#define PERIPHS_IO_MUX_SLEEP_PULLDWN BIT2
#define PERIPHS_IO_MUX_SLEEP_OE BIT1
#define PERIPHS_IO_MUX_OE BIT0
#define PERIPHS_IO_MUX_CONF_U (PERIPHS_IO_MUX + 0x00)
#define SPI0_CLK_EQU_SYS_CLK BIT8
#define SPI1_CLK_EQU_SYS_CLK BIT9
#define PERIPHS_IO_MUX_MTDI_U (PERIPHS_IO_MUX + 0x04)
#define FUNC_MTDI 0
#define FUNC_I2SI_DATA 1
#define FUNC_HSPIQ_MISO 2
#define FUNC_GPIO12 3
#define FUNC_UART0_DTR 4
#define PERIPHS_IO_MUX_MTCK_U (PERIPHS_IO_MUX + 0x08)
#define FUNC_MTCK 0
#define FUNC_I2SI_BCK 1
#define FUNC_HSPID_MOSI 2
#define FUNC_GPIO13 3
#define FUNC_UART0_CTS 4
#define PERIPHS_IO_MUX_MTMS_U (PERIPHS_IO_MUX + 0x0C)
#define FUNC_MTMS 0
#define FUNC_I2SI_WS 1
#define FUNC_HSPI_CLK 2
#define FUNC_GPIO14 3
#define FUNC_UART0_DSR 4
#define PERIPHS_IO_MUX_MTDO_U (PERIPHS_IO_MUX + 0x10)
#define FUNC_MTDO 0
#define FUNC_I2SO_BCK 1
#define FUNC_HSPI_CS0 2
#define FUNC_GPIO15 3
#define FUNC_U0RTS 4
#define FUNC_UART0_RTS 4
#define PERIPHS_IO_MUX_U0RXD_U (PERIPHS_IO_MUX + 0x14)
#define FUNC_U0RXD 0
#define FUNC_I2SO_DATA 1
#define FUNC_GPIO3 3
#define FUNC_CLK_XTAL_BK 4
#define PERIPHS_IO_MUX_U0TXD_U (PERIPHS_IO_MUX + 0x18)
#define FUNC_U0TXD 0
#define FUNC_SPICS1 1
#define FUNC_GPIO1 3
#define FUNC_CLK_RTC_BK 4
#define PERIPHS_IO_MUX_SD_CLK_U (PERIPHS_IO_MUX + 0x1c)
#define FUNC_SDCLK 0
#define FUNC_SPICLK 1
#define FUNC_GPIO6 3
#define UART1_CTS 4
#define PERIPHS_IO_MUX_SD_DATA0_U (PERIPHS_IO_MUX + 0x20)
#define FUNC_SDDATA0 0
#define FUNC_SPIQ_MISO 1
#define FUNC_GPIO7 3
#define FUNC_U1TXD 4
#define FUNC_UART1_TXD 4
#define PERIPHS_IO_MUX_SD_DATA1_U (PERIPHS_IO_MUX + 0x24)
#define FUNC_SDDATA1 0
#define FUNC_SPID_MOSI 1
#define FUNC_GPIO8 3
#define FUNC_U1RXD 4
#define FUNC_UART1_RXD 4
#define PERIPHS_IO_MUX_SD_DATA2_U (PERIPHS_IO_MUX + 0x28)
#define FUNC_SDDATA2 0
#define FUNC_SPIHD 1
#define FUNC_GPIO9 3
#define UFNC_HSPIHD 4
#define PERIPHS_IO_MUX_SD_DATA3_U (PERIPHS_IO_MUX + 0x2c)
#define FUNC_SDDATA3 0
#define FUNC_SPIWP 1
#define FUNC_GPIO10 3
#define FUNC_HSPIWP 4
#define PERIPHS_IO_MUX_SD_CMD_U (PERIPHS_IO_MUX + 0x30)
#define FUNC_SDCMD 0
#define FUNC_SPICS0 1
#define FUNC_GPIO11 3
#define U1RTS 4
#define UART1_RTS 4
#define PERIPHS_IO_MUX_GPIO0_U (PERIPHS_IO_MUX + 0x34)
#define FUNC_GPIO0 0
#define FUNC_SPICS2 1
#define FUNC_CLK_OUT 4
#define PERIPHS_IO_MUX_GPIO2_U (PERIPHS_IO_MUX + 0x38)
#define FUNC_GPIO2 0
#define FUNC_I2SO_WS 1
#define FUNC_U1TXD_BK 2
#define FUNC_UART1_TXD_BK 2
#define FUNC_U0TXD_BK 4
#define FUNC_UART0_TXD_BK 4
#define PERIPHS_IO_MUX_GPIO4_U (PERIPHS_IO_MUX + 0x3C)
#define FUNC_GPIO4 0
#define FUNC_CLK_XTAL 1
#define PERIPHS_IO_MUX_GPIO5_U (PERIPHS_IO_MUX + 0x40)
#define FUNC_GPIO5 0
#define FUNC_CLK_RTC 1
#define PIN_PULLUP_DIS(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP)
#define PIN_PULLUP_EN(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) do { \
CLEAR_PERI_REG_MASK(PIN_NAME, (PERIPHS_IO_MUX_FUNC << PERIPHS_IO_MUX_FUNC_S)); \
SET_PERI_REG_MASK(PIN_NAME, (((FUNC & BIT2) << 2) | (FUNC & 0x3)) << PERIPHS_IO_MUX_FUNC_S); \
} while (0)
#endif //_PIN_MUX_H_

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/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SPI_REGISTER_H_INCLUDED
#define SPI_REGISTER_H_INCLUDED
#define REG_SPI_BASE(i) (0x60000200 - i*0x100)
#define SPI_CMD(i) (REG_SPI_BASE(i) + 0x0)
#define SPI_USR (BIT(18))
#define SPI_ADDR(i) (REG_SPI_BASE(i) + 0x4)
#define SPI_CTRL(i) (REG_SPI_BASE(i) + 0x8)
#define SPI_WR_BIT_ORDER (BIT(26))
#define SPI_RD_BIT_ORDER (BIT(25))
#define SPI_QIO_MODE (BIT(24))
#define SPI_DIO_MODE (BIT(23))
#define SPI_QOUT_MODE (BIT(20))
#define SPI_DOUT_MODE (BIT(14))
#define SPI_FASTRD_MODE (BIT(13))
#define SPI_RD_STATUS(i) (REG_SPI_BASE(i) + 0x10)
#define SPI_CTRL2(i) (REG_SPI_BASE(i) + 0x14)
#define SPI_CS_DELAY_NUM 0x0000000F
#define SPI_CS_DELAY_NUM_S 28
#define SPI_CS_DELAY_MODE 0x00000003
#define SPI_CS_DELAY_MODE_S 26
#define SPI_MOSI_DELAY_NUM 0x00000007
#define SPI_MOSI_DELAY_NUM_S 23
#define SPI_MOSI_DELAY_MODE 0x00000003
#define SPI_MOSI_DELAY_MODE_S 21
#define SPI_MISO_DELAY_NUM 0x00000007
#define SPI_MISO_DELAY_NUM_S 18
#define SPI_MISO_DELAY_MODE 0x00000003
#define SPI_MISO_DELAY_MODE_S 16
#define SPI_CLOCK(i) (REG_SPI_BASE(i) + 0x18)
#define SPI_CLK_EQU_SYSCLK (BIT(31))
#define SPI_CLKDIV_PRE 0x00001FFF
#define SPI_CLKDIV_PRE_S 18
#define SPI_CLKCNT_N 0x0000003F
#define SPI_CLKCNT_N_S 12
#define SPI_CLKCNT_H 0x0000003F
#define SPI_CLKCNT_H_S 6
#define SPI_CLKCNT_L 0x0000003F
#define SPI_CLKCNT_L_S 0
#define SPI_USER(i) (REG_SPI_BASE(i) + 0x1C)
#define SPI_USR_COMMAND (BIT(31))
#define SPI_USR_ADDR (BIT(30))
#define SPI_USR_DUMMY (BIT(29))
#define SPI_USR_MISO (BIT(28))
#define SPI_USR_MOSI (BIT(27))
#define SPI_USR_MOSI_HIGHPART (BIT(25))
#define SPI_USR_MISO_HIGHPART (BIT(24))
#define SPI_SIO (BIT(16))
#define SPI_FWRITE_QIO (BIT(15))
#define SPI_FWRITE_DIO (BIT(14))
#define SPI_FWRITE_QUAD (BIT(13))
#define SPI_FWRITE_DUAL (BIT(12))
#define SPI_WR_BYTE_ORDER (BIT(11))
#define SPI_RD_BYTE_ORDER (BIT(10))
#define SPI_CK_OUT_EDGE (BIT(7))
#define SPI_CK_I_EDGE (BIT(6))
#define SPI_CS_SETUP (BIT(5))
#define SPI_CS_HOLD (BIT(4))
#define SPI_FLASH_MODE (BIT(2))
#define SPI_USER1(i) (REG_SPI_BASE(i) + 0x20)
#define SPI_USR_ADDR_BITLEN 0x0000003F
#define SPI_USR_ADDR_BITLEN_S 26
#define SPI_USR_MOSI_BITLEN 0x000001FF
#define SPI_USR_MOSI_BITLEN_S 17
#define SPI_USR_MISO_BITLEN 0x000001FF
#define SPI_USR_MISO_BITLEN_S 8
#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
#define SPI_USR_DUMMY_CYCLELEN_S 0
#define SPI_USER2(i) (REG_SPI_BASE(i) + 0x24)
#define SPI_USR_COMMAND_BITLEN 0x0000000F
#define SPI_USR_COMMAND_BITLEN_S 28
#define SPI_USR_COMMAND_VALUE 0x0000FFFF
#define SPI_USR_COMMAND_VALUE_S 0
#define SPI_WR_STATUS(i) (REG_SPI_BASE(i) + 0x28)
#define SPI_PIN(i) (REG_SPI_BASE(i) + 0x2C)
#define SPI_CS2_DIS (BIT(2))
#define SPI_CS1_DIS (BIT(1))
#define SPI_CS0_DIS (BIT(0))
#define SPI_SLAVE(i) (REG_SPI_BASE(i) + 0x30)
#define SPI_SYNC_RESET (BIT(31))
#define SPI_SLAVE_MODE (BIT(30))
#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
#define SPI_SLV_WR_RD_STA_EN (BIT(28))
#define SPI_SLV_CMD_DEFINE (BIT(27))
#define SPI_TRANS_CNT 0x0000000F
#define SPI_TRANS_CNT_S 23
#define SPI_TRANS_DONE_EN (BIT(9))
#define SPI_SLV_WR_STA_DONE_EN (BIT(8))
#define SPI_SLV_RD_STA_DONE_EN (BIT(7))
#define SPI_SLV_WR_BUF_DONE_EN (BIT(6))
#define SPI_SLV_RD_BUF_DONE_EN (BIT(5))
#define SLV_SPI_INT_EN 0x0000001f
#define SLV_SPI_INT_EN_S 5
#define SPI_TRANS_DONE (BIT(4))
#define SPI_SLV_WR_STA_DONE (BIT(3))
#define SPI_SLV_RD_STA_DONE (BIT(2))
#define SPI_SLV_WR_BUF_DONE (BIT(1))
#define SPI_SLV_RD_BUF_DONE (BIT(0))
#define SPI_SLAVE1(i) (REG_SPI_BASE(i) + 0x34)
#define SPI_SLV_STATUS_BITLEN 0x0000001F
#define SPI_SLV_STATUS_BITLEN_S 27
#define SPI_SLV_BUF_BITLEN 0x000001FF
#define SPI_SLV_BUF_BITLEN_S 16
#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
#define SPI_SLV_RD_ADDR_BITLEN_S 10
#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
#define SPI_SLV_WR_ADDR_BITLEN_S 4
#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
#define SPI_SLAVE2(i) (REG_SPI_BASE(i) + 0x38)
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
#define SPI_SLV_WRSTR_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_WRSTR_DUMMY_CYCLELEN_S 8
#define SPI_SLV_RDSTR_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_RDSTR_DUMMY_CYCLELEN_S 0
#define SPI_SLAVE3(i) (REG_SPI_BASE(i) + 0x3C)
#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
#define SPI_SLV_WRSTA_CMD_VALUE_S 24
#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
#define SPI_SLV_RDSTA_CMD_VALUE_S 16
#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
#define SPI_SLV_WRBUF_CMD_VALUE_S 8
#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
#define SPI_SLV_RDBUF_CMD_VALUE_S 0
#define SPI_W0(i) (REG_SPI_BASE(i) + 0x40)
#define SPI_W1(i) (REG_SPI_BASE(i) + 0x44)
#define SPI_W2(i) (REG_SPI_BASE(i) + 0x48)
#define SPI_W3(i) (REG_SPI_BASE(i) + 0x4C)
#define SPI_W4(i) (REG_SPI_BASE(i) + 0x50)
#define SPI_W5(i) (REG_SPI_BASE(i) + 0x54)
#define SPI_W6(i) (REG_SPI_BASE(i) + 0x58)
#define SPI_W7(i) (REG_SPI_BASE(i) + 0x5C)
#define SPI_W8(i) (REG_SPI_BASE(i) + 0x60)
#define SPI_W9(i) (REG_SPI_BASE(i) + 0x64)
#define SPI_W10(i) (REG_SPI_BASE(i) + 0x68)
#define SPI_W11(i) (REG_SPI_BASE(i) + 0x6C)
#define SPI_W12(i) (REG_SPI_BASE(i) + 0x70)
#define SPI_W13(i) (REG_SPI_BASE(i) + 0x74)
#define SPI_W14(i) (REG_SPI_BASE(i) + 0x78)
#define SPI_W15(i) (REG_SPI_BASE(i) + 0x7C)
#define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
#define SPI_INT_HOLD_ENA 0x00000003
#define SPI_INT_HOLD_ENA_S 0
#endif // SPI_REGISTER_H_INCLUDED

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/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _TIMER_REGISTER_H_
#define _TIMER_REGISTER_H_
#define PERIPHS_TIMER_BASEDDR 0x60000600
#define FRC1_LOAD_ADDRESS (PERIPHS_TIMER_BASEDDR + 0x0)
#define TIMER_FRC1_LOAD_VALUE 0x007FFFFF
#define TIMER_FRC1_LOAD_VALUE_S 0
#define FRC1_LOAD_DATA_MSB 22
#define FRC1_LOAD_DATA_LSB 0
#define FRC1_LOAD_DATA_MASK 0x007fffff
#define FRC1_COUNT_ADDRESS (PERIPHS_TIMER_BASEDDR + 0x4)
#define TIMER_FRC1_COUNT 0x007FFFFF
#define TIMER_FRC1_COUNT_S 0
#define FRC1_COUNT_DATA_MSB 22
#define FRC1_COUNT_DATA_LSB 0
#define FRC1_COUNT_DATA_MASK 0x007fffff
#define FRC1_CTRL_ADDRESS (PERIPHS_TIMER_BASEDDR + 0x8)
#define TIMER_FRC1_INT (BIT(8))
#define TIMER_FRC1_CTRL 0x000000FF
#define TIMER_FRC1_CTRL_S 0
#define FRC1_CTRL_DATA_MSB 7
#define FRC1_CTRL_DATA_LSB 0
#define FRC1_CTRL_DATA_MASK 0x000000ff
#define FRC1_INT_ADDRESS (PERIPHS_TIMER_BASEDDR + 0xC)
#define TIMER_FRC1_INT_CLR_MASK (BIT(0))
#define FRC1_INT_CLR_MSB 0
#define FRC1_INT_CLR_LSB 0
#define FRC1_INT_CLR_MASK 0x00000001
#define FRC2_LOAD_ADDRESS (PERIPHS_TIMER_BASEDDR + 0x20)
#define TIMER_FRC2_LOAD_VALUE 0xFFFFFFFF
#define TIMER_FRC2_LOAD_VALUE_S 0
#define FRC2_LOAD_DATA_MSB 31
#define FRC2_LOAD_DATA_LSB 0
#define FRC2_LOAD_DATA_MASK 0xffffffff
#define FRC2_COUNT_ADDRESS (PERIPHS_TIMER_BASEDDR + 0x24)
#define TIMER_FRC2_COUNT 0xFFFFFFFF
#define TIMER_FRC2_COUNT_S 0
#define FRC2_COUNT_DATA_MSB 31
#define FRC2_COUNT_DATA_LSB 0
#define FRC2_COUNT_DATA_MASK 0xffffffff
#define FRC2_CTRL_ADDRESS (PERIPHS_TIMER_BASEDDR + 0x28)
#define TIMER_FRC2_INT (BIT(8))
#define TIMER_FRC2_CTRL 0x000000FF
#define TIMER_FRC2_CTRL_S 0
#define FRC2_CTRL_DATA_MSB 7
#define FRC2_CTRL_DATA_LSB 0
#define FRC2_CTRL_DATA_MASK 0x000000ff
#define FRC2_INT_ADDRESS (PERIPHS_TIMER_BASEDDR + 0x2C)
#define TIMER_FRC2_INT_CLR_MASK (BIT(0))
#define FRC2_INT_CLR_MSB 0
#define FRC2_INT_CLR_LSB 0
#define FRC2_INT_CLR_MASK 0x00000001
#define FRC2_ALARM_ADDRESS (PERIPHS_TIMER_BASEDDR + 0x30)
#define TIMER_FRC2_ALARM 0xFFFFFFFF
#define TIMER_FRC2_ALARM_S 0
#define FRC2_ALARM_DATA_MSB 31
#define FRC2_ALARM_DATA_LSB 0
#define FRC2_ALARM_DATA_MASK 0xffffffff
#endif

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/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef UART_REGISTER_H_
#define UART_REGISTER_H_
#define REG_UART_BASE(i) (0x60000000 + (i)*0xf00)
//version value:32'h062000
#define UART_FIFO(i) (REG_UART_BASE(i) + 0x0)
#define UART_RXFIFO_RD_BYTE 0x000000FF
#define UART_RXFIFO_RD_BYTE_S 0
#define UART_INT_RAW(i) (REG_UART_BASE(i) + 0x4)
#define UART_RXFIFO_TOUT_INT_RAW (BIT(8))
#define UART_BRK_DET_INT_RAW (BIT(7))
#define UART_CTS_CHG_INT_RAW (BIT(6))
#define UART_DSR_CHG_INT_RAW (BIT(5))
#define UART_RXFIFO_OVF_INT_RAW (BIT(4))
#define UART_FRM_ERR_INT_RAW (BIT(3))
#define UART_PARITY_ERR_INT_RAW (BIT(2))
#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1))
#define UART_RXFIFO_FULL_INT_RAW (BIT(0))
#define UART_INT_ST(i) (REG_UART_BASE(i) + 0x8)
#define UART_RXFIFO_TOUT_INT_ST (BIT(8))
#define UART_BRK_DET_INT_ST (BIT(7))
#define UART_CTS_CHG_INT_ST (BIT(6))
#define UART_DSR_CHG_INT_ST (BIT(5))
#define UART_RXFIFO_OVF_INT_ST (BIT(4))
#define UART_FRM_ERR_INT_ST (BIT(3))
#define UART_PARITY_ERR_INT_ST (BIT(2))
#define UART_TXFIFO_EMPTY_INT_ST (BIT(1))
#define UART_RXFIFO_FULL_INT_ST (BIT(0))
#define UART_INT_ENA(i) (REG_UART_BASE(i) + 0xC)
#define UART_RXFIFO_TOUT_INT_ENA (BIT(8))
#define UART_BRK_DET_INT_ENA (BIT(7))
#define UART_CTS_CHG_INT_ENA (BIT(6))
#define UART_DSR_CHG_INT_ENA (BIT(5))
#define UART_RXFIFO_OVF_INT_ENA (BIT(4))
#define UART_FRM_ERR_INT_ENA (BIT(3))
#define UART_PARITY_ERR_INT_ENA (BIT(2))
#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1))
#define UART_RXFIFO_FULL_INT_ENA (BIT(0))
#define UART_INT_CLR(i) (REG_UART_BASE(i) + 0x10)
#define UART_RXFIFO_TOUT_INT_CLR (BIT(8))
#define UART_BRK_DET_INT_CLR (BIT(7))
#define UART_CTS_CHG_INT_CLR (BIT(6))
#define UART_DSR_CHG_INT_CLR (BIT(5))
#define UART_RXFIFO_OVF_INT_CLR (BIT(4))
#define UART_FRM_ERR_INT_CLR (BIT(3))
#define UART_PARITY_ERR_INT_CLR (BIT(2))
#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1))
#define UART_RXFIFO_FULL_INT_CLR (BIT(0))
#define UART_CLKDIV(i) (REG_UART_BASE(i) + 0x14)
#define UART_CLKDIV_CNT 0x000FFFFF
#define UART_CLKDIV_S 0
#define UART_AUTOBAUD(i) (REG_UART_BASE(i) + 0x18)
#define UART_GLITCH_FILT 0x000000FF
#define UART_GLITCH_FILT_S 8
#define UART_AUTOBAUD_EN (BIT(0))
#define UART_STATUS(i) (REG_UART_BASE(i) + 0x1C)
#define UART_TXD (BIT(31))
#define UART_RTSN (BIT(30))
#define UART_DTRN (BIT(29))
#define UART_TXFIFO_CNT 0x000000FF
#define UART_TXFIFO_CNT_S 16
#define UART_RXD (BIT(15))
#define UART_CTSN (BIT(14))
#define UART_DSRN (BIT(13))
#define UART_RXFIFO_CNT 0x000000FF
#define UART_RXFIFO_CNT_S 0
#define UART_CONF0(i) (REG_UART_BASE(i) + 0x20)
#define UART_DTR_INV (BIT(24))
#define UART_RTS_INV (BIT(23))
#define UART_TXD_INV (BIT(22))
#define UART_DSR_INV (BIT(21))
#define UART_CTS_INV (BIT(20))
#define UART_RXD_INV (BIT(19))
#define UART_TXFIFO_RST (BIT(18))
#define UART_RXFIFO_RST (BIT(17))
#define UART_IRDA_EN (BIT(16))
#define UART_TX_FLOW_EN (BIT(15))
#define UART_LOOPBACK (BIT(14))
#define UART_IRDA_RX_INV (BIT(13))
#define UART_IRDA_TX_INV (BIT(12))
#define UART_IRDA_WCTL (BIT(11))
#define UART_IRDA_TX_EN (BIT(10))
#define UART_IRDA_DPLX (BIT(9))
#define UART_TXD_BRK (BIT(8))
#define UART_SW_DTR (BIT(7))
#define UART_SW_RTS (BIT(6))
#define UART_STOP_BIT_NUM 0x00000003
#define UART_STOP_BIT_NUM_S 4
#define UART_BIT_NUM 0x00000003
#define UART_BIT_NUM_S 2
#define UART_PARITY_EN (BIT(1))
#define UART_PARITY (BIT(0))
#define UART_CONF1(i) (REG_UART_BASE(i) + 0x24)
#define UART_RX_TOUT_EN (BIT(31))
#define UART_RX_TOUT_THRHD 0x0000007F
#define UART_RX_TOUT_THRHD_S 24
#define UART_RX_FLOW_EN (BIT(23))
#define UART_RX_FLOW_THRHD 0x0000007F
#define UART_RX_FLOW_THRHD_S 16
#define UART_TXFIFO_EMPTY_THRHD 0x0000007F
#define UART_TXFIFO_EMPTY_THRHD_S 8
#define UART_RXFIFO_FULL_THRHD 0x0000007F
#define UART_RXFIFO_FULL_THRHD_S 0
#define UART_LOWPULSE(i) (REG_UART_BASE(i) + 0x28)
#define UART_LOWPULSE_MIN_CNT 0x000FFFFF
#define UART_LOWPULSE_MIN_CNT_S 0
#define UART_HIGHPULSE(i) (REG_UART_BASE(i) + 0x2C)
#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF
#define UART_HIGHPULSE_MIN_CNT_S 0
#define UART_PULSE_NUM(i) (REG_UART_BASE(i) + 0x30)
#define UART_PULSE_NUM_CNT 0x0003FF
#define UART_PULSE_NUM_CNT_S 0
#define UART_DATE(i) (REG_UART_BASE(i) + 0x78)
#define UART_ID(i) (REG_UART_BASE(i) + 0x7C)
#endif // UART_REGISTER_H_INCLUDED