espressif/ESP8266_RTOS_SDK
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1. driver:
  1). Fix hw_timer issue, #96;
  2). Fix SPI output data error;
  3). Fix SPI read data bug;
  4). Fix driver lib compile issue;
  5). Fix uart flow control issue;

2. lwip:
  1). Enable lwip ETHARP_TRUS_IP_MAC;
  2). Modify dhcp/dhcps timer from 60 seconds to 1 second;

3. WiFi:
  1). Support CSA;
This commit is contained in:
Espressif Systems
2017-05-27 11:13:46 +08:00
parent fdd3346291
commit e1e17a12c3
18 changed files with 102 additions and 31 deletions
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16
driver_lib/driver/spi_interface.c
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@ -22,6 +22,7 @@
#include "spi_interface.h"
#include "esp8266/eagle_soc.h"
#include "esp8266/ets_sys.h"
#include "esp8266/pin_mux_register.h"
#include "esp_libc.h"
//*****************************************************************************
//
@ -123,6 +124,10 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
// SPI Speed
if (1 < (pAttr->speed)) {
CLEAR_PERI_REG_MASK(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK);
if (spiNum == SpiNum_HSPI) {
CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI1_CLK_EQU_SYS_CLK);
}
WRITE_PERI_REG(SPI_CLOCK(spiNum),
((pAttr->speed & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) |
((((pAttr->speed + 1) / 2 - 1) & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) |
@ -169,6 +174,8 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
//clear Daul or Quad lines transmission mode
CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_QIO_MODE | SPI_DIO_MODE | SPI_DOUT_MODE | SPI_QOUT_MODE);
SET_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_FASTRD_MODE);
}
/**
@ -258,6 +265,7 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN, ((pInData->dataLen << 3) - 1), SPI_USR_MOSI_BITLEN_S);
} else {
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN,
0, SPI_USR_MOSI_BITLEN_S);
}
@ -329,9 +337,15 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MISO_BITLEN,
0, SPI_USR_MISO_BITLEN_S);
}
//CLEAR FIFO DATA
int fifo_idx = 0;
do {
WRITE_PERI_REG(SPI_W0(spiNum) + (fifo_idx << 2), 0);
} while (++fifo_idx < (pOutData->dataLen / 4));
// Start send data
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Read data out
do {