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feat(bootloader): Initialize SPI flash clock and I/O mode at bootloader

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This commit is contained in:
Dong Heng
2018-11-05 19:34:32 +08:00
parent 14d8307dc2
commit d5b14d7427
8 changed files with 108 additions and 108 deletions
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83
components/esp8266/source/chip_boot.c
View File

@ -13,86 +13,17 @@
// limitations under the License.
#include "sdkconfig.h"
#include "esp_attr.h"
#ifndef CONFIG_BOOTLOADER_INIT_SPI_FLASH
#include "spi_flash.h"
#include "esp_log.h"
#include "esp_system.h"
#include "esp8266/eagle_soc.h"
#include "esp8266/rom_functions.h"
#include "esp_image_format.h"
#define PERIPHS_SPI_FLASH_USRREG (0x60000200 + 0x1c)
#define PERIPHS_SPI_FLASH_CTRL (0x60000200 + 0x08)
#define PERIPHS_IO_MUX_CONF_U (0x60000800)
#define SPI0_CLK_EQU_SYSCLK BIT8
#define SPI_FLASH_CLK_EQU_SYSCLK BIT12
static const char *TAG = "chip_boot";
/*
* @brief initialize the chip including flash I/O and chip cache according to
* boot parameters which are stored at the flash
* @brief initialize the chip
*/
void chip_boot(size_t start_addr)
void chip_boot(void)
{
int ret;
uint32_t freqdiv, flash_size;
uint32_t freqbits;
esp_image_header_t fhdr;
extern void esp_spi_flash_init(uint32_t spi_speed, uint32_t spi_mode);
uint32_t flash_map_table[FALSH_SIZE_MAP_MAX] = {
1 * 1024 * 1024,
2 * 1024 * 1024,
4 * 1024 * 1024,
8 * 1024 * 1024,
16 * 1024 * 1024
};
uint32_t flash_map_table_size = sizeof(flash_map_table) / sizeof(flash_map_table[0]);
extern esp_spi_flash_chip_t flashchip;
extern void phy_get_bb_evm(void);
extern void cache_init(uint8_t);
extern void user_spi_flash_dio_to_qio_pre_init(void);
phy_get_bb_evm();
SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_USRREG, BIT5);
ret = spi_flash_read(start_addr, &fhdr, sizeof(esp_image_header_t));
if (ret) {
ESP_EARLY_LOGE(TAG, "SPI flash read result %d\n", ret);
}
if (3 > fhdr.spi_speed)
freqdiv = fhdr.spi_speed + 2;
else if (0x0F == fhdr.spi_speed)
freqdiv = 1;
else
freqdiv = 2;
if (fhdr.spi_size < flash_map_table_size) {
flash_size = flash_map_table[fhdr.spi_size];
ESP_EARLY_LOGD(TAG, "SPI flash size is %d\n", flash_size);
} else {
flash_size = 0;
ESP_EARLY_LOGE(TAG, "SPI size error is %d\n", fhdr.spi_size);
}
flashchip.chip_size = flash_size;
if (1 >= freqdiv) {
freqbits = SPI_FLASH_CLK_EQU_SYSCLK;
SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_FLASH_CLK_EQU_SYSCLK);
SET_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI0_CLK_EQU_SYSCLK);
} else {
freqbits = ((freqdiv - 1) << 8) + ((freqdiv / 2 - 1) << 4) + (freqdiv - 1);
CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_FLASH_CLK_EQU_SYSCLK);
CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI0_CLK_EQU_SYSCLK);
}
SET_PERI_REG_BITS(PERIPHS_SPI_FLASH_CTRL, 0xfff, freqbits, 0);
if (fhdr.spi_mode == ESP_IMAGE_SPI_MODE_QIO) {
ESP_EARLY_LOGD(TAG, "SPI flash enable QIO mode\n");
user_spi_flash_dio_to_qio_pre_init();
}
esp_spi_flash_init(CONFIG_SPI_FLASH_FREQ, CONFIG_SPI_FLASH_MODE);
}
#endif /* CONFIG_BOOTLOADER_INIT_SPI_FLASH */

9
components/esp8266/source/startup.c
View File

@ -33,7 +33,7 @@
#define FLASH_MAP_ADDR 0x40200000
#define FLASH_MAP_SIZE 0x00100000
extern void chip_boot(size_t start_addr);
extern void chip_boot(void);
extern int rtc_init(void);
extern int mac_init(void);
extern int base_gpio_init(void);
@ -41,6 +41,7 @@ extern int watchdog_init(void);
extern int wifi_timer_init(void);
extern int wifi_nvs_init(void);
extern esp_err_t esp_pthread_init(void);
extern void phy_get_bb_evm(void);
static void user_init_entry(void *param)
{
@ -55,6 +56,8 @@ static void user_init_entry(void *param)
for (func = &__init_array_start; func < &__init_array_end; func++)
func[0]();
phy_get_bb_evm();
assert(nvs_flash_init() == 0);
assert(wifi_nvs_init() == 0);
assert(rtc_init() == 0);
@ -108,7 +111,9 @@ void call_user_start(size_t start_addr)
"wsr a0, vecbase\n"
: : :"memory");
chip_boot(start_addr);
#ifndef CONFIG_BOOTLOADER_INIT_SPI_FLASH
chip_boot();
#endif
/* clear bss data */
for (p = &_bss_start; p < &_bss_end; p++)