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refactor(hspi): Refactor hspi driver for esp8266 idf
This commit is contained in:
XiongYu
@ -1,195 +1,268 @@
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/*
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* ESPRSSIF MIT License
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*
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* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
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*
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* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
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* it is free of charge, to any person obtaining a copy of this software and associated
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* documentation files (the "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
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* to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all copies or
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* substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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#ifndef SPI_REGISTER_H_INCLUDED
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#define SPI_REGISTER_H_INCLUDED
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "eagle_soc.h"
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#pragma once
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#define REG_SPI_BASE(i) (0x60000200 - i*0x100)
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#include "esp8266/eagle_soc.h"
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#define SPI_CMD(i) (REG_SPI_BASE(i) + 0x0)
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#define SPI_USR (BIT(18))
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SPI_ADDR(i) (REG_SPI_BASE(i) + 0x4)
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#define REG_SPI_BASE(i) (0x60000200-i*0x100)
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#define SPI_CMD(i) (REG_SPI_BASE(i) + 0x0)
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#define SPI_CTRL(i) (REG_SPI_BASE(i) + 0x8)
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#define SPI_WR_BIT_ORDER (BIT(26))
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#define SPI_RD_BIT_ORDER (BIT(25))
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#define SPI_QIO_MODE (BIT(24))
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#define SPI_DIO_MODE (BIT(23))
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#define SPI_QOUT_MODE (BIT(20))
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#define SPI_DOUT_MODE (BIT(14))
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#define SPI_FASTRD_MODE (BIT(13))
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#define SPI_FLASH_READ BIT31
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#define SPI_FLASH_WREN BIT30
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#define SPI_FLASH_WRDI BIT29
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#define SPI_FLASH_RDID BIT28
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#define SPI_FLASH_RDSR BIT27
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#define SPI_FLASH_WRSR BIT26
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#define SPI_FLASH_PP BIT25
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#define SPI_FLASH_SE BIT24
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#define SPI_FLASH_BE BIT23
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#define SPI_FLASH_CE BIT22
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#define SPI_FLASH_RES BIT20
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#define SPI_RD_STATUS(i) (REG_SPI_BASE(i) + 0x10)
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#define SPI_USR (BIT(18))
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#define SPI_CTRL2(i) (REG_SPI_BASE(i) + 0x14)
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#define SPI_CS_DELAY_NUM 0x0000000F
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#define SPI_CS_DELAY_NUM_S 28
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#define SPI_CS_DELAY_MODE 0x00000003
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#define SPI_CS_DELAY_MODE_S 26
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#define SPI_MOSI_DELAY_NUM 0x00000007
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#define SPI_MOSI_DELAY_NUM_S 23
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#define SPI_MOSI_DELAY_MODE 0x00000003
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#define SPI_MOSI_DELAY_MODE_S 21
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#define SPI_MISO_DELAY_NUM 0x00000007
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#define SPI_MISO_DELAY_NUM_S 18
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#define SPI_MISO_DELAY_MODE 0x00000003
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#define SPI_MISO_DELAY_MODE_S 16
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#define SPI_ADDR(i) (REG_SPI_BASE(i) + 0x4)
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#define SPI_CLOCK(i) (REG_SPI_BASE(i) + 0x18)
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#define SPI_CLK_EQU_SYSCLK (BIT(31))
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#define SPI_CLKDIV_PRE 0x00001FFF
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#define SPI_CLKDIV_PRE_S 18
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#define SPI_CLKCNT_N 0x0000003F
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#define SPI_CLKCNT_N_S 12
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#define SPI_CLKCNT_H 0x0000003F
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#define SPI_CLKCNT_H_S 6
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#define SPI_CLKCNT_L 0x0000003F
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#define SPI_CLKCNT_L_S 0
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#define SPI_CTRL(i) (REG_SPI_BASE(i) + 0x8)
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#define SPI_WR_BIT_ORDER (BIT(26))
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#define SPI_RD_BIT_ORDER (BIT(25))
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#define SPI_QIO_MODE (BIT(24))
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#define SPI_DIO_MODE (BIT(23))
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#define SPI_QOUT_MODE (BIT(20))
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#define SPI_DOUT_MODE (BIT(14))
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#define SPI_FASTRD_MODE (BIT(13))
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#define SPI_USER(i) (REG_SPI_BASE(i) + 0x1C)
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#define SPI_USR_COMMAND (BIT(31))
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#define SPI_USR_ADDR (BIT(30))
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#define SPI_USR_DUMMY (BIT(29))
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#define SPI_USR_MISO (BIT(28))
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#define SPI_USR_MOSI (BIT(27))
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#define SPI_USR_MOSI_HIGHPART (BIT(25))
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#define SPI_USR_MISO_HIGHPART (BIT(24))
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#define SPI_SIO (BIT(16))
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#define SPI_FWRITE_QIO (BIT(15))
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#define SPI_FWRITE_DIO (BIT(14))
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#define SPI_FWRITE_QUAD (BIT(13))
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#define SPI_FWRITE_DUAL (BIT(12))
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#define SPI_WR_BYTE_ORDER (BIT(11))
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#define SPI_RD_BYTE_ORDER (BIT(10))
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#define SPI_CK_OUT_EDGE (BIT(7))
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#define SPI_CK_I_EDGE (BIT(6))
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#define SPI_CS_SETUP (BIT(5))
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#define SPI_CS_HOLD (BIT(4))
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#define SPI_FLASH_MODE (BIT(2))
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#define SPI_CTRL1(i) (REG_SPI_BASE(i) + 0xc)
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#define SPI_CS_HOLD_DELAY 0xf
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#define SPI_CS_HOLD_DELAY_S 28
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#define SPI_CS_HOLD_DELAY_RES 0xfff
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#define SPI_CS_HOLD_DELAY_RES_S 16
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#define SPI_USER1(i) (REG_SPI_BASE(i) + 0x20)
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#define SPI_USR_ADDR_BITLEN 0x0000003F
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#define SPI_USR_ADDR_BITLEN_S 26
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#define SPI_USR_MOSI_BITLEN 0x000001FF
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#define SPI_USR_MOSI_BITLEN_S 17
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#define SPI_USR_MISO_BITLEN 0x000001FF
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#define SPI_USR_MISO_BITLEN_S 8
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#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
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#define SPI_USR_DUMMY_CYCLELEN_S 0
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#define SPI_USER2(i) (REG_SPI_BASE(i) + 0x24)
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#define SPI_USR_COMMAND_BITLEN 0x0000000F
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#define SPI_USR_COMMAND_BITLEN_S 28
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#define SPI_USR_COMMAND_VALUE 0x0000FFFF
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#define SPI_USR_COMMAND_VALUE_S 0
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#define SPI_RD_STATUS(i) (REG_SPI_BASE(i) + 0x10)
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#define SPI_WR_STATUS(i) (REG_SPI_BASE(i) + 0x28)
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#define SPI_CTRL2(i) (REG_SPI_BASE(i) + 0x14)
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#define SPI_PIN(i) (REG_SPI_BASE(i) + 0x2C)
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#define SPI_CS2_DIS (BIT(2))
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#define SPI_CS1_DIS (BIT(1))
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#define SPI_CS0_DIS (BIT(0))
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#define SPI_CS_DELAY_NUM 0x0000000F
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#define SPI_CS_DELAY_NUM_S 28
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#define SPI_CS_DELAY_MODE 0x00000003
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#define SPI_CS_DELAY_MODE_S 26
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#define SPI_MOSI_DELAY_NUM 0x00000007
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#define SPI_MOSI_DELAY_NUM_S 23
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#define SPI_MOSI_DELAY_MODE 0x00000003
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#define SPI_MOSI_DELAY_MODE_S 21
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#define SPI_MISO_DELAY_NUM 0x00000007
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#define SPI_MISO_DELAY_NUM_S 18
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#define SPI_MISO_DELAY_MODE 0x00000003
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#define SPI_MISO_DELAY_MODE_S 16
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#define SPI_CLOCK(i) (REG_SPI_BASE(i) + 0x18)
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#define SPI_CLK_EQU_SYSCLK (BIT(31))
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#define SPI_CLKDIV_PRE 0x00001FFF
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#define SPI_CLKDIV_PRE_S 18
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#define SPI_CLKCNT_N 0x0000003F
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#define SPI_CLKCNT_N_S 12
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#define SPI_CLKCNT_H 0x0000003F
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#define SPI_CLKCNT_H_S 6
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#define SPI_CLKCNT_L 0x0000003F
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#define SPI_CLKCNT_L_S 0
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#define SPI_SLAVE(i) (REG_SPI_BASE(i) + 0x30)
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#define SPI_SYNC_RESET (BIT(31))
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#define SPI_SLAVE_MODE (BIT(30))
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#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
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#define SPI_SLV_WR_RD_STA_EN (BIT(28))
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#define SPI_SLV_CMD_DEFINE (BIT(27))
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#define SPI_TRANS_CNT 0x0000000F
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#define SPI_TRANS_CNT_S 23
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#define SPI_TRANS_DONE_EN (BIT(9))
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#define SPI_SLV_WR_STA_DONE_EN (BIT(8))
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#define SPI_SLV_RD_STA_DONE_EN (BIT(7))
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#define SPI_SLV_WR_BUF_DONE_EN (BIT(6))
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#define SPI_SLV_RD_BUF_DONE_EN (BIT(5))
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#define SLV_SPI_INT_EN 0x0000001f
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#define SLV_SPI_INT_EN_S 5
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#define SPI_TRANS_DONE (BIT(4))
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#define SPI_SLV_WR_STA_DONE (BIT(3))
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#define SPI_SLV_RD_STA_DONE (BIT(2))
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#define SPI_SLV_WR_BUF_DONE (BIT(1))
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#define SPI_SLV_RD_BUF_DONE (BIT(0))
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#define SPI_USER(i) (REG_SPI_BASE(i) + 0x1C)
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#define SPI_USR_COMMAND (BIT(31))
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#define SPI_USR_ADDR (BIT(30))
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#define SPI_USR_DUMMY (BIT(29))
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#define SPI_USR_MISO (BIT(28))
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#define SPI_USR_MOSI (BIT(27))
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#define SPI_SLAVE1(i) (REG_SPI_BASE(i) + 0x34)
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#define SPI_SLV_STATUS_BITLEN 0x0000001F
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#define SPI_SLV_STATUS_BITLEN_S 27
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#define SPI_SLV_BUF_BITLEN 0x000001FF
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#define SPI_SLV_BUF_BITLEN_S 16
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#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
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#define SPI_SLV_RD_ADDR_BITLEN_S 10
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#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
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#define SPI_SLV_WR_ADDR_BITLEN_S 4
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#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
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#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
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#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
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#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
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#define SPI_USR_MOSI_HIGHPART (BIT(25))
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#define SPI_USR_MISO_HIGHPART (BIT(24))
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#define SPI_SLAVE2(i) (REG_SPI_BASE(i) + 0x38)
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#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF
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#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
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#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF
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#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
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#define SPI_SLV_WRSTR_DUMMY_CYCLELEN 0x000000FF
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#define SPI_SIO (BIT(16))
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#define SPI_FWRITE_QIO (BIT(15))
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#define SPI_FWRITE_DIO (BIT(14))
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#define SPI_FWRITE_QUAD (BIT(13))
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#define SPI_FWRITE_DUAL (BIT(12))
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#define SPI_WR_BYTE_ORDER (BIT(11))
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#define SPI_RD_BYTE_ORDER (BIT(10))
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#define SPI_CK_OUT_EDGE (BIT(7))
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#define SPI_CK_I_EDGE (BIT(6))
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#define SPI_CS_SETUP (BIT(5))
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#define SPI_CS_HOLD (BIT(4))
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#define SPI_FLASH_MODE (BIT(2))
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#define SPI_USER1(i) (REG_SPI_BASE(i) + 0x20)
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#define SPI_USR_ADDR_BITLEN 0x0000003F
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#define SPI_USR_ADDR_BITLEN_S 26
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#define SPI_USR_MOSI_BITLEN 0x000001FF
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#define SPI_USR_MOSI_BITLEN_S 17
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#define SPI_USR_MISO_BITLEN 0x000001FF
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#define SPI_USR_MISO_BITLEN_S 8
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#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
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#define SPI_USR_DUMMY_CYCLELEN_S 0
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#define SPI_USER2(i) (REG_SPI_BASE(i) + 0x24)
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#define SPI_USR_COMMAND_BITLEN 0x0000000F
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#define SPI_USR_COMMAND_BITLEN_S 28
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#define SPI_USR_COMMAND_VALUE 0x0000FFFF
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#define SPI_USR_COMMAND_VALUE_S 0
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#define SPI_WR_STATUS(i) (REG_SPI_BASE(i) + 0x28)
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#define SPI_PIN(i) (REG_SPI_BASE(i) + 0x2C)
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#define SPI_IDLE_EDGE (BIT(29))
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#define SPI_CS2_DIS (BIT(2))
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#define SPI_CS1_DIS (BIT(1))
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#define SPI_CS0_DIS (BIT(0))
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#define SPI_SLAVE(i) (REG_SPI_BASE(i) + 0x30)
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#define SPI_SYNC_RESET (BIT(31))
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#define SPI_SLAVE_MODE (BIT(30))
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#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
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#define SPI_SLV_WR_RD_STA_EN (BIT(28))
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#define SPI_SLV_CMD_DEFINE (BIT(27))
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#define SPI_TRANS_CNT 0x0000000F
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#define SPI_TRANS_CNT_S 23
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#define SPI_TRANS_DONE_EN (BIT(9))
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#define SPI_SLV_WR_STA_DONE_EN (BIT(8))
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#define SPI_SLV_RD_STA_DONE_EN (BIT(7))
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#define SPI_SLV_WR_BUF_DONE_EN (BIT(6))
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#define SPI_SLV_RD_BUF_DONE_EN (BIT(5))
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#define SLV_SPI_INT_EN 0x0000001f
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#define SLV_SPI_INT_EN_S 5
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#define SPI_TRANS_DONE (BIT(4))
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#define SPI_SLV_WR_STA_DONE (BIT(3))
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#define SPI_SLV_RD_STA_DONE (BIT(2))
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#define SPI_SLV_WR_BUF_DONE (BIT(1))
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#define SPI_SLV_RD_BUF_DONE (BIT(0))
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#define SPI_SLAVE1(i) (REG_SPI_BASE(i) + 0x34)
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#define SPI_SLV_STATUS_BITLEN 0x0000001F
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#define SPI_SLV_STATUS_BITLEN_S 27
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#define SPI_SLV_BUF_BITLEN 0x000001FF
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#define SPI_SLV_BUF_BITLEN_S 16
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#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
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#define SPI_SLV_RD_ADDR_BITLEN_S 10
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#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
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#define SPI_SLV_WR_ADDR_BITLEN_S 4
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#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
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#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
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#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
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#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
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#define SPI_SLAVE2(i) (REG_SPI_BASE(i) + 0x38)
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#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0X000000FF
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#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
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#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0X000000FF
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#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
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#define SPI_SLV_WRSTR_DUMMY_CYCLELEN 0X000000FF
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#define SPI_SLV_WRSTR_DUMMY_CYCLELEN_S 8
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#define SPI_SLV_RDSTR_DUMMY_CYCLELEN 0x000000FF
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#define SPI_SLV_RDSTR_DUMMY_CYCLELEN_S 0
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#define SPI_SLV_RDSTR_DUMMY_CYCLELEN 0x000000FF
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#define SPI_SLV_RDSTR_DUMMY_CYCLELEN_S 0
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#define SPI_SLAVE3(i) (REG_SPI_BASE(i) + 0x3C)
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#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
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#define SPI_SLV_WRSTA_CMD_VALUE_S 24
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#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
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#define SPI_SLV_RDSTA_CMD_VALUE_S 16
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#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
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#define SPI_SLV_WRBUF_CMD_VALUE_S 8
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#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
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#define SPI_SLV_RDBUF_CMD_VALUE_S 0
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#define SPI_SLAVE3(i) (REG_SPI_BASE(i) + 0x3C)
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#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
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#define SPI_SLV_WRSTA_CMD_VALUE_S 24
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#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
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#define SPI_SLV_RDSTA_CMD_VALUE_S 16
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#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
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#define SPI_SLV_WRBUF_CMD_VALUE_S 8
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#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
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#define SPI_SLV_RDBUF_CMD_VALUE_S 0
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#define SPI_W0(i) (REG_SPI_BASE(i) + 0x40)
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#define SPI_W1(i) (REG_SPI_BASE(i) + 0x44)
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#define SPI_W2(i) (REG_SPI_BASE(i) + 0x48)
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#define SPI_W3(i) (REG_SPI_BASE(i) + 0x4C)
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#define SPI_W4(i) (REG_SPI_BASE(i) + 0x50)
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#define SPI_W5(i) (REG_SPI_BASE(i) + 0x54)
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#define SPI_W6(i) (REG_SPI_BASE(i) + 0x58)
|
||||
#define SPI_W7(i) (REG_SPI_BASE(i) + 0x5C)
|
||||
#define SPI_W8(i) (REG_SPI_BASE(i) + 0x60)
|
||||
#define SPI_W9(i) (REG_SPI_BASE(i) + 0x64)
|
||||
#define SPI_W10(i) (REG_SPI_BASE(i) + 0x68)
|
||||
#define SPI_W11(i) (REG_SPI_BASE(i) + 0x6C)
|
||||
#define SPI_W12(i) (REG_SPI_BASE(i) + 0x70)
|
||||
#define SPI_W13(i) (REG_SPI_BASE(i) + 0x74)
|
||||
#define SPI_W14(i) (REG_SPI_BASE(i) + 0x78)
|
||||
#define SPI_W15(i) (REG_SPI_BASE(i) + 0x7C)
|
||||
#define SPI_W0(i) (REG_SPI_BASE(i) +0x40)
|
||||
#define SPI_W1(i) (REG_SPI_BASE(i) +0x44)
|
||||
#define SPI_W2(i) (REG_SPI_BASE(i) +0x48)
|
||||
#define SPI_W3(i) (REG_SPI_BASE(i) +0x4C)
|
||||
#define SPI_W4(i) (REG_SPI_BASE(i) +0x50)
|
||||
#define SPI_W5(i) (REG_SPI_BASE(i) +0x54)
|
||||
#define SPI_W6(i) (REG_SPI_BASE(i) +0x58)
|
||||
#define SPI_W7(i) (REG_SPI_BASE(i) +0x5C)
|
||||
#define SPI_W8(i) (REG_SPI_BASE(i) +0x60)
|
||||
#define SPI_W9(i) (REG_SPI_BASE(i) +0x64)
|
||||
#define SPI_W10(i) (REG_SPI_BASE(i) +0x68)
|
||||
#define SPI_W11(i) (REG_SPI_BASE(i) +0x6C)
|
||||
#define SPI_W12(i) (REG_SPI_BASE(i) +0x70)
|
||||
#define SPI_W13(i) (REG_SPI_BASE(i) +0x74)
|
||||
#define SPI_W14(i) (REG_SPI_BASE(i) +0x78)
|
||||
#define SPI_W15(i) (REG_SPI_BASE(i) +0x7C)
|
||||
|
||||
#define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
|
||||
#define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
|
||||
|
||||
#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
|
||||
#define SPI_INT_HOLD_ENA 0x00000003
|
||||
#define SPI_INT_HOLD_ENA_S 0
|
||||
#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
|
||||
#define SPI_INT_HOLD_ENA 0x00000003
|
||||
#define SPI_INT_HOLD_ENA_S 0
|
||||
|
||||
#endif // SPI_REGISTER_H_INCLUDED
|
||||
#define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
|
||||
#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
|
||||
|
||||
#define SPI_ENABLE_AHB BIT17
|
||||
|
||||
#define SPI_FLASH_CLK_EQU_SYSCLK BIT12
|
||||
|
||||
//SPI flash command
|
||||
#define SPI_FLASH_READ BIT31
|
||||
#define SPI_FLASH_WREN BIT30
|
||||
#define SPI_FLASH_WRDI BIT29
|
||||
#define SPI_FLASH_RDID BIT28
|
||||
#define SPI_FLASH_RDSR BIT27
|
||||
#define SPI_FLASH_WRSR BIT26
|
||||
#define SPI_FLASH_PP BIT25
|
||||
#define SPI_FLASH_SE BIT24
|
||||
#define SPI_FLASH_BE BIT23
|
||||
#define SPI_FLASH_CE BIT22
|
||||
#define SPI_FLASH_RES BIT20
|
||||
#define SPI_FLASH_DPD BIT21
|
||||
#define SPI_FLASH_HPM BIT19
|
||||
|
||||
//SPI address register
|
||||
#define SPI_FLASH_BYTES_LEN 24
|
||||
#define SPI_BUFF_BYTE_NUM 32
|
||||
#define IODATA_START_ADDR BIT0
|
||||
|
||||
//SPI status register
|
||||
#define SPI_FLASH_BUSY_FLAG BIT0
|
||||
#define SPI_FLASH_WRENABLE_FLAG BIT1
|
||||
#define SPI_FLASH_BP0 BIT2
|
||||
#define SPI_FLASH_BP1 BIT3
|
||||
#define SPI_FLASH_BP2 BIT4
|
||||
#define SPI_FLASH_TOP_BOT_PRO_FLAG BIT5
|
||||
#define SPI_FLASH_STATUS_PRO_FLAG BIT7
|
||||
|
||||
#define FLASH_WR_PROTECT (SPI_FLASH_BP0|SPI_FLASH_BP1|SPI_FLASH_BP2)
|
||||
|
||||
#define SPI 0
|
||||
|
||||
#define PERIPHS_SPI_FLASH_C0 SPI_W0(SPI)
|
||||
#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL(SPI)
|
||||
#define PERIPHS_SPI_FLASH_CMD SPI_CMD(SPI)
|
||||
|
||||
#define SPI0_CLK_EQU_SYSCLK BIT8
|
||||
|
||||
#define PERIPHS_SPI_FLASH_USRREG (0x60000200 + 0x1c)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
236
components/esp8266/include/esp8266/spi_struct.h
Normal file
236
components/esp8266/include/esp8266/spi_struct.h
Normal file
@ -0,0 +1,236 @@
|
||||
// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp8266/eagle_soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 18; /*reserved*/
|
||||
uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
|
||||
uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
|
||||
uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
|
||||
uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
|
||||
uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cmd;
|
||||
uint32_t addr; /*addr to slave / from master. SPI transfer from the MSB to the LSB. If length > 32 bits, then address continues from MSB of wr_status.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t clkcnt_l: 4;
|
||||
uint32_t clkcnt_h: 4;
|
||||
uint32_t clkcnt_n: 4;
|
||||
uint32_t clk_equ_sysclk: 1;
|
||||
uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.*/
|
||||
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/
|
||||
uint32_t reserved15: 5; /*reserved*/
|
||||
uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
|
||||
uint32_t reserved21: 2; /*reserved*/
|
||||
uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
|
||||
uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
|
||||
uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/
|
||||
uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/
|
||||
uint32_t reserved27: 5; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 16; /*reserved*/
|
||||
uint32_t cs_hold_delay_res: 12; /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/
|
||||
uint32_t cs_hold_delay: 4; /*SPI cs signal is delayed by spi clock cycles*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t status: 16; /*In the slave mode, it is the status for master to read out.*/
|
||||
uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/
|
||||
uint32_t status_ext: 8; /*In the slave mode,it is the status for master to read out.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rd_status; /*In the slave mode, this register are the status register for the master to read out.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 16; /*reserved*/
|
||||
uint32_t miso_delay_mode: 2; /*MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
|
||||
uint32_t miso_delay_num: 3; /*MISO signals are delayed by system clock cycles*/
|
||||
uint32_t mosi_delay_mode: 2; /*MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
|
||||
uint32_t mosi_delay_num: 3; /*MOSI signals are delayed by system clock cycles*/
|
||||
uint32_t cs_delay_mode: 2; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
|
||||
uint32_t cs_delay_num: 4; /*spi_cs signal is delayed by system clock cycles*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_n. In the slave mode it must be 0.*/
|
||||
uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_n+1)/2-1). In the slave mode it must be 0.*/
|
||||
uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_n+1)*/
|
||||
uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk.*/
|
||||
uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clock;
|
||||
union {
|
||||
struct {
|
||||
uint32_t duplex: 1;
|
||||
uint32_t reserved1: 1; /*reserved*/
|
||||
uint32_t flash_mode: 1;
|
||||
uint32_t reserved3: 1; /*reserved*/
|
||||
uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
|
||||
uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
|
||||
uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.*/
|
||||
uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/
|
||||
uint32_t reserved8: 2; /*reserved*/
|
||||
uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian*/
|
||||
uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/
|
||||
uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/
|
||||
uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/
|
||||
uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/
|
||||
uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/
|
||||
uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/
|
||||
uint32_t reserved17: 7; /*reserved*/
|
||||
uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
|
||||
uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
|
||||
uint32_t reserved26: 1; /*reserved*/
|
||||
uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/
|
||||
uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/
|
||||
uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/
|
||||
uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/
|
||||
uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
|
||||
uint32_t usr_miso_bitlen: 9; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
|
||||
uint32_t usr_mosi_bitlen: 9; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
|
||||
uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_command_value: 16; /*The value of command. Output sequence: bit 7-0 and then 15-8.*/
|
||||
uint32_t reserved16: 12; /*reserved*/
|
||||
uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user2;
|
||||
uint32_t wr_status; /*In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t cs0_dis: 1; /*SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/
|
||||
uint32_t cs1_dis: 1; /*SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/
|
||||
uint32_t cs2_dis: 1; /*SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/
|
||||
uint32_t reserved3: 16; /*reserved*/
|
||||
uint32_t slave_mode: 1; /*1: Both CLK and CS are input, 0: Both CLK and CS are output*/
|
||||
uint32_t reserved20: 9; /*reserved*/
|
||||
uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/
|
||||
uint32_t reserved30: 2; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} pin;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/
|
||||
uint32_t wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/
|
||||
uint32_t rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/
|
||||
uint32_t wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/
|
||||
uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/
|
||||
uint32_t rd_buf_inten: 1; /*The interrupt enable bit for the completion of read-buffer operation in the slave mode.*/
|
||||
uint32_t wr_buf_inten: 1; /*The interrupt enable bit for the completion of write-buffer operation in the slave mode.*/
|
||||
uint32_t rd_sta_inten: 1; /*The interrupt enable bit for the completion of read-status operation in the slave mode.*/
|
||||
uint32_t wr_sta_inten: 1; /*The interrupt enable bit for the completion of write-status operation in the slave mode.*/
|
||||
uint32_t trans_inten: 1; /*The interrupt enable bit for the completion of any operation in both the master mode and the slave mode.*/
|
||||
uint32_t reserved10: 13; /*reserved*/
|
||||
uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode.*/
|
||||
uint32_t cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer 4: read-status*/
|
||||
uint32_t wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/
|
||||
uint32_t wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/
|
||||
uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/
|
||||
uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slave;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/
|
||||
uint32_t wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/
|
||||
uint32_t rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/
|
||||
uint32_t wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/
|
||||
uint32_t wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/
|
||||
uint32_t rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/
|
||||
uint32_t buf_bitlen: 9; /*In the slave mode it is the length of buffer bit.*/
|
||||
uint32_t status_readback: 1; /*In the slave mode it is the bit decide whether master reads rd_status register or wr_status register data. 0: rd_status: 1: wr_status*/
|
||||
uint32_t reserved25: 1; /*reserved*/
|
||||
uint32_t status_bitlen: 5; /*In the slave mode it is the length of status bit.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slave1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/
|
||||
uint32_t wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/
|
||||
uint32_t rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/
|
||||
uint32_t wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slave2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/
|
||||
uint32_t wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/
|
||||
uint32_t rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/
|
||||
uint32_t wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slave3;
|
||||
uint32_t data_buf[16]; /*data buffer*/
|
||||
uint32_t reserved_80[30];
|
||||
uint32_t ext2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ,idle, phase 2: hold at ,prepare, phase.*/
|
||||
uint32_t reserved2: 30; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ext3;
|
||||
} spi_dev_t;
|
||||
|
||||
extern spi_dev_t SPI0;
|
||||
extern spi_dev_t SPI1;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user