mirror of
https://github.com/espressif/ESP8266_RTOS_SDK.git
synced 2025-06-05 05:01:54 +08:00
refactor(hspi): Refactor hspi driver for esp8266 idf
This commit is contained in:
XiongYu
433
components/esp8266/include/driver/spi.h
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433
components/esp8266/include/driver/spi.h
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// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include "esp_err.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SPI_NUM_MAX 2
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// SPI bus CPOL and CPHA definition
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#define SPI_CPOL_LOW 0
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#define SPI_CPOL_HIGH 1
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#define SPI_CPHA_LOW 0
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#define SPI_CPHA_HIGH 1
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// SPI bus data sequence definition
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#define SPI_BIT_ORDER_MSB_FIRST 1
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#define SPI_BIT_ORDER_LSB_FIRST 0
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#define SPI_BYTE_ORDER_MSB_FIRST 1
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#define SPI_BYTE_ORDER_LSB_FIRST 0
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// SPI default bus interface parameter definition
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// CS_EN:1, MISO_EN:1, MOSI_EN:1, BYTE_TX_ORDER:1, BYTE_TX_ORDER:1, BIT_RX_ORDER:0, BIT_TX_ORDER:0, CPHA:0, CPOL:0
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#define SPI_DEFAULT_INTERFACE 0x1F0
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// SPI master default interrupt enable definition
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// TRANS_DONE: true, WRITE_STATUS: false, READ_STATUS: false, WRITE_BUFFER: false, READ_BUFFER: false
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#define SPI_MASTER_DEFAULT_INTR_ENABLE 0x10
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// SPI slave default interrupt enable definition
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// TRANS_DONE: false, WRITE_STATUS: true, READ_STATUS: true, WRITE_BUFFER: true, READ_BUFFER: ture
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#define SPI_SLAVE_DEFAULT_INTR_ENABLE 0x0F
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// SPI event definition
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#define SPI_INIT_EVENT 0
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#define SPI_TRANS_START_EVENT 1
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#define SPI_TRANS_DONE_EVENT 2
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#define SPI_DEINIT_EVENT 3
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#define SPI_MASTER_WRITE_DATA_TO_SLAVE_CMD 2
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#define SPI_MASTER_READ_DATA_FROM_SLAVE_CMD 3
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#define SPI_MASTER_WRITE_STATUS_TO_SLAVE_CMD 1
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#define SPI_MASTER_READ_STATUS_FROM_SLAVE_CMD 4
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#define SPI_SLV_RD_BUF_DONE (BIT(0))
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#define SPI_SLV_WR_BUF_DONE (BIT(1))
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#define SPI_SLV_RD_STA_DONE (BIT(2))
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#define SPI_SLV_WR_STA_DONE (BIT(3))
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#define SPI_TRANS_DONE (BIT(4))
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typedef void (*spi_event_callback_t)(int event, void *arg);
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// ESP8266 has two hardware SPI, CSPI and HSPI. Currently, HSPI can be used arbitrarily.
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// SPI peripheral enumeration
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typedef enum {
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CSPI_HOST = 0,
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HSPI_HOST
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} spi_host_t;
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// SPI clock division factor enumeration
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typedef enum {
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SPI_2MHz_DIV = 40,
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SPI_4MHz_DIV = 20,
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SPI_5MHz_DIV = 16,
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SPI_8MHz_DIV = 10,
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SPI_10MHz_DIV = 8,
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SPI_16MHz_DIV = 5,
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SPI_20MHz_DIV = 4,
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SPI_40MHz_DIV = 2,
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SPI_80MHz_DIV = 1,
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} spi_clk_div_t;
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// SPI working mode enumeration
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typedef enum {
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SPI_MASTER_MODE,
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SPI_SLAVE_MODE
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} spi_mode_t;
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// SPI interrupt enable union type definition
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typedef union {
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struct {
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uint32_t read_buffer: 1;
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uint32_t write_buffer: 1;
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uint32_t read_status: 1;
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uint32_t write_status: 1;
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uint32_t trans_done: 1;
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uint32_t reserved5: 27;
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};
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uint32_t val;
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} spi_intr_enable_t;
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// SPI bus interface parameter union type definition
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typedef union {
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struct {
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uint32_t cpol: 1; // Clock Polarity
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uint32_t cpha: 1; // Clock Phase
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uint32_t bit_tx_order: 1;
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uint32_t bit_rx_order: 1;
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uint32_t byte_tx_order: 1;
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uint32_t byte_rx_order: 1;
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uint32_t mosi_en: 1;
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uint32_t miso_en: 1;
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uint32_t cs_en: 1;
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uint32_t reserved9: 23;
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};
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uint32_t val;
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} spi_interface_t;
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// SPI transmission parameter structure type definition
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typedef struct {
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uint16_t *cmd;
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uint32_t *addr;
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uint32_t *mosi;
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uint32_t *miso;
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union {
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struct {
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uint32_t cmd: 5;
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uint32_t addr: 7;
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uint32_t mosi: 10;
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uint32_t miso: 10;
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};
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uint32_t val;
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} bits;
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} spi_trans_t;
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// SPI initialization parameter structure type definition
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typedef struct {
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spi_interface_t interface;
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spi_intr_enable_t intr_enable;
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spi_event_callback_t event_cb;
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spi_mode_t mode;
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spi_clk_div_t clk_div;
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} spi_config_t;
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/**
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* @brief Get the SPI clock division factor
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param clk_div Pointer to accept clock division factor
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_get_clk_div(spi_host_t host, spi_clk_div_t *clk_div);
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/**
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* @brief Get SPI Interrupt Enable
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param intr_enable Pointer to accept interrupt enable
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_get_intr_enable(spi_host_t host, spi_intr_enable_t *intr_enable);
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/**
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* @brief Get SPI working mode
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param mode Pointer to accept working mode
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_get_mode(spi_host_t host, spi_mode_t *mode);
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/**
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* @brief Get SPI bus interface configuration
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param interface Pointer to accept bus interface configuration
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_get_interface(spi_host_t host, spi_interface_t *interface);
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/**
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* @brief Get the SPI event callback function
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param event_cb Pointer to accept event callback function
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_get_event_callback(spi_host_t host, spi_event_callback_t *event_cb);
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/**
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* @brief Set the SPI clock division factor
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param clk_div Pointer to deliver clock division factor
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_set_clk_div(spi_host_t host, spi_clk_div_t *clk_div);
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/**
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* @brief Set SPI interrupt enable
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param intr_enable Pointer to deliver interrupt enable
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_set_intr_enable(spi_host_t host, spi_intr_enable_t *intr_enable);
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/**
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* @brief Set the SPI mode of operation
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param mode Pointer to deliver working mode
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_set_mode(spi_host_t host, spi_mode_t *mode);
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/**
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* @brief Get SPI dummy bitlen
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param bitlen Pointer to accept dummy bitlen
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_get_dummy(spi_host_t host, uint16_t *bitlen);
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/**
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* @brief Set SPI dummy bitlen
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param bitlen Pointer to deliver dummy bitlen
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_set_dummy(spi_host_t host, uint16_t *bitlen);
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/**
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* @brief Set SPI bus interface configuration
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param interface Pointer to deliver bus interface configuration
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_set_interface(spi_host_t host, spi_interface_t *interface);
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/**
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* @brief Set the SPI event callback function
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*
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* @note This event_cb will be called from an ISR. So there is a stack
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* size limit (configurable as "ISR stack size" in menuconfig). This
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* limit is smaller compared to a global SPI interrupt handler due
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* to the additional level of indirection.
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param event_cb Pointer to deliver event callback function
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_set_event_callback(spi_host_t host, spi_event_callback_t *event_cb);
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/**
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* @brief Get SPI slave wr_status register
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param status Pointer to accept wr_status register
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_slave_get_status(spi_host_t host, uint32_t *status);
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/**
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* @brief Set SPI slave rd_status register
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param status Pointer to deliver rd_status register
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_slave_set_status(spi_host_t host, uint32_t *status);
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/**
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* @brief SPI data transfer function
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*
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* @note If the bit of the corresponding phase in the transmission parameter is 0, its data will not work.
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* For example: trans.bits.cmd = 0, cmd will not be transmitted
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param trans Transmission parameter structure
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_trans(spi_host_t host, spi_trans_t trans);
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/**
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* @brief Deinit the spi
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @return
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* - ESP_OK Success
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* - ESP_FAIL spi has not been initialized yet
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*/
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esp_err_t spi_deinit(spi_host_t host);
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/**
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* @brief Initialize the spi
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*
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* @note SPI0 has been used by FLASH and cannot be used by the user temporarily.
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*
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* @param host SPI peripheral number
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* - CSPI_HOST SPI0
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* - HSPI_HOST SPI1
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*
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* @param config Pointer to deliver initialize configuration parameter
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_NO_MEM malloc fail
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* - ESP_FAIL spi has been initialized
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*/
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esp_err_t spi_init(spi_host_t host, spi_config_t *config);
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#ifdef __cplusplus
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}
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#endif
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@ -1,263 +0,0 @@
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// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef SPI_REGISTER_H_INCLUDED
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#define SPI_REGISTER_H_INCLUDED
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#include "esp8266/eagle_soc.h"
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#define REG_SPI_BASE(i) (0x60000200-i*0x100)
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#define SPI_CMD(i) (REG_SPI_BASE(i) + 0x0)
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#define SPI_FLASH_READ BIT31
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#define SPI_FLASH_WREN BIT30
|
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#define SPI_FLASH_WRDI BIT29
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#define SPI_FLASH_RDID BIT28
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#define SPI_FLASH_RDSR BIT27
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#define SPI_FLASH_WRSR BIT26
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#define SPI_FLASH_PP BIT25
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#define SPI_FLASH_SE BIT24
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#define SPI_FLASH_BE BIT23
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#define SPI_FLASH_CE BIT22
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#define SPI_FLASH_RES BIT20
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#define SPI_USR (BIT(18))
|
||||
|
||||
#define SPI_ADDR(i) (REG_SPI_BASE(i) + 0x4)
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||||
|
||||
#define SPI_CTRL(i) (REG_SPI_BASE(i) + 0x8)
|
||||
#define SPI_WR_BIT_ORDER (BIT(26))
|
||||
#define SPI_RD_BIT_ORDER (BIT(25))
|
||||
#define SPI_QIO_MODE (BIT(24))
|
||||
#define SPI_DIO_MODE (BIT(23))
|
||||
#define SPI_QOUT_MODE (BIT(20))
|
||||
#define SPI_DOUT_MODE (BIT(14))
|
||||
#define SPI_FASTRD_MODE (BIT(13))
|
||||
|
||||
#define SPI_CTRL1(i) (REG_SPI_BASE(i) + 0xc)
|
||||
#define SPI_CS_HOLD_DELAY 0xf
|
||||
#define SPI_CS_HOLD_DELAY_S 28
|
||||
#define SPI_CS_HOLD_DELAY_RES 0xfff
|
||||
#define SPI_CS_HOLD_DELAY_RES_S 16
|
||||
|
||||
|
||||
#define SPI_RD_STATUS(i) (REG_SPI_BASE(i) + 0x10)
|
||||
|
||||
#define SPI_CTRL2(i) (REG_SPI_BASE(i) + 0x14)
|
||||
|
||||
#define SPI_CS_DELAY_NUM 0x0000000F
|
||||
#define SPI_CS_DELAY_NUM_S 28
|
||||
#define SPI_CS_DELAY_MODE 0x00000003
|
||||
#define SPI_CS_DELAY_MODE_S 26
|
||||
#define SPI_MOSI_DELAY_NUM 0x00000007
|
||||
#define SPI_MOSI_DELAY_NUM_S 23
|
||||
#define SPI_MOSI_DELAY_MODE 0x00000003
|
||||
#define SPI_MOSI_DELAY_MODE_S 21
|
||||
#define SPI_MISO_DELAY_NUM 0x00000007
|
||||
#define SPI_MISO_DELAY_NUM_S 18
|
||||
#define SPI_MISO_DELAY_MODE 0x00000003
|
||||
#define SPI_MISO_DELAY_MODE_S 16
|
||||
#define SPI_CLOCK(i) (REG_SPI_BASE(i) + 0x18)
|
||||
#define SPI_CLK_EQU_SYSCLK (BIT(31))
|
||||
#define SPI_CLKDIV_PRE 0x00001FFF
|
||||
#define SPI_CLKDIV_PRE_S 18
|
||||
#define SPI_CLKCNT_N 0x0000003F
|
||||
#define SPI_CLKCNT_N_S 12
|
||||
#define SPI_CLKCNT_H 0x0000003F
|
||||
#define SPI_CLKCNT_H_S 6
|
||||
#define SPI_CLKCNT_L 0x0000003F
|
||||
#define SPI_CLKCNT_L_S 0
|
||||
|
||||
#define SPI_USER(i) (REG_SPI_BASE(i) + 0x1C)
|
||||
#define SPI_USR_COMMAND (BIT(31))
|
||||
#define SPI_USR_ADDR (BIT(30))
|
||||
#define SPI_USR_DUMMY (BIT(29))
|
||||
#define SPI_USR_MISO (BIT(28))
|
||||
#define SPI_USR_MOSI (BIT(27))
|
||||
|
||||
#define SPI_USR_MOSI_HIGHPART (BIT(25))
|
||||
#define SPI_USR_MISO_HIGHPART (BIT(24))
|
||||
|
||||
|
||||
#define SPI_SIO (BIT(16))
|
||||
#define SPI_FWRITE_QIO (BIT(15))
|
||||
#define SPI_FWRITE_DIO (BIT(14))
|
||||
#define SPI_FWRITE_QUAD (BIT(13))
|
||||
#define SPI_FWRITE_DUAL (BIT(12))
|
||||
#define SPI_WR_BYTE_ORDER (BIT(11))
|
||||
#define SPI_RD_BYTE_ORDER (BIT(10))
|
||||
#define SPI_CK_OUT_EDGE (BIT(7))
|
||||
#define SPI_CK_I_EDGE (BIT(6))
|
||||
#define SPI_CS_SETUP (BIT(5))
|
||||
#define SPI_CS_HOLD (BIT(4))
|
||||
#define SPI_FLASH_MODE (BIT(2))
|
||||
|
||||
#define SPI_USER1(i) (REG_SPI_BASE(i) + 0x20)
|
||||
#define SPI_USR_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_USR_ADDR_BITLEN_S 26
|
||||
#define SPI_USR_MOSI_BITLEN 0x000001FF
|
||||
#define SPI_USR_MOSI_BITLEN_S 17
|
||||
#define SPI_USR_MISO_BITLEN 0x000001FF
|
||||
#define SPI_USR_MISO_BITLEN_S 8
|
||||
|
||||
#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_USR_DUMMY_CYCLELEN_S 0
|
||||
|
||||
#define SPI_USER2(i) (REG_SPI_BASE(i) + 0x24)
|
||||
#define SPI_USR_COMMAND_BITLEN 0x0000000F
|
||||
#define SPI_USR_COMMAND_BITLEN_S 28
|
||||
#define SPI_USR_COMMAND_VALUE 0x0000FFFF
|
||||
#define SPI_USR_COMMAND_VALUE_S 0
|
||||
|
||||
#define SPI_WR_STATUS(i) (REG_SPI_BASE(i) + 0x28)
|
||||
#define SPI_PIN(i) (REG_SPI_BASE(i) + 0x2C)
|
||||
#define SPI_IDLE_EDGE (BIT(29))
|
||||
#define SPI_CS2_DIS (BIT(2))
|
||||
#define SPI_CS1_DIS (BIT(1))
|
||||
#define SPI_CS0_DIS (BIT(0))
|
||||
|
||||
#define SPI_SLAVE(i) (REG_SPI_BASE(i) + 0x30)
|
||||
#define SPI_SYNC_RESET (BIT(31))
|
||||
#define SPI_SLAVE_MODE (BIT(30))
|
||||
#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
|
||||
#define SPI_SLV_WR_RD_STA_EN (BIT(28))
|
||||
#define SPI_SLV_CMD_DEFINE (BIT(27))
|
||||
#define SPI_TRANS_CNT 0x0000000F
|
||||
#define SPI_TRANS_CNT_S 23
|
||||
#define SPI_TRANS_DONE_EN (BIT(9))
|
||||
#define SPI_SLV_WR_STA_DONE_EN (BIT(8))
|
||||
#define SPI_SLV_RD_STA_DONE_EN (BIT(7))
|
||||
#define SPI_SLV_WR_BUF_DONE_EN (BIT(6))
|
||||
#define SPI_SLV_RD_BUF_DONE_EN (BIT(5))
|
||||
|
||||
|
||||
|
||||
#define SLV_SPI_INT_EN 0x0000001f
|
||||
#define SLV_SPI_INT_EN_S 5
|
||||
|
||||
#define SPI_TRANS_DONE (BIT(4))
|
||||
#define SPI_SLV_WR_STA_DONE (BIT(3))
|
||||
#define SPI_SLV_RD_STA_DONE (BIT(2))
|
||||
#define SPI_SLV_WR_BUF_DONE (BIT(1))
|
||||
#define SPI_SLV_RD_BUF_DONE (BIT(0))
|
||||
|
||||
#define SPI_SLAVE1(i) (REG_SPI_BASE(i) + 0x34)
|
||||
#define SPI_SLV_STATUS_BITLEN 0x0000001F
|
||||
#define SPI_SLV_STATUS_BITLEN_S 27
|
||||
#define SPI_SLV_BUF_BITLEN 0x000001FF
|
||||
#define SPI_SLV_BUF_BITLEN_S 16
|
||||
#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_SLV_RD_ADDR_BITLEN_S 10
|
||||
#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_SLV_WR_ADDR_BITLEN_S 4
|
||||
|
||||
#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
|
||||
#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
|
||||
#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
|
||||
#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
|
||||
|
||||
|
||||
|
||||
#define SPI_SLAVE2(i) (REG_SPI_BASE(i) + 0x38)
|
||||
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0X000000FF
|
||||
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
|
||||
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0X000000FF
|
||||
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
|
||||
#define SPI_SLV_WRSTR_DUMMY_CYCLELEN 0X000000FF
|
||||
#define SPI_SLV_WRSTR_DUMMY_CYCLELEN_S 8
|
||||
#define SPI_SLV_RDSTR_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_SLV_RDSTR_DUMMY_CYCLELEN_S 0
|
||||
|
||||
#define SPI_SLAVE3(i) (REG_SPI_BASE(i) + 0x3C)
|
||||
#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_WRSTA_CMD_VALUE_S 24
|
||||
#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_RDSTA_CMD_VALUE_S 16
|
||||
#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_WRBUF_CMD_VALUE_S 8
|
||||
#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_RDBUF_CMD_VALUE_S 0
|
||||
|
||||
#define SPI_W0(i) (REG_SPI_BASE(i) +0x40)
|
||||
#define SPI_W1(i) (REG_SPI_BASE(i) +0x44)
|
||||
#define SPI_W2(i) (REG_SPI_BASE(i) +0x48)
|
||||
#define SPI_W3(i) (REG_SPI_BASE(i) +0x4C)
|
||||
#define SPI_W4(i) (REG_SPI_BASE(i) +0x50)
|
||||
#define SPI_W5(i) (REG_SPI_BASE(i) +0x54)
|
||||
#define SPI_W6(i) (REG_SPI_BASE(i) +0x58)
|
||||
#define SPI_W7(i) (REG_SPI_BASE(i) +0x5C)
|
||||
#define SPI_W8(i) (REG_SPI_BASE(i) +0x60)
|
||||
#define SPI_W9(i) (REG_SPI_BASE(i) +0x64)
|
||||
#define SPI_W10(i) (REG_SPI_BASE(i) +0x68)
|
||||
#define SPI_W11(i) (REG_SPI_BASE(i) +0x6C)
|
||||
#define SPI_W12(i) (REG_SPI_BASE(i) +0x70)
|
||||
#define SPI_W13(i) (REG_SPI_BASE(i) +0x74)
|
||||
#define SPI_W14(i) (REG_SPI_BASE(i) +0x78)
|
||||
#define SPI_W15(i) (REG_SPI_BASE(i) +0x7C)
|
||||
|
||||
#define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
|
||||
|
||||
#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
|
||||
#define SPI_INT_HOLD_ENA 0x00000003
|
||||
#define SPI_INT_HOLD_ENA_S 0
|
||||
|
||||
#define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
|
||||
#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
|
||||
|
||||
#define SPI_ENABLE_AHB BIT17
|
||||
|
||||
#define SPI_FLASH_CLK_EQU_SYSCLK BIT12
|
||||
|
||||
//SPI flash command
|
||||
#define SPI_FLASH_READ BIT31
|
||||
#define SPI_FLASH_WREN BIT30
|
||||
#define SPI_FLASH_WRDI BIT29
|
||||
#define SPI_FLASH_RDID BIT28
|
||||
#define SPI_FLASH_RDSR BIT27
|
||||
#define SPI_FLASH_WRSR BIT26
|
||||
#define SPI_FLASH_PP BIT25
|
||||
#define SPI_FLASH_SE BIT24
|
||||
#define SPI_FLASH_BE BIT23
|
||||
#define SPI_FLASH_CE BIT22
|
||||
#define SPI_FLASH_RES BIT20
|
||||
#define SPI_FLASH_DPD BIT21
|
||||
#define SPI_FLASH_HPM BIT19
|
||||
|
||||
//SPI address register
|
||||
#define SPI_FLASH_BYTES_LEN 24
|
||||
#define SPI_BUFF_BYTE_NUM 32
|
||||
#define IODATA_START_ADDR BIT0
|
||||
|
||||
//SPI status register
|
||||
#define SPI_FLASH_BUSY_FLAG BIT0
|
||||
#define SPI_FLASH_WRENABLE_FLAG BIT1
|
||||
#define SPI_FLASH_BP0 BIT2
|
||||
#define SPI_FLASH_BP1 BIT3
|
||||
#define SPI_FLASH_BP2 BIT4
|
||||
#define SPI_FLASH_TOP_BOT_PRO_FLAG BIT5
|
||||
#define SPI_FLASH_STATUS_PRO_FLAG BIT7
|
||||
|
||||
#define FLASH_WR_PROTECT (SPI_FLASH_BP0|SPI_FLASH_BP1|SPI_FLASH_BP2)
|
||||
|
||||
#define SPI 0
|
||||
|
||||
#define PERIPHS_SPI_FLASH_C0 SPI_W0(SPI)
|
||||
#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL(SPI)
|
||||
#define PERIPHS_SPI_FLASH_CMD SPI_CMD(SPI)
|
||||
|
||||
#define SPI0_CLK_EQU_SYSCLK BIT8
|
||||
|
||||
#define PERIPHS_SPI_FLASH_USRREG (0x60000200 + 0x1c)
|
||||
|
||||
#endif // SPI_REGISTER_H_INCLUDED
|
||||
Reference in New Issue
Block a user