mirror of
https://github.com/espressif/ESP8266_RTOS_SDK.git
synced 2025-07-17 19:13:52 +08:00
refactor(hspi): Refactor hspi driver for esp8266 idf
This commit is contained in:
XiongYu
658
components/esp8266/driver/spi.c
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658
components/esp8266/driver/spi.c
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@ -0,0 +1,658 @@
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// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdio.h>
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#include <string.h>
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#include <stdint.h>
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#include "FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "esp8266/eagle_soc.h"
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#include "esp8266/spi_struct.h"
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#include "esp8266/pin_mux_register.h"
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#include "esp_libc.h"
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#include "esp_heap_caps.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "rom/ets_sys.h"
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#include "spi.h"
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#define ENTER_CRITICAL() portENTER_CRITICAL()
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#define EXIT_CRITICAL() portEXIT_CRITICAL()
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static const char *TAG = "spi";
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#define SPI_CHECK(a, str, ret_val) \
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if (!(a)) { \
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ESP_LOGE(TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
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return (ret_val); \
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}
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#define spi_intr_enable() _xt_isr_unmask(1 << ETS_SPI_INUM)
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#define spi_intr_disable() _xt_isr_mask(1 << ETS_SPI_INUM)
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#define spi_intr_register(a, b) _xt_isr_attach(ETS_SPI_INUM, (a), (b))
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// SPI interrupt status register address definition for determining the interrupt source
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#define DPORT_SPI_INT_STATUS_REG 0x3ff00020
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#define DPORT_SPI_INT_STATUS_SPI0 BIT4
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#define DPORT_SPI_INT_STATUS_SPI1 BIT7
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typedef struct {
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spi_mode_t mode;
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spi_interface_t interface;
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SemaphoreHandle_t trans_mux;
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spi_event_callback_t event_cb;
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} spi_object_t;
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static spi_object_t *spi_object[SPI_NUM_MAX] = {NULL, NULL};
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// DRAM_ATTR is required to avoid SPI array placed in flash, due to accessed from ISR
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static DRAM_ATTR spi_dev_t *const SPI[SPI_NUM_MAX] = {&SPI0, &SPI1};
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esp_err_t spi_get_clk_div(spi_host_t host, spi_clk_div_t *clk_div)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(clk_div, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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if (SPI[host]->clock.clk_equ_sysclk) {
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*clk_div = SPI_80MHz_DIV;
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}
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*clk_div = SPI[host]->clock.clkcnt_n + 1;
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return ESP_OK;
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}
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esp_err_t spi_set_clk_div(spi_host_t host, spi_clk_div_t *clk_div)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(clk_div, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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ENTER_CRITICAL();
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if (SPI_MASTER_MODE == spi_object[host]->mode) {
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if (SPI_80MHz_DIV == *clk_div) {
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switch (host) {
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case CSPI_HOST: {
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SET_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI0_CLK_EQU_SYS_CLK);
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}
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break;
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case HSPI_HOST: {
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SET_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI1_CLK_EQU_SYS_CLK);
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}
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break;
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}
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SPI[host]->clock.clk_equ_sysclk = true;
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} else {
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// Configure the IO_MUX clock (required, otherwise the clock output will be confusing)
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switch (host) {
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case CSPI_HOST: {
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CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI0_CLK_EQU_SYS_CLK);
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}
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break;
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case HSPI_HOST: {
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CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI1_CLK_EQU_SYS_CLK);
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}
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break;
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}
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// FRE(SCLK) = clk_equ_sysclk ? 80MHz : APB_CLK(80MHz) / clkdiv_pre / clkcnt
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SPI[host]->clock.clk_equ_sysclk = false;
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SPI[host]->clock.clkdiv_pre = 0;
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SPI[host]->clock.clkcnt_n = *clk_div - 1;
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// In the master mode clkcnt_h = floor((clkcnt_n+1)/2-1). In the slave mode it must be 0
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SPI[host]->clock.clkcnt_h = *clk_div / 2 - 1;
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// In the master mode clkcnt_l = clkcnt_n. In the slave mode it must be 0
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SPI[host]->clock.clkcnt_l = *clk_div - 1;
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}
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} else {
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// Slave mode must be set to 0
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SPI[host]->clock.val = 0;
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}
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EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t spi_get_intr_enable(spi_host_t host, spi_intr_enable_t *intr_enable)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(intr_enable, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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intr_enable->val = (SPI[host]->slave.val >> 5) & 0x1F;
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return ESP_OK;
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}
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esp_err_t spi_set_intr_enable(spi_host_t host, spi_intr_enable_t *intr_enable)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(intr_enable, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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ENTER_CRITICAL();
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SPI[host]->slave.rd_buf_inten = intr_enable->read_buffer;
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SPI[host]->slave.wr_buf_inten = intr_enable->write_buffer;
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SPI[host]->slave.rd_sta_inten = intr_enable->read_status;
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SPI[host]->slave.wr_sta_inten = intr_enable->write_status;
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SPI[host]->slave.trans_inten = intr_enable->trans_done;
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// Clear interrupt status register
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SPI[host]->slave.rd_buf_done = false;
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SPI[host]->slave.wr_buf_done = false;
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SPI[host]->slave.rd_sta_done = false;
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SPI[host]->slave.wr_sta_done = false;
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SPI[host]->slave.trans_done = false;
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EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t spi_get_mode(spi_host_t host, spi_mode_t *mode)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(mode, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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*mode = spi_object[host]->mode;
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return ESP_OK;
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}
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esp_err_t spi_set_mode(spi_host_t host, spi_mode_t *mode)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(mode, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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spi_object[host]->mode = *mode;
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ENTER_CRITICAL();
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// Disable flash operation mode
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SPI[host]->user.flash_mode = false;
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if (SPI_MASTER_MODE == *mode) {
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// Set to Master mode
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SPI[host]->pin.slave_mode = false;
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SPI[host]->slave.slave_mode = false;
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// Master uses the entire hardware buffer to improve transmission speed
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SPI[host]->user.usr_mosi_highpart = false;
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SPI[host]->user.usr_miso_highpart = false;
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SPI[host]->user.usr_mosi = true;
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// Create hardware cs in advance
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SPI[host]->user.cs_setup = true;
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// Hysteresis to keep hardware cs
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SPI[host]->user.cs_hold = true;
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SPI[host]->user.duplex = true;
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SPI[host]->user.ck_i_edge = true;
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SPI[host]->ctrl2.mosi_delay_num = 0;
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SPI[host]->ctrl2.miso_delay_num = 1;
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} else {
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// Set to Slave mode
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SPI[host]->pin.slave_mode = true;
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SPI[host]->slave.slave_mode = true;
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SPI[host]->user.usr_miso_highpart = true;
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SPI[host]->ctrl2.mosi_delay_num = 1;
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SPI[host]->ctrl2.miso_delay_num = 0;
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SPI[host]->slave.wr_rd_sta_en = 1;
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SPI[host]->slave1.status_bitlen = 31;
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SPI[host]->slave1.status_readback = 0;
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// Put the slave's miso on the highpart, so you can only send 256bits
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// In Slave mode miso, mosi length is the same
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SPI[host]->slave1.buf_bitlen = 255;
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SPI[host]->cmd.usr = 1;
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}
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SPI[host]->user.fwrite_dual = false;
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SPI[host]->user.fwrite_quad = false;
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SPI[host]->user.fwrite_dio = false;
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SPI[host]->user.fwrite_qio = false;
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SPI[host]->ctrl.fread_dual = false;
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SPI[host]->ctrl.fread_quad = false;
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SPI[host]->ctrl.fread_dio = false;
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SPI[host]->ctrl.fread_qio = false;
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SPI[host]->ctrl.fastrd_mode = true;
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EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t spi_get_interface(spi_host_t host, spi_interface_t *interface)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(interface, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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*interface = spi_object[host]->interface;
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return ESP_OK;
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}
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esp_err_t spi_set_interface(spi_host_t host, spi_interface_t *interface)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(interface, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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spi_object[host]->interface = *interface;
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ENTER_CRITICAL();
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switch (host) {
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case CSPI_HOST: {
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// Initialize SPI IO
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PIN_PULLUP_EN(PERIPHS_IO_MUX_SD_CLK_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SPICLK);
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if (interface->mosi_en) {
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PIN_PULLUP_EN(PERIPHS_IO_MUX_SD_DATA1_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, FUNC_SPID_MOSI);
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}
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if (interface->miso_en) {
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PIN_PULLUP_EN(PERIPHS_IO_MUX_SD_DATA0_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, FUNC_SPIQ_MISO);
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}
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if (interface->cs_en) {
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PIN_PULLUP_EN(PERIPHS_IO_MUX_SD_CMD_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, FUNC_SPICS0);
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}
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}
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break;
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case HSPI_HOST: {
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// Initialize HSPI IO
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PIN_PULLUP_EN(PERIPHS_IO_MUX_MTMS_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, FUNC_HSPI_CLK); //GPIO14 is SPI CLK pin (Clock)
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if (interface->mosi_en) {
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PIN_PULLUP_EN(PERIPHS_IO_MUX_MTCK_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_HSPID_MOSI); //GPIO13 is SPI MOSI pin (Master Data Out)
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}
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if (interface->miso_en) {
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PIN_PULLUP_EN(PERIPHS_IO_MUX_MTDI_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, FUNC_HSPIQ_MISO); //GPIO12 is SPI MISO pin (Master Data In)
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}
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if (interface->cs_en) {
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PIN_PULLUP_EN(PERIPHS_IO_MUX_MTDO_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_HSPI_CS0);
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}
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}
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break;
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}
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// Set the clock polarity and phase
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SPI[host]->pin.ck_idle_edge = interface->cpol;
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if (interface->cpol == interface->cpha) {
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SPI[host]->user.ck_out_edge = false;
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} else {
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SPI[host]->user.ck_out_edge = true;
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}
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// Set data bit order
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SPI[host]->ctrl.wr_bit_order = interface->bit_tx_order;
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SPI[host]->ctrl.rd_bit_order = interface->bit_rx_order;
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// Set data byte order
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SPI[host]->user.wr_byte_order = interface->byte_tx_order;
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SPI[host]->user.rd_byte_order = interface->byte_rx_order;
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EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t spi_get_dummy(spi_host_t host, uint16_t *bitlen)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(bitlen, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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if (SPI[host]->user.usr_dummy) {
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*bitlen = SPI[host]->user1.usr_dummy_cyclelen + 1;
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} else {
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*bitlen = 0;
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}
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return ESP_OK;
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}
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esp_err_t spi_set_dummy(spi_host_t host, uint16_t *bitlen)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(bitlen, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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SPI_CHECK(*bitlen <= 256, "spi dummy must be shorter than 256 bits", ESP_ERR_INVALID_ARG);
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ENTER_CRITICAL();
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if (*bitlen) {
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SPI[host]->user.usr_dummy = 1;
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SPI[host]->user1.usr_dummy_cyclelen = *bitlen - 1;
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} else {
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SPI[host]->user.usr_dummy = 0;
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}
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EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t spi_get_event_callback(spi_host_t host, spi_event_callback_t *event_cb)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(event_cb, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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*event_cb = spi_object[host]->event_cb;
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return ESP_OK;
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}
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esp_err_t spi_set_event_callback(spi_host_t host, spi_event_callback_t *event_cb)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(event_cb, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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spi_object[host]->event_cb = *event_cb;
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return ESP_OK;
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}
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esp_err_t spi_slave_get_status(spi_host_t host, uint32_t *status)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(SPI_SLAVE_MODE == spi_object[host]->mode, "this function must used by spi slave mode", ESP_FAIL);
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SPI_CHECK(status, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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ENTER_CRITICAL();
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*status = SPI[host]->wr_status;
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EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t spi_slave_set_status(spi_host_t host, uint32_t *status)
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{
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SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
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SPI_CHECK(SPI_SLAVE_MODE == spi_object[host]->mode, "this function must used by spi slave mode", ESP_FAIL);
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SPI_CHECK(status, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
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ENTER_CRITICAL();
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SPI[host]->rd_status.val = *status;
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EXIT_CRITICAL();
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return ESP_OK;
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}
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static esp_err_t spi_master_trans(spi_host_t host, spi_trans_t trans)
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{
|
||||
SPI_CHECK(trans.bits.cmd <= 16, "spi cmd must be shorter than 16 bits", ESP_ERR_INVALID_ARG);
|
||||
SPI_CHECK(trans.bits.addr <= 32, "spi addr must be shorter than 32 bits", ESP_ERR_INVALID_ARG);
|
||||
SPI_CHECK(trans.bits.mosi <= 512, "spi mosi must be shorter than 512 bits", ESP_ERR_INVALID_ARG);
|
||||
SPI_CHECK(trans.bits.miso <= 512, "spi miso must be shorter than 512 bits", ESP_ERR_INVALID_ARG);
|
||||
|
||||
int x, y;
|
||||
|
||||
// Waiting for an incomplete transfer
|
||||
while (SPI[host]->cmd.usr);
|
||||
|
||||
ENTER_CRITICAL();
|
||||
|
||||
// Set the cmd length and transfer cmd
|
||||
if (trans.bits.cmd && trans.cmd) {
|
||||
SPI[host]->user.usr_command = 1;
|
||||
SPI[host]->user2.usr_command_bitlen = trans.bits.cmd - 1;
|
||||
SPI[host]->user2.usr_command_value = *trans.cmd;
|
||||
} else {
|
||||
SPI[host]->user.usr_command = 0;
|
||||
}
|
||||
|
||||
// Set addr length and transfer addr
|
||||
if (trans.bits.addr && trans.addr) {
|
||||
SPI[host]->user.usr_addr = 1;
|
||||
SPI[host]->user1.usr_addr_bitlen = trans.bits.addr - 1;
|
||||
SPI[host]->addr = *trans.addr;
|
||||
} else {
|
||||
SPI[host]->user.usr_addr = 0;
|
||||
}
|
||||
|
||||
// Set mosi length and transmit mosi
|
||||
if (trans.bits.mosi && trans.mosi) {
|
||||
SPI[host]->user.usr_mosi = 1;
|
||||
SPI[host]->user1.usr_mosi_bitlen = trans.bits.mosi - 1;
|
||||
|
||||
for (x = 0; x < trans.bits.mosi; x += 32) {
|
||||
y = x / 32;
|
||||
SPI[host]->data_buf[y] = trans.mosi[y];
|
||||
}
|
||||
} else {
|
||||
SPI[host]->user.usr_mosi = 0;
|
||||
}
|
||||
|
||||
// Set the length of the miso
|
||||
if (trans.bits.miso && trans.miso) {
|
||||
SPI[host]->user.usr_miso = 1;
|
||||
SPI[host]->user1.usr_miso_bitlen = trans.bits.miso - 1;
|
||||
} else {
|
||||
SPI[host]->user.usr_miso = 0;
|
||||
}
|
||||
|
||||
// Call the event callback function to send a transfer start event
|
||||
if (spi_object[host]->event_cb) {
|
||||
spi_object[host]->event_cb(SPI_TRANS_START_EVENT, NULL);
|
||||
}
|
||||
|
||||
// Start transmission
|
||||
SPI[host]->cmd.usr = 1;
|
||||
|
||||
// Receive miso data
|
||||
if (trans.bits.miso && trans.miso) {
|
||||
while (SPI[host]->cmd.usr);
|
||||
|
||||
for (x = 0; x < trans.bits.miso; x += 32) {
|
||||
y = x / 32;
|
||||
trans.miso[y] = SPI[host]->data_buf[y];
|
||||
}
|
||||
}
|
||||
|
||||
EXIT_CRITICAL();
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static esp_err_t spi_slave_trans(spi_host_t host, spi_trans_t trans)
|
||||
{
|
||||
SPI_CHECK(trans.bits.cmd >= 3 && trans.bits.cmd <= 16, "spi cmd must be longer than 3 bits and shorter than 16 bits", ESP_ERR_INVALID_ARG);
|
||||
SPI_CHECK(trans.bits.addr >= 1 && trans.bits.addr <= 32, "spi addr must be longer than 1 bits and shorter than 32 bits", ESP_ERR_INVALID_ARG);
|
||||
SPI_CHECK(trans.bits.miso <= 256, "spi miso must be shorter than 256 bits", ESP_ERR_INVALID_ARG);
|
||||
SPI_CHECK(trans.bits.mosi <= 256, "spi mosi must be shorter than 256 bits", ESP_ERR_INVALID_ARG);
|
||||
|
||||
int x, y;
|
||||
ENTER_CRITICAL();
|
||||
// Set cmd length and receive cmd
|
||||
SPI[host]->user2.usr_command_bitlen = trans.bits.cmd - 1;
|
||||
|
||||
if (trans.cmd) {
|
||||
*trans.cmd = SPI[host]->user2.usr_command_value;
|
||||
}
|
||||
|
||||
// Set addr length and transfer addr
|
||||
SPI[host]->slave1.wr_addr_bitlen = trans.bits.addr - 1;
|
||||
SPI[host]->slave1.rd_addr_bitlen = trans.bits.addr - 1;
|
||||
|
||||
if (trans.addr) {
|
||||
*trans.addr = SPI[host]->addr;
|
||||
}
|
||||
|
||||
// Set the length of the miso and transfer the miso
|
||||
if (trans.bits.miso && trans.miso) {
|
||||
for (x = 0; x < trans.bits.miso; x += 32) {
|
||||
y = x / 32;
|
||||
SPI[host]->data_buf[y + 8] = trans.miso[y];
|
||||
}
|
||||
}
|
||||
|
||||
// Call the event callback function to send a transfer start event
|
||||
if (spi_object[host]->event_cb) {
|
||||
spi_object[host]->event_cb(SPI_TRANS_START_EVENT, NULL);
|
||||
}
|
||||
|
||||
// Receive mosi data
|
||||
if (trans.bits.mosi && trans.mosi) {
|
||||
for (x = 0; x < trans.bits.mosi; x += 32) {
|
||||
y = x / 32;
|
||||
trans.mosi[y] = SPI[host]->data_buf[y];
|
||||
}
|
||||
}
|
||||
|
||||
EXIT_CRITICAL();
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static esp_err_t spi_trans_static(spi_host_t host, spi_trans_t trans)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (SPI_MASTER_MODE == spi_object[host]->mode) {
|
||||
ret = spi_master_trans(host, trans);
|
||||
} else {
|
||||
ret = spi_slave_trans(host, trans);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
esp_err_t spi_trans(spi_host_t host, spi_trans_t trans)
|
||||
{
|
||||
SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
|
||||
SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
|
||||
SPI_CHECK(trans.bits.val, "trans bits is empty", ESP_ERR_INVALID_ARG);
|
||||
|
||||
int ret;
|
||||
|
||||
xSemaphoreTake(spi_object[host]->trans_mux, portMAX_DELAY);
|
||||
ret = spi_trans_static(host, trans);
|
||||
xSemaphoreGive(spi_object[host]->trans_mux);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static IRAM_ATTR void spi_intr(void *arg)
|
||||
{
|
||||
spi_host_t host;
|
||||
uint32_t trans_done;
|
||||
|
||||
if (READ_PERI_REG(DPORT_SPI_INT_STATUS_REG) & DPORT_SPI_INT_STATUS_SPI0) { // DPORT_SPI_INT_STATUS_SPI0
|
||||
trans_done = SPI0.slave.val & 0x1F;
|
||||
SPI0.slave.val &= ~0x3FF;
|
||||
host = CSPI_HOST;
|
||||
} else if (READ_PERI_REG(DPORT_SPI_INT_STATUS_REG) & DPORT_SPI_INT_STATUS_SPI1) { // DPORT_SPI_INT_STATUS_SPI1
|
||||
trans_done = SPI1.slave.val & 0x1F;
|
||||
SPI1.slave.val &= ~0x1F;
|
||||
host = HSPI_HOST;
|
||||
} else {
|
||||
return;
|
||||
}
|
||||
|
||||
if (spi_object[host]) {
|
||||
if (spi_object[host]->event_cb) {
|
||||
spi_object[host]->event_cb(SPI_TRANS_DONE_EVENT, &trans_done);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
esp_err_t spi_deinit(spi_host_t host)
|
||||
{
|
||||
SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
|
||||
SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
|
||||
|
||||
spi_intr_enable_t intr_enable;
|
||||
// Turn off the current host interrupt enable
|
||||
intr_enable.val = 0;
|
||||
spi_set_intr_enable(host, &intr_enable);
|
||||
|
||||
// Turn off the SPI interrupt if all other hosts are not initialized
|
||||
if (host == CSPI_HOST) {
|
||||
if (spi_object[HSPI_HOST] == NULL) {
|
||||
spi_intr_disable();
|
||||
}
|
||||
} else {
|
||||
if (spi_object[CSPI_HOST] == NULL) {
|
||||
spi_intr_disable();
|
||||
}
|
||||
}
|
||||
|
||||
// Waiting for all transfers to complete
|
||||
while (SPI[host]->cmd.usr);
|
||||
|
||||
// Call the event callback function to send the SPI_DEINIT event
|
||||
if (spi_object[host]->event_cb) {
|
||||
spi_object[host]->event_cb(SPI_DEINIT_EVENT, NULL);
|
||||
}
|
||||
|
||||
if (spi_object[host]->trans_mux) {
|
||||
vSemaphoreDelete(spi_object[host]->trans_mux);
|
||||
}
|
||||
free(spi_object[host]);
|
||||
spi_object[host] = NULL;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t spi_init(spi_host_t host, spi_config_t *config)
|
||||
{
|
||||
SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
|
||||
SPI_CHECK(host > CSPI_HOST, "CSPI_HOST can't support now", ESP_FAIL);
|
||||
SPI_CHECK(NULL == spi_object[host], "spi has been initialized", ESP_FAIL);
|
||||
|
||||
spi_object[host] = (spi_object_t *)malloc(sizeof(spi_object_t));
|
||||
SPI_CHECK(spi_object[host], "malloc fail", ESP_ERR_NO_MEM);
|
||||
spi_object[host]->trans_mux = xSemaphoreCreateMutex();
|
||||
if (NULL == spi_object[host]->trans_mux) {
|
||||
spi_deinit(host);
|
||||
SPI_CHECK(false, "Semaphore create fail", ESP_ERR_NO_MEM);
|
||||
}
|
||||
uint16_t dummy_bitlen = 0;
|
||||
|
||||
spi_set_event_callback(host, &config->event_cb);
|
||||
spi_set_mode(host, &config->mode);
|
||||
spi_set_interface(host, &config->interface);
|
||||
spi_set_clk_div(host, &config->clk_div);
|
||||
spi_set_dummy(host, &dummy_bitlen);
|
||||
spi_set_intr_enable(host, &config->intr_enable);
|
||||
spi_intr_register(spi_intr, NULL);
|
||||
spi_intr_enable();
|
||||
|
||||
if (spi_object[host]->event_cb) {
|
||||
spi_object[host]->event_cb(SPI_INIT_EVENT, NULL);
|
||||
}
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
Reference in New Issue
Block a user