mirror of
https://github.com/espressif/ESP8266_RTOS_SDK.git
synced 2025-05-22 01:27:11 +08:00
feat(spi_flash): Refactor SPI flash for saving IRAM
This commit is contained in:
Dong Heng
@ -211,4 +211,49 @@
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#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
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#define SPI_INT_HOLD_ENA 0x00000003
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#define SPI_INT_HOLD_ENA_S 0
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#define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
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#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
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#define SPI_ENABLE_AHB BIT17
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#define SPI_FLASH_CLK_EQU_SYSCLK BIT12
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//SPI flash command
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#define SPI_FLASH_READ BIT31
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#define SPI_FLASH_WREN BIT30
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#define SPI_FLASH_WRDI BIT29
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#define SPI_FLASH_RDID BIT28
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#define SPI_FLASH_RDSR BIT27
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#define SPI_FLASH_WRSR BIT26
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#define SPI_FLASH_PP BIT25
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#define SPI_FLASH_SE BIT24
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#define SPI_FLASH_BE BIT23
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#define SPI_FLASH_CE BIT22
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#define SPI_FLASH_RES BIT20
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#define SPI_FLASH_DPD BIT21
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#define SPI_FLASH_HPM BIT19
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//SPI address register
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#define SPI_FLASH_BYTES_LEN 24
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#define SPI_BUFF_BYTE_NUM 32
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#define IODATA_START_ADDR BIT0
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//SPI status register
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#define SPI_FLASH_BUSY_FLAG BIT0
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#define SPI_FLASH_WRENABLE_FLAG BIT1
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#define SPI_FLASH_BP0 BIT2
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#define SPI_FLASH_BP1 BIT3
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#define SPI_FLASH_BP2 BIT4
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#define SPI_FLASH_TOP_BOT_PRO_FLAG BIT5
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#define SPI_FLASH_STATUS_PRO_FLAG BIT7
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#define FLASH_WR_PROTECT (SPI_FLASH_BP0|SPI_FLASH_BP1|SPI_FLASH_BP2)
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#define SPI 0
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#define PERIPHS_SPI_FLASH_C0 SPI_W0(SPI)
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#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL(SPI)
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#define PERIPHS_SPI_FLASH_CMD SPI_CMD(SPI)
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#endif // SPI_REGISTER_H_INCLUDED
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@ -103,7 +103,7 @@ SECTIONS
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*(.init.literal)
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*(.init)
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*(.iram1 .iram1.*)
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*libspi_flash.a:spi_flash.o(.literal .text .literal.* .text.*)
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*libspi_flash.a:spi_flash_raw.o(.literal .text .literal.* .text.*)
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*(.literal .text .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.fini.literal)
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*(.fini)
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71
components/spi_flash/include/priv/esp_spi_flash_raw.h
Normal file
71
components/spi_flash/include/priv/esp_spi_flash_raw.h
Normal file
@ -0,0 +1,71 @@
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stddef.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_err.h"
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#include "esp8266/rom_functions.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum GD25Q32C_status {
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GD25Q32C_STATUS1=0,
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GD25Q32C_STATUS2,
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GD25Q32C_STATUS3,
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};
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typedef enum {
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SPI_TX = 0x1,
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SPI_RX = 0x2,
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SPI_WRSR = 0x4,
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SPI_RAW = 0x8, /*!< No wait spi idle and no read status */
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} spi_cmd_dir_t;
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typedef struct {
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uint16_t cmd;
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uint8_t cmd_len;
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uint32_t *addr;
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uint8_t addr_len;
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uint32_t *data;
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uint8_t data_len;
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uint8_t dummy_bits;
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} spi_cmd_t;
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bool spi_user_cmd_raw(esp_spi_flash_chip_t *chip, spi_cmd_dir_t mode, spi_cmd_t *p_cmd);
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uint32_t spi_flash_get_id_raw(esp_spi_flash_chip_t *chip);
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esp_err_t spi_flash_enable_qmode_raw(esp_spi_flash_chip_t *chip);
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esp_err_t spi_flash_read_status_raw(esp_spi_flash_chip_t *chip, uint32_t *status);
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esp_err_t spi_flash_write_status_raw(esp_spi_flash_chip_t *chip, uint32_t status_value);
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esp_err_t spi_flash_read_raw(esp_spi_flash_chip_t *chip, size_t src_addr, void *dest, size_t size);
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esp_err_t spi_flash_write_raw(esp_spi_flash_chip_t *chip, size_t dest_addr, const void *src, size_t size);
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esp_err_t spi_flash_erase_sector_raw(esp_spi_flash_chip_t *chip, size_t sec, size_t sec_size);
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void spi_flash_switch_to_qio_raw(void);
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#ifdef __cplusplus
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}
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#endif
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File diff suppressed because it is too large
Load Diff
290
components/spi_flash/src/spi_flash_raw.c
Normal file
290
components/spi_flash/src/spi_flash_raw.c
Normal file
@ -0,0 +1,290 @@
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include "spi_flash.h"
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#include "priv/esp_spi_flash_raw.h"
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#include "esp8266/eagle_soc.h"
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#include "esp8266/pin_mux_register.h"
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#include "driver/spi_register.h"
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void Cache_Read_Disable_2(void)
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{
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CLEAR_PERI_REG_MASK(CACHE_FLASH_CTRL_REG,CACHE_READ_EN_BIT);
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while(REG_READ(SPI_EXT2(0)) != 0) { }
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CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL,SPI_ENABLE_AHB);
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}
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void Cache_Read_Enable_2()
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{
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SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL,SPI_ENABLE_AHB);
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SET_PERI_REG_MASK(CACHE_FLASH_CTRL_REG,CACHE_READ_EN_BIT);
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}
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void Cache_Read_Enable_New(void) __attribute__((alias("Cache_Read_Enable_2")));
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uint32_t spi_flash_get_id_raw(esp_spi_flash_chip_t *chip)
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{
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uint32_t rdid = 0;
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Cache_Read_Disable();
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Wait_SPI_Idle(chip);
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0, 0); // clear regisrter
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WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_RDID);
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while(READ_PERI_REG(PERIPHS_SPI_FLASH_CMD)!=0);
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rdid = READ_PERI_REG(PERIPHS_SPI_FLASH_C0)&0xffffff;
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Cache_Read_Enable_New();
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return rdid;
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}
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esp_err_t spi_flash_read_status_raw(esp_spi_flash_chip_t *chip, uint32_t *status)
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{
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esp_err_t ret;
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Cache_Read_Disable_2();
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ret = SPI_read_status(chip, status);
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Cache_Read_Enable_2();
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return ret;
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}
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esp_err_t spi_flash_write_status_raw(esp_spi_flash_chip_t *chip, uint32_t status_value)
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{
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Cache_Read_Disable_2();
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Wait_SPI_Idle(chip);
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if (ESP_OK != SPI_write_enable(chip))
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return ESP_ERR_FLASH_OP_FAIL;
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if(ESP_OK != SPI_write_status(chip, status_value))
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return ESP_ERR_FLASH_OP_FAIL;
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Wait_SPI_Idle(chip);
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Cache_Read_Enable_2();
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return ESP_OK;
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}
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esp_err_t spi_flash_erase_sector_raw(esp_spi_flash_chip_t *chip, size_t sec, size_t sec_size)
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{
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esp_err_t ret = ESP_OK;
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Cache_Read_Disable_2();
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if (ESP_OK != SPI_write_enable(chip)) {
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ret = ESP_ERR_FLASH_OP_FAIL;
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}
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if (ESP_OK != SPI_sector_erase(chip, sec * sec_size)) {
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ret = ESP_ERR_FLASH_OP_FAIL;
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}
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Cache_Read_Enable_2();
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return ret;
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}
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esp_err_t spi_flash_enable_qmode_raw(esp_spi_flash_chip_t *chip)
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{
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esp_err_t ret;
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Cache_Read_Disable_2();
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ret = Enable_QMode(chip);
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Wait_SPI_Idle(chip);
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Cache_Read_Enable_2();
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return ret;
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}
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esp_err_t spi_flash_write_raw(esp_spi_flash_chip_t *chip, size_t dest_addr, const void *src, size_t size)
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{
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esp_err_t ret;
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Cache_Read_Disable_2();
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ret = SPI_page_program(chip, dest_addr, (void *)src, size);
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Cache_Read_Enable_2();
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return ret;
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}
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esp_err_t spi_flash_read_raw(esp_spi_flash_chip_t *chip, size_t src_addr, void *dest, size_t size)
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{
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esp_err_t ret;
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Cache_Read_Disable_2();
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ret = SPI_read_data(chip, src_addr, dest, size);
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Cache_Read_Enable_2();
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return ret;
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}
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bool spi_user_cmd_raw(esp_spi_flash_chip_t *chip, spi_cmd_dir_t mode, spi_cmd_t *p_cmd)
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{
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int idx = 0;
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// Cache Disable
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Cache_Read_Disable_2();
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//wait spi idle
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if((mode & SPI_RAW) == 0) {
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Wait_SPI_Idle(chip);
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}
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//save reg
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uint32_t io_mux_reg = READ_PERI_REG(PERIPHS_IO_MUX_CONF_U);
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uint32_t spi_clk_reg = READ_PERI_REG(SPI_CLOCK(SPI));
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uint32_t spi_ctrl_reg = READ_PERI_REG(SPI_CTRL(SPI));
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uint32_t spi_user_reg = READ_PERI_REG(SPI_USER(SPI));
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if (mode & SPI_WRSR) {
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// enable write register
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SPI_write_enable(chip);
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}
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SET_PERI_REG_MASK(SPI_USER(SPI),SPI_USR_COMMAND);
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//Disable flash operation mode
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CLEAR_PERI_REG_MASK(SPI_USER(SPI), SPI_FLASH_MODE);
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//SET SPI SEND BUFFER MODE
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CLEAR_PERI_REG_MASK(SPI_USER(SPI), SPI_USR_MISO_HIGHPART);
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//CLEAR EQU SYS CLK
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CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U,SPI0_CLK_EQU_SYS_CLK);
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SET_PERI_REG_MASK(SPI_USER(SPI), SPI_CS_SETUP|SPI_CS_HOLD|SPI_USR_COMMAND|SPI_USR_MOSI);
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CLEAR_PERI_REG_MASK(SPI_USER(SPI), SPI_FLASH_MODE);
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//CLEAR DAUL OR QUAD LINES TRANSMISSION MODE
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CLEAR_PERI_REG_MASK(SPI_CTRL(SPI), SPI_QIO_MODE|SPI_DIO_MODE|SPI_DOUT_MODE|SPI_QOUT_MODE);
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WRITE_PERI_REG(SPI_CLOCK(SPI),
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((3&SPI_CLKCNT_N)<<SPI_CLKCNT_N_S)|
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((1&SPI_CLKCNT_H)<<SPI_CLKCNT_H_S)|
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((3&SPI_CLKCNT_L)<<SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div
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//Enable fast read mode
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SET_PERI_REG_MASK(SPI_CTRL(SPI), SPI_FASTRD_MODE);
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//WAIT COMMAND DONE
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while(READ_PERI_REG(SPI_CMD(SPI)) & SPI_USR);
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//SET USER CMD
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if (p_cmd->cmd_len != 0) {
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//Max CMD length is 16 bits
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SET_PERI_REG_BITS(SPI_USER2(SPI), SPI_USR_COMMAND_BITLEN, p_cmd->cmd_len * 8 - 1, SPI_USR_COMMAND_BITLEN_S);
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//Enable CMD
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SET_PERI_REG_MASK(SPI_USER(SPI), SPI_USR_COMMAND);
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//LOAD CMD
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SET_PERI_REG_BITS(SPI_USER2(SPI), SPI_USR_COMMAND_VALUE, p_cmd->cmd, SPI_USR_COMMAND_VALUE_S);
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} else {
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//CLEAR CMD
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CLEAR_PERI_REG_MASK(SPI_USER(SPI), SPI_USR_COMMAND);
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SET_PERI_REG_BITS(SPI_USER2(SPI), SPI_USR_COMMAND_BITLEN, 0, SPI_USR_COMMAND_BITLEN_S);
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}
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if (p_cmd->dummy_bits != 0) {
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//SET dummy bits
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SET_PERI_REG_BITS(SPI_USER1(SPI), SPI_USR_DUMMY_CYCLELEN, p_cmd->dummy_bits - 1, SPI_USR_DUMMY_CYCLELEN_S);
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//Enable dummy
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SET_PERI_REG_MASK(SPI_USER(SPI), SPI_USR_DUMMY);
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} else {
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//CLEAR DUMMY
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SET_PERI_REG_BITS(SPI_USER1(SPI), SPI_USR_DUMMY_CYCLELEN, 0, SPI_USR_DUMMY_CYCLELEN_S);
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CLEAR_PERI_REG_MASK(SPI_USER(SPI), SPI_USR_DUMMY);
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}
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//SET USER ADDRESS
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if (p_cmd->addr_len != 0) {
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//Set addr lenght
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SET_PERI_REG_BITS(SPI_USER1(SPI), SPI_USR_ADDR_BITLEN, p_cmd->addr_len * 8 - 1, SPI_USR_ADDR_BITLEN_S);
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//Enable user address
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SET_PERI_REG_MASK(SPI_USER(SPI), SPI_USR_ADDR);
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WRITE_PERI_REG(SPI_ADDR(SPI), *p_cmd->addr);
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} else {
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//CLEAR ADDR
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CLEAR_PERI_REG_MASK(SPI_USER(SPI), SPI_USR_ADDR);
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SET_PERI_REG_BITS(SPI_USER1(SPI), SPI_USR_ADDR_BITLEN, 0, SPI_USR_ADDR_BITLEN_S);
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}
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uint32_t *value = p_cmd->data;
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if (((mode & SPI_TX) || (mode & SPI_WRSR)) && p_cmd->data_len != 0) {
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//Enable MOSI, disable MISO
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SET_PERI_REG_MASK(SPI_USER(SPI), SPI_USR_MOSI);
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CLEAR_PERI_REG_MASK(SPI_USER(SPI), SPI_USR_MISO);
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do {
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WRITE_PERI_REG((SPI_W0(SPI) + (idx << 2)), *value++);
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} while ( ++idx < (p_cmd->data_len / 4));
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SET_PERI_REG_BITS(SPI_USER1(SPI), SPI_USR_MOSI_BITLEN, ((p_cmd->data_len) * 8 - 1), SPI_USR_MOSI_BITLEN_S);
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} else if ((mode & SPI_RX) && p_cmd->data_len != 0) {
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//Enable MISO, disable MOSI
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CLEAR_PERI_REG_MASK(SPI_USER(SPI), SPI_USR_MOSI);
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SET_PERI_REG_MASK(SPI_USER(SPI), SPI_USR_MISO);
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SET_PERI_REG_BITS(SPI_USER1(SPI),SPI_USR_MISO_BITLEN, p_cmd->data_len * 8 - 1, SPI_USR_MISO_BITLEN_S);
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int fifo_idx = 0;
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do {
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WRITE_PERI_REG((SPI_W0(SPI) + (fifo_idx << 2)), 0);
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} while ( ++fifo_idx < (p_cmd->data_len / 4));
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} else {
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CLEAR_PERI_REG_MASK(SPI_USER(SPI), SPI_USR_MOSI);
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CLEAR_PERI_REG_MASK(SPI_USER(SPI), SPI_USR_MISO);
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SET_PERI_REG_BITS(SPI_USER1(SPI), SPI_USR_MISO_BITLEN, 0, SPI_USR_MISO_BITLEN_S);
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SET_PERI_REG_BITS(SPI_USER1(SPI), SPI_USR_MOSI_BITLEN, 0, SPI_USR_MOSI_BITLEN_S);
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}
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//Start command
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SET_PERI_REG_MASK(SPI_CMD(SPI), SPI_USR);
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while (READ_PERI_REG(SPI_CMD(SPI)) & SPI_USR);
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if (mode & SPI_RX) {
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do {
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*p_cmd->data ++ = READ_PERI_REG(SPI_W0(SPI) + (idx << 2));
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} while (++idx < (p_cmd->data_len / 4));
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}
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//recover
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WRITE_PERI_REG(PERIPHS_IO_MUX_CONF_U,io_mux_reg);
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WRITE_PERI_REG(SPI_CTRL(SPI),spi_ctrl_reg);
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WRITE_PERI_REG(SPI_CLOCK(SPI),spi_clk_reg);
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WRITE_PERI_REG(SPI_USER(SPI),spi_user_reg);
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if((mode & SPI_RAW) == 0) {
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Wait_SPI_Idle(chip);
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}
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//enable icache
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Cache_Read_Enable_2();
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return true;
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}
|
||||
|
||||
void spi_flash_switch_to_qio_raw(void)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_QIO_MODE
|
||||
|SPI_QOUT_MODE
|
||||
|SPI_DIO_MODE
|
||||
|SPI_DOUT_MODE
|
||||
|SPI_FASTRD_MODE);
|
||||
|
||||
SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_QIO_MODE | SPI_FASTRD_MODE);
|
||||
}
|
||||
Reference in New Issue
Block a user