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Merge branch 'feature/clean_up_driver' into 'master'

Browse Source 
Driver code clean up

See merge request
This commit is contained in:
Wu Jian Gang
2018-05-23 18:09:48 +08:00
parent feb22160cc 3c560f678a
commit 9daf22b07b
13 changed files with 617 additions and 619 deletions

93
components/esp8266/driver/gpio.c

@ -1,38 +1,33 @@
/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp_common.h"
#include "freertos/portmacro.h"
#include <stdint.h>
#include "esp8266/eagle_soc.h"
#include "esp8266/pin_mux_register.h"
#include "FreeRTOS.h"
#include "gpio.h"
void gpio_config(GPIO_ConfigTypeDef *pGPIOConfig)
void gpio_config(GPIO_ConfigTypeDef* pGPIOConfig)
{
uint16 gpio_pin_mask = pGPIOConfig->GPIO_Pin;
uint32 io_reg;
uint8 io_num = 0;
uint32 pin_reg;
uint16_t gpio_pin_mask = pGPIOConfig->GPIO_Pin;
uint32_t io_reg;
uint8_t io_num = 0;
uint32_t pin_reg;
if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Input) {
GPIO_AS_INPUT(gpio_pin_mask);
@ -94,7 +89,7 @@ void gpio_config(GPIO_ConfigTypeDef *pGPIOConfig)
* writes is significant, calling code should divide a single call
* into multiple calls.
*/
void gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, uint32 disable_mask)
void gpio_output_conf(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask)
{
GPIO_REG_WRITE(GPIO_OUT_W1TS_ADDRESS, set_mask);
GPIO_REG_WRITE(GPIO_OUT_W1TC_ADDRESS, clear_mask);
@ -105,7 +100,7 @@ void gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, ui
/*
* Sample the value of GPIO input pins and returns a bitmask.
*/
uint32 gpio_input_get(void)
uint32_t gpio_input_get(void)
{
return GPIO_REG_READ(GPIO_IN_ADDRESS);
}
@ -121,7 +116,7 @@ uint32 gpio_input_get(void)
* application-specific handler may wish to use gpio_intr_pending
* to check for any additional pending interrupts before it returns.
*/
void gpio_intr_handler_register(void *fn, void *arg)
void gpio_intr_handler_register(void* fn, void* arg)
{
_xt_isr_attach(ETS_GPIO_INUM, fn, arg);
}
@ -129,9 +124,9 @@ void gpio_intr_handler_register(void *fn, void *arg)
/*
only highlevel and lowlevel intr can use for wakeup
*/
void gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state)
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state)
{
uint32 pin_reg;
uint32_t pin_reg;
if ((intr_state == GPIO_PIN_INTR_LOLEVEL) || (intr_state == GPIO_PIN_INTR_HILEVEL)) {
portENTER_CRITICAL();
@ -148,8 +143,8 @@ void gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state)
void gpio_pin_wakeup_disable(void)
{
uint8 i;
uint32 pin_reg;
uint8_t i;
uint32_t pin_reg;
for (i = 0; i < GPIO_PIN_COUNT; i++) {
pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(i));
@ -163,9 +158,9 @@ void gpio_pin_wakeup_disable(void)
}
}
void gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state)
void gpio_pin_intr_state_set(uint32_t i, GPIO_INT_TYPE intr_state)
{
uint32 pin_reg;
uint32_t pin_reg;
portENTER_CRITICAL();
@ -180,34 +175,34 @@ void gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state)
void gpio16_output_conf(void)
{
WRITE_PERI_REG(PAD_XPD_DCDC_CONF,
(READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32)0x1); // mux configuration for XPD_DCDC to output rtc_gpio0
(READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32_t)0x1); // mux configuration for XPD_DCDC to output rtc_gpio0
WRITE_PERI_REG(RTC_GPIO_CONF,
(READ_PERI_REG(RTC_GPIO_CONF) & (uint32)0xfffffffe) | (uint32)0x0); //mux configuration for out enable
(READ_PERI_REG(RTC_GPIO_CONF) & (uint32_t)0xfffffffe) | (uint32_t)0x0); //mux configuration for out enable
WRITE_PERI_REG(RTC_GPIO_ENABLE,
(READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe) | (uint32)0x1); //out enable
(READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32_t)0xfffffffe) | (uint32_t)0x1); //out enable
}
void gpio16_output_set(uint8 value)
void gpio16_output_set(uint8_t value)
{
WRITE_PERI_REG(RTC_GPIO_OUT,
(READ_PERI_REG(RTC_GPIO_OUT) & (uint32)0xfffffffe) | (uint32)(value & 1));
(READ_PERI_REG(RTC_GPIO_OUT) & (uint32_t)0xfffffffe) | (uint32_t)(value & 1));
}
void gpio16_input_conf(void)
{
WRITE_PERI_REG(PAD_XPD_DCDC_CONF,
(READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32)0x1); // mux configuration for XPD_DCDC and rtc_gpio0 connection
(READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32_t)0x1); // mux configuration for XPD_DCDC and rtc_gpio0 connection
WRITE_PERI_REG(RTC_GPIO_CONF,
(READ_PERI_REG(RTC_GPIO_CONF) & (uint32)0xfffffffe) | (uint32)0x0); //mux configuration for out enable
(READ_PERI_REG(RTC_GPIO_CONF) & (uint32_t)0xfffffffe) | (uint32_t)0x0); //mux configuration for out enable
WRITE_PERI_REG(RTC_GPIO_ENABLE,
READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe); //out disable
READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32_t)0xfffffffe); //out disable
}
uint8 gpio16_input_get(void)
uint8_t gpio16_input_get(void)
{
return (uint8)(READ_PERI_REG(RTC_GPIO_IN_DATA) & 1);
return (uint8_t)(READ_PERI_REG(RTC_GPIO_IN_DATA) & 1);
}

69
components/esp8266/driver/hw_timer.c

@ -1,36 +1,33 @@
/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp_common.h"
#include "freertos/portmacro.h"
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include "esp8266/ets_sys.h"
#include "esp8266/eagle_soc.h"
#include "esp8266/timer_register.h"
#include "FreeRTOS.h"
#define US_TO_RTC_TIMER_TICKS(t) \
((t) ? \
(((t) > 0x35A) ? \
(((t) >> 2) * ((APB_CLK_FREQ >> 4) / 250000) + ((t)&0x3) * ((APB_CLK_FREQ >> 4) / 1000000)) : \
(((t) *(APB_CLK_FREQ>>4)) / 1000000)) : \
0)
0)
#define FRC1_ENABLE_TIMER BIT7
#define FRC1_AUTO_LOAD BIT6
@ -52,9 +49,9 @@ static void (* user_hw_timer_cb)(void) = NULL;
bool frc1_auto_load = false;
static void hw_timer_isr_cb(void *arg)
static void hw_timer_isr_cb(void* arg)
{
if(frc1_auto_load == false ) {
if (frc1_auto_load == false) {
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
DIVDED_BY_16 | TM_EDGE_INT);
}
@ -66,12 +63,13 @@ static void hw_timer_isr_cb(void *arg)
void hw_timer_disarm(void)
{
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,0);
RTC_REG_WRITE(FRC1_CTRL_ADDRESS, 0);
}
void hw_timer_arm(uint32 val ,bool req)
void hw_timer_arm(uint32_t val, bool req)
{
frc1_auto_load = req;
if (frc1_auto_load == true) {
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
FRC1_AUTO_LOAD | DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
@ -91,6 +89,7 @@ void hw_timer_set_func(void (* user_hw_timer_cb_set)(void))
void hw_timer_init(void)
{
#if 0
if (req == 1) {
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
FRC1_AUTO_LOAD | DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
@ -110,18 +109,18 @@ void hw_timer_init(void)
#if 0
#include "hw_timer.h"
#define REG_WRITE(_r,_v) (*(volatile uint32 *)(_r)) = (_v)
#define REG_READ(_r) (*(volatile uint32 *)(_r))
#define REG_WRITE(_r,_v) (*(volatile uint32_t *)(_r)) = (_v)
#define REG_READ(_r) (*(volatile uint32_t *)(_r))
#define WDEV_NOW() REG_READ(0x3ff20c00)
uint32 tick_now2 = 0;
uint32_t tick_now2 = 0;
void hw_test_timer_cb(void)
{
static uint16 j = 0;
j++;
if ((WDEV_NOW() - tick_now2) >= 1000000) {
static uint32 idx = 1;
static uint32_t idx = 1;
tick_now2 = WDEV_NOW();
os_printf("b%u:%d\n", idx++, j);
j = 0;
@ -133,7 +132,7 @@ void hw_test_timer_cb(void)
void user_init(void)
{
hw_timer_init();
hw_timer_set_func(hw_test_timer_cb,1);
hw_timer_set_func(hw_test_timer_cb, 1);
hw_timer_arm(100);
}
#endif

147
components/esp8266/driver/i2c_master.c

@ -1,40 +1,47 @@
/******************************************************************************
* Copyright 2013-2014 Espressif Systems (Wuxi)
*
* FileName: i2c_master.c
*
* Description: i2c master API
*
* Modification history:
* 2014/3/12, v1.0 create this file.
*******************************************************************************/
#include "c_types.h"
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include <stdbool.h>
#include "esp8266/ets_sys.h"
#include "esp_misc.h"
#include "gpio.h"
#include "freertos/portmacro.h"
#include "gpio.h"
#include "i2c_master.h"
LOCAL uint8 m_nLastSDA;
LOCAL uint8 m_nLastSCL;
#include "FreeRTOS.h"
static uint8_t m_nLastSDA;
static uint8_t m_nLastSCL;
/******************************************************************************
* FunctionName : i2c_master_setDC
* Description : Internal used function -
* set i2c SDA and SCL bit value for half clk cycle
* Parameters : uint8 SDA
* uint8 SCL
* Parameters : uint8_t SDA
* uint8_t SCL
* Returns : NONE
*******************************************************************************/
LOCAL void ICACHE_FLASH_ATTR
i2c_master_setDC(uint8 SDA, uint8 SCL)
static void i2c_master_setDC(uint8_t SDA, uint8_t SCL)
{
SDA &= 0x01;
SCL &= 0x01;
SDA &= 0x01;
SCL &= 0x01;
m_nLastSDA = SDA;
m_nLastSCL = SCL;
ETS_INTR_LOCK();
if ((0 == SDA) && (0 == SCL)) {
I2C_MASTER_SDA_LOW_SCL_LOW();
} else if ((0 == SDA) && (1 == SCL)) {
@ -44,6 +51,7 @@ i2c_master_setDC(uint8 SDA, uint8 SCL)
} else {
I2C_MASTER_SDA_HIGH_SCL_HIGH();
}
ETS_INTR_UNLOCK();
}
@ -52,12 +60,11 @@ i2c_master_setDC(uint8 SDA, uint8 SCL)
* Description : Internal used function -
* get i2c SDA bit value
* Parameters : NONE
* Returns : uint8 - SDA bit value
* Returns : uint8_t - SDA bit value
*******************************************************************************/
LOCAL uint8 ICACHE_FLASH_ATTR
i2c_master_getDC(void)
static uint8_t i2c_master_getDC(void)
{
uint8 sda_out;
uint8_t sda_out;
ETS_INTR_LOCK();
sda_out = GPIO_INPUT_GET(GPIO_ID_PIN(I2C_MASTER_SDA_GPIO));
ETS_INTR_UNLOCK();
@ -70,10 +77,9 @@ i2c_master_getDC(void)
* Parameters : NONE
* Returns : NONE
*******************************************************************************/
void ICACHE_FLASH_ATTR
i2c_master_init(void)
void i2c_master_init(void)
{
uint8 i;
uint8_t i;
i2c_master_setDC(1, 0);
i2c_master_wait(5);
@ -87,9 +93,9 @@ i2c_master_init(void)
// set data_cnt to max value
for (i = 0; i < 28; i++) {
i2c_master_setDC(1, 0);
i2c_master_wait(5); // sda 1, scl 0
i2c_master_wait(5); // sda 1, scl 0
i2c_master_setDC(1, 1);
i2c_master_wait(5); // sda 1, scl 1
i2c_master_wait(5); // sda 1, scl 1
}
// reset all
@ -104,8 +110,7 @@ i2c_master_init(void)
* Parameters : NONE
* Returns : NONE
*******************************************************************************/
void ICACHE_FLASH_ATTR
i2c_master_gpio_init(void)
void i2c_master_gpio_init(void)
{
ETS_GPIO_INTR_DISABLE() ;
// ETS_INTR_LOCK();
@ -132,15 +137,14 @@ i2c_master_gpio_init(void)
* Parameters : NONE
* Returns : NONE
*******************************************************************************/
void ICACHE_FLASH_ATTR
i2c_master_start(void)
void i2c_master_start(void)
{
i2c_master_setDC(1, m_nLastSCL);
i2c_master_wait(5);
i2c_master_setDC(1, 1);
i2c_master_wait(5); // sda 1, scl 1
i2c_master_wait(5); // sda 1, scl 1
i2c_master_setDC(0, 1);
i2c_master_wait(5); // sda 0, scl 1
i2c_master_wait(5); // sda 0, scl 1
}
/******************************************************************************
@ -149,36 +153,34 @@ i2c_master_start(void)
* Parameters : NONE
* Returns : NONE
*******************************************************************************/
void ICACHE_FLASH_ATTR
i2c_master_stop(void)
void i2c_master_stop(void)
{
i2c_master_wait(5);
i2c_master_setDC(0, m_nLastSCL);
i2c_master_wait(5); // sda 0
i2c_master_wait(5); // sda 0
i2c_master_setDC(0, 1);
i2c_master_wait(5); // sda 0, scl 1
i2c_master_wait(5); // sda 0, scl 1
i2c_master_setDC(1, 1);
i2c_master_wait(5); // sda 1, scl 1
i2c_master_wait(5); // sda 1, scl 1
}
/******************************************************************************
* FunctionName : i2c_master_setAck
* Description : set ack to i2c bus as level value
* Parameters : uint8 level - 0 or 1
* Parameters : uint8_t level - 0 or 1
* Returns : NONE
*******************************************************************************/
void ICACHE_FLASH_ATTR
i2c_master_setAck(uint8 level)
void i2c_master_setAck(uint8_t level)
{
i2c_master_setDC(m_nLastSDA, 0);
i2c_master_wait(5);
i2c_master_setDC(level, 0);
i2c_master_wait(5); // sda level, scl 0
i2c_master_wait(5); // sda level, scl 0
i2c_master_setDC(level, 1);
i2c_master_wait(8); // sda level, scl 1
i2c_master_wait(8); // sda level, scl 1
i2c_master_setDC(level, 0);
i2c_master_wait(5); // sda level, scl 0
i2c_master_wait(5); // sda level, scl 0
i2c_master_setDC(1, 0);
i2c_master_wait(5);
}
@ -187,12 +189,11 @@ i2c_master_setAck(uint8 level)
* FunctionName : i2c_master_getAck
* Description : confirm if peer send ack
* Parameters : NONE
* Returns : uint8 - ack value, 0 or 1
* Returns : uint8_t - ack value, 0 or 1
*******************************************************************************/
uint8 ICACHE_FLASH_ATTR
i2c_master_getAck(void)
uint8_t i2c_master_getAck(void)
{
uint8 retVal;
uint8_t retVal;
i2c_master_setDC(m_nLastSDA, 0);
i2c_master_wait(5);
i2c_master_setDC(1, 0);
@ -214,13 +215,12 @@ i2c_master_getAck(void)
* Parameters : NONE
* Returns : true : get ack ; false : get nack
*******************************************************************************/
bool ICACHE_FLASH_ATTR
i2c_master_checkAck(void)
bool i2c_master_checkAck(void)
{
if(i2c_master_getAck()){
return FALSE;
}else{
return TRUE;
if (i2c_master_getAck()) {
return false;
} else {
return true;
}
}
@ -230,19 +230,18 @@ i2c_master_checkAck(void)
* Parameters : NONE
* Returns : NONE
*******************************************************************************/
void ICACHE_FLASH_ATTR
i2c_master_send_ack(void)
void i2c_master_send_ack(void)
{
i2c_master_setAck(0x0);
}
/******************************************************************************
* FunctionName : i2c_master_send_nack
* Description : response nack
* Parameters : NONE
* Returns : NONE
*******************************************************************************/
void ICACHE_FLASH_ATTR
i2c_master_send_nack(void)
void i2c_master_send_nack(void)
{
i2c_master_setAck(0x1);
}
@ -251,24 +250,23 @@ i2c_master_send_nack(void)
* FunctionName : i2c_master_readByte
* Description : read Byte from i2c bus
* Parameters : NONE
* Returns : uint8 - readed value
* Returns : uint8_t - readed value
*******************************************************************************/
uint8 ICACHE_FLASH_ATTR
i2c_master_readByte(void)
uint8_t i2c_master_readByte(void)
{
uint8 retVal = 0;
uint8 k, i;
uint8_t retVal = 0;
uint8_t k, i;
i2c_master_wait(5);
i2c_master_setDC(m_nLastSDA, 0);
i2c_master_wait(5); // sda 1, scl 0
i2c_master_wait(5); // sda 1, scl 0
for (i = 0; i < 8; i++) {
i2c_master_wait(5);
i2c_master_setDC(1, 0);
i2c_master_wait(5); // sda 1, scl 0
i2c_master_wait(5); // sda 1, scl 0
i2c_master_setDC(1, 1);
i2c_master_wait(5); // sda 1, scl 1
i2c_master_wait(5); // sda 1, scl 1
k = i2c_master_getDC();
i2c_master_wait(5);
@ -282,7 +280,7 @@ i2c_master_readByte(void)
}
i2c_master_setDC(1, 0);
i2c_master_wait(5); // sda 1, scl 0
i2c_master_wait(5); // sda 1, scl 0
return retVal;
}
@ -290,14 +288,13 @@ i2c_master_readByte(void)
/******************************************************************************
* FunctionName : i2c_master_writeByte
* Description : write wrdata value(one byte) into i2c
* Parameters : uint8 wrdata - write value
* Parameters : uint8_t wrdata - write value
* Returns : NONE
*******************************************************************************/
void ICACHE_FLASH_ATTR
i2c_master_writeByte(uint8 wrdata)
void i2c_master_writeByte(uint8_t wrdata)
{
uint8 dat;
sint8 i;
uint8_t dat;
int8_t i;
i2c_master_wait(5);

170
components/esp8266/driver/spi_interface.c

@ -1,30 +1,31 @@
/**
* spi_interface.c
*
* Defines and Macros for the SPI.
*
* Copyright @ 2015 Espressif System Co., Ltd.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are NOT permitted except as agreed by
* Espressif System Co., Ltd.
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/**
* @file spi_interface.c
* @brief Defines and Macros for the SPI.
*/
#include "spi_interface.h"
#include "esp8266/eagle_soc.h"
#include <stdint.h>
#include "esp8266/ets_sys.h"
#include "esp8266/pin_mux_register.h"
#include "esp_libc.h"
#include "freertos/portmacro.h"
#include "spi_interface.h"
#include "FreeRTOS.h"
//*****************************************************************************
//
// Make sure all of the definitions in this header have a C binding.
@ -38,7 +39,7 @@ extern "C"
// Show the spi registers.
#define SHOWDEBUG
void __ShowRegValue(const char * func, uint32_t line)
void __ShowRegValue(const char* func, uint32_t line)
{
#ifndef SHOWDEBUG
int i;
@ -63,6 +64,7 @@ void __ShowRegValue(const char * func, uint32_t line)
printf(" ADDR[0x%08x],Value[0x%08x]\r\n", regAddr, READ_PERI_REG(regAddr));
regAddr += 4;
}
#endif
}
@ -73,32 +75,36 @@ void __ShowRegValue(const char * func, uint32_t line)
* @brief Based on pAttr initialize SPI module.
*
*/
void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
void SPIInit(SpiNum spiNum, SpiAttr* pAttr)
{
if ((spiNum > SpiNum_HSPI)
|| (NULL == pAttr)) {
|| (NULL == pAttr)) {
return;
}
// SPI_CPOL & SPI_CPHA
switch (pAttr->subMode) {
case SpiSubMode_1:
CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
break;
case SpiSubMode_2:
SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
break;
case SpiSubMode_3:
SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE);
break;
case SpiSubMode_0:
default:
CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE);
// To do nothing
break;
case SpiSubMode_1:
CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
break;
case SpiSubMode_2:
SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
break;
case SpiSubMode_3:
SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE);
break;
case SpiSubMode_0:
default:
CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE);
// To do nothing
break;
}
// SPI bit order
@ -121,10 +127,12 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
// SPI mode type
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE);
// SPI Send buffer
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART );// By default slave send buffer C0-C7
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART); // By default slave send buffer C0-C7
// SPI Speed
if (1 < (pAttr->speed)) {
CLEAR_PERI_REG_MASK(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK);
if (spiNum == SpiNum_HSPI) {
CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI1_CLK_EQU_SYS_CLK);
}
@ -136,8 +144,9 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
} else {
WRITE_PERI_REG(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK); // 80Mhz speed
}
// By default format:CMD+ADDR+DATA
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI );
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI);
//delay num
SET_PERI_REG_MASK(SPI_CTRL2(spiNum), ((0x1 & SPI_MISO_DELAY_NUM) << SPI_MISO_DELAY_NUM_S));
@ -183,11 +192,12 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
* @brief Set address value by master mode.
*
*/
void ICACHE_FLASH_ATTR SPIMasterCfgAddr(SpiNum spiNum, uint32_t addr)
void SPIMasterCfgAddr(SpiNum spiNum, uint32_t addr)
{
if (spiNum > SpiNum_HSPI) {
return;
}
// Set address
WRITE_PERI_REG(SPI_ADDR(spiNum), addr);
}
@ -196,11 +206,12 @@ void ICACHE_FLASH_ATTR SPIMasterCfgAddr(SpiNum spiNum, uint32_t addr)
* @brief Set command value by master mode.
*
*/
void ICACHE_FLASH_ATTR SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd)
void SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd)
{
if (spiNum > SpiNum_HSPI) {
return;
}
// SPI_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1,
// bit15-0 is cmd value.
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_VALUE, cmd, SPI_USR_COMMAND_VALUE_S);
@ -210,16 +221,20 @@ void ICACHE_FLASH_ATTR SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd)
* @brief Send data to slave.
*
*/
int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
int SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
{
char idx = 0;
if ((spiNum > SpiNum_HSPI)
|| (NULL == pInData)
|| (64 < pInData->dataLen)) {
|| (NULL == pInData)
|| (64 < pInData->dataLen)) {
return -1;
}
uint32_t *value = pInData->data;
uint32_t* value = pInData->data;
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Set command by user.
if (pInData->cmdLen != 0) {
// Max command length 16 bits.
@ -234,6 +249,7 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
0, SPI_USR_COMMAND_BITLEN_S);
}
// Set Address by user.
if (pInData->addrLen == 0) {
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
@ -243,6 +259,7 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
if (NULL == pInData->addr) {
return -1;
}
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
((pInData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S);
// Enable address
@ -250,18 +267,22 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
// Load address
SPIMasterCfgAddr(spiNum, *pInData->addr);
}
// Set data by user.
if (pInData->dataLen != 0) {
if (NULL == value) {
return -1;
}
// Enable MOSI
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
// Load send buffer
do {
WRITE_PERI_REG((SPI_W0(spiNum) + (idx << 2)), *value++);
} while (++idx < (pInData->dataLen / 4));
// Set data send buffer length.Max data length 64 bytes.
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN, ((pInData->dataLen << 3) - 1), SPI_USR_MOSI_BITLEN_S);
} else {
@ -270,6 +291,7 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN,
0, SPI_USR_MOSI_BITLEN_S);
}
// Start send data
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
@ -281,16 +303,19 @@ int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
* @brief Receive data from slave.
*
*/
int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
int SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
{
char idx = 0;
if ((spiNum > SpiNum_HSPI)
|| (NULL == pOutData)) {
|| (NULL == pOutData)) {
return -1;
}
uint32_t *value = pOutData->data;
uint32_t* value = pOutData->data;
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Set command by user.
if (pOutData->cmdLen != 0) {
// Max command length 16 bits.
@ -305,6 +330,7 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
0, SPI_USR_COMMAND_BITLEN_S);
}
// Set Address by user.
if (pOutData->addrLen == 0) {
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
@ -314,6 +340,7 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
if (NULL == pOutData->addr) {
return -1;
}
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
((pOutData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S);
// Enable address
@ -321,11 +348,13 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
// Load address
SPIMasterCfgAddr(spiNum, *pOutData->addr);
}
// Set data by user.
if (pOutData->dataLen != 0) {
if (NULL == value) {
return -1;
}
// Clear MOSI enable
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
// Enable MOSI
@ -341,13 +370,16 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
//CLEAR FIFO DATA
int fifo_idx = 0;
do {
WRITE_PERI_REG(SPI_W0(spiNum) + (fifo_idx << 2), 0);
} while (++fifo_idx < (pOutData->dataLen / 4));
// Start send data
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Read data out
do {
*pOutData->data++ = READ_PERI_REG(SPI_W0(spiNum) + (idx << 2));
@ -361,15 +393,18 @@ int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
* @brief Load data to send buffer by slave mode.
*
*/
int ICACHE_FLASH_ATTR SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uint8_t outLen)
int SPISlaveSendData(SpiNum spiNum, uint32_t* pInData, uint8_t outLen)
{
if (NULL == pInData) {
return -1;
}
char i;
for (i = 0; i < outLen; ++i) {
WRITE_PERI_REG((SPI_W8(spiNum) + (i << 2)), *pInData++);
}
return 0;
}
@ -377,7 +412,7 @@ int ICACHE_FLASH_ATTR SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uint8_t
* @brief Configurate slave prepare for receive data.
*
*/
int ICACHE_FLASH_ATTR SPISlaveRecvData(SpiNum spiNum, void(*isrFunc)(void*))
int SPISlaveRecvData(SpiNum spiNum, void(*isrFunc)(void*))
{
if ((spiNum > SpiNum_HSPI)) {
return -1;
@ -390,8 +425,8 @@ int ICACHE_FLASH_ATTR SPISlaveRecvData(SpiNum spiNum, void(*isrFunc)(void*))
// Maybe enable slave transmission liston
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
//
_xt_isr_attach(ETS_SPI_INUM, isrFunc, NULL);
// ETS_SPI_INTR_ATTACH(isrFunc, NULL);
_xt_isr_attach(ETS_SPI_INUM, isrFunc, NULL);
// ETS_SPI_INTR_ATTACH(isrFunc, NULL);
// Enable isr
ETS_SPI_INTR_ENABLE();
@ -405,12 +440,14 @@ int ICACHE_FLASH_ATTR SPISlaveRecvData(SpiNum spiNum, void(*isrFunc)(void*))
* @brief Send data to slave(ESP8266 register of RD_STATUS or WR_STATUS).
*
*/
void ICACHE_FLASH_ATTR SPIMasterSendStatus(SpiNum spiNum, uint8_t data)
void SPIMasterSendStatus(SpiNum spiNum, uint8_t data)
{
if (spiNum > SpiNum_HSPI) {
return;
}
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Enable MOSI
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
@ -423,7 +460,7 @@ void ICACHE_FLASH_ATTR SPIMasterSendStatus(SpiNum spiNum, uint8_t data)
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN,
((sizeof(data) << 3) - 1), SPI_USR_MOSI_BITLEN_S);
WRITE_PERI_REG(SPI_W0(spiNum), (uint32)(data));
WRITE_PERI_REG(SPI_W0(spiNum), (uint32_t)(data));
// Start SPI
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
@ -434,13 +471,14 @@ void ICACHE_FLASH_ATTR SPIMasterSendStatus(SpiNum spiNum, uint8_t data)
* @brief Receive status register from slave(ESP8266).
*
*/
int ICACHE_FLASH_ATTR SPIMasterRecvStatus(SpiNum spiNum)
int SPIMasterRecvStatus(SpiNum spiNum)
{
if (spiNum > SpiNum_HSPI) {
return -1;
}
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
// Enable MISO
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI | SPI_USR_DUMMY | SPI_USR_ADDR);
@ -461,18 +499,19 @@ int ICACHE_FLASH_ATTR SPIMasterRecvStatus(SpiNum spiNum)
(void)(READ_PERI_REG(SPI_W0(spiNum)) & 0xff);
SHOWREG();
return (uint8)(READ_PERI_REG(SPI_W0(spiNum)) & 0xff);
return (uint8_t)(READ_PERI_REG(SPI_W0(spiNum)) & 0xff);
}
/**
* @brief Select SPI CS pin.
*
*/
void ICACHE_FLASH_ATTR SPICsPinSelect(SpiNum spiNum, SpiPinCS pinCs)
void SPICsPinSelect(SpiNum spiNum, SpiPinCS pinCs)
{
if (spiNum > SpiNum_HSPI) {
return;
}
// clear select
SET_PERI_REG_BITS(SPI_PIN(spiNum), 3, 0, 0);
SET_PERI_REG_MASK(SPI_PIN(spiNum), pinCs);
@ -482,11 +521,12 @@ void ICACHE_FLASH_ATTR SPICsPinSelect(SpiNum spiNum, SpiPinCS pinCs)
* @brief Enable SPI interrupt source.
*
*/
void ICACHE_FLASH_ATTR SPIIntEnable(SpiNum spiNum, SpiIntSrc intSrc)
void SPIIntEnable(SpiNum spiNum, SpiIntSrc intSrc)
{
if (spiNum > SpiNum_HSPI) {
return;
}
SET_PERI_REG_MASK(SPI_SLAVE(spiNum), intSrc);
}
@ -494,11 +534,12 @@ void ICACHE_FLASH_ATTR SPIIntEnable(SpiNum spiNum, SpiIntSrc intSrc)
* @brief Disable SPI interrupt source.
*
*/
void ICACHE_FLASH_ATTR SPIIntDisable(SpiNum spiNum, SpiIntSrc intSrc)
void SPIIntDisable(SpiNum spiNum, SpiIntSrc intSrc)
{
if (spiNum > SpiNum_HSPI) {
return;
}
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), intSrc);
}
@ -506,11 +547,12 @@ void ICACHE_FLASH_ATTR SPIIntDisable(SpiNum spiNum, SpiIntSrc intSrc)
* @brief Clear all of SPI interrupt source.
*
*/
void ICACHE_FLASH_ATTR SPIIntClear(SpiNum spiNum)
void SPIIntClear(SpiNum spiNum)
{
if (spiNum > SpiNum_HSPI) {
return;
}
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SpiIntSrc_TransDoneEn
| SpiIntSrc_WrStaDoneEn
| SpiIntSrc_RdStaDoneEn

145
components/esp8266/driver/uart.c

@ -1,35 +1,32 @@
/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp_common.h"
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include "esp8266/pin_mux_register.h"
#include "esp8266/uart_register.h"
#include "esp8266/rom_functions.h"
#include "esp_misc.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/queue.h"
#include "uart.h"
#include "esp8266/rom_functions.h"
enum {
UART_EVENT_RX_CHAR,
@ -37,30 +34,28 @@ enum {
};
typedef struct _os_event_ {
uint32 event;
uint32 param;
uint32_t event;
uint32_t param;
} os_event_t;
xTaskHandle xUartTaskHandle;
xQueueHandle xQueueUart;
LOCAL STATUS
uart_tx_one_char(uint8 uart, uint8 TxChar)
static STATUS uart_tx_one_char(uint8_t uart, uint8_t TxChar)
{
while (true) {
uint32 fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S);
uint32_t fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S);
if ((fifo_cnt >> UART_TXFIFO_CNT_S & UART_TXFIFO_CNT) < 126) {
break;
}
}
WRITE_PERI_REG(UART_FIFO(uart) , TxChar);
WRITE_PERI_REG(UART_FIFO(uart), TxChar);
return OK;
}
LOCAL void
uart1_write_char(char c)
static void uart1_write_char(char c)
{
if (c == '\n') {
uart_tx_one_char(UART1, '\r');
@ -71,8 +66,7 @@ uart1_write_char(char c)
}
}
LOCAL void
uart0_write_char(char c)
static void uart0_write_char(char c)
{
if (c == '\n') {
uart_tx_one_char(UART0, '\r');
@ -84,8 +78,7 @@ uart0_write_char(char c)
}
#if 0
LOCAL void
uart_rx_intr_handler_ssc(void *arg)
static void uart_rx_intr_handler_ssc(void *arg)
{
/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
* uart1 and uart0 respectively
@ -93,8 +86,8 @@ uart_rx_intr_handler_ssc(void *arg)
os_event_t e;
portBASE_TYPE xHigherPriorityTaskWoken;
uint8 RcvChar;
uint8 uart_no = 0;
uint8_t RcvChar;
uint8_t uart_no = 0;
if (UART_RXFIFO_FULL_INT_ST != (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_FULL_INT_ST)) {
return;
@ -107,12 +100,11 @@ uart_rx_intr_handler_ssc(void *arg)
e.event = UART_EVENT_RX_CHAR;
e.param = RcvChar;
xQueueSendFromISR(xQueueUart, (void *)&e, &xHigherPriorityTaskWoken);
xQueueSendFromISR(xQueueUart, (void*)&e, &xHigherPriorityTaskWoken);
portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
}
LOCAL void
uart_config(uint8 uart_no, UartDevice *uart)
static void uart_config(uint8_t uart_no, UartDevice *uart)
{
if (uart_no == UART1) {
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
@ -151,13 +143,12 @@ uart_config(uint8 uart_no, UartDevice *uart)
#endif
#if 0
LOCAL void
uart_task(void *pvParameters)
static void uart_task(void *pvParameters)
{
os_event_t e;
for (;;) {
if (xQueueReceive(xQueueUart, (void *)&e, (portTickType)portMAX_DELAY)) {
if (xQueueReceive(xQueueUart, (void*)&e, (portTickType)portMAX_DELAY)) {
switch (e.event) {
case UART_EVENT_RX_CHAR:
printf("%c", e.param);
@ -172,8 +163,7 @@ uart_task(void *pvParameters)
vTaskDelete(NULL);
}
void
uart_init(void)
void uart_init(void)
{
while (READ_PERI_REG(UART_STATUS(0)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S));
@ -197,33 +187,29 @@ uart_init(void)
xQueueUart = xQueueCreate(32, sizeof(os_event_t));
xTaskCreate(uart_task, (uint8 const *)"uTask", 512, NULL, tskIDLE_PRIORITY + 2, &xUartTaskHandle);
xTaskCreate(uart_task, (uint8_t const*)"uTask", 512, NULL, tskIDLE_PRIORITY + 2, &xUartTaskHandle);
}
#endif
//=================================================================
void
UART_SetWordLength(UART_Port uart_no, UART_WordLength len)
void UART_SetWordLength(UART_Port uart_no, UART_WordLength len)
{
SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_BIT_NUM, len, UART_BIT_NUM_S);
}
void
UART_SetStopBits(UART_Port uart_no, UART_StopBits bit_num)
void UART_SetStopBits(UART_Port uart_no, UART_StopBits bit_num)
{
SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_STOP_BIT_NUM, bit_num, UART_STOP_BIT_NUM_S);
}
void
UART_SetLineInverse(UART_Port uart_no, UART_LineLevelInverse inverse_mask)
void UART_SetLineInverse(UART_Port uart_no, UART_LineLevelInverse inverse_mask)
{
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_LINE_INV_MASK);
SET_PERI_REG_MASK(UART_CONF0(uart_no), inverse_mask);
}
void
UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode)
void UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode)
{
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_PARITY | UART_PARITY_EN);
@ -233,15 +219,13 @@ UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode)
}
}
void
UART_SetBaudrate(UART_Port uart_no, uint32 baud_rate)
void UART_SetBaudrate(UART_Port uart_no, uint32_t baud_rate)
{
uart_div_modify(uart_no, UART_CLK_FREQ / baud_rate);
}
//only when USART_HardwareFlowControl_RTS is set , will the rx_thresh value be set.
void
UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8 rx_thresh)
void UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8_t rx_thresh)
{
if (flow_ctrl & USART_HardwareFlowControl_RTS) {
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
@ -259,39 +243,33 @@ UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8 rx_thresh)
}
}
void
UART_WaitTxFifoEmpty(UART_Port uart_no) //do not use if tx flow control enabled
void UART_WaitTxFifoEmpty(UART_Port uart_no) //do not use if tx flow control enabled
{
while (READ_PERI_REG(UART_STATUS(uart_no)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S));
}
void
UART_ResetFifo(UART_Port uart_no)
void UART_ResetFifo(UART_Port uart_no)
{
SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
}
void
UART_ClearIntrStatus(UART_Port uart_no, uint32 clr_mask)
void UART_ClearIntrStatus(UART_Port uart_no, uint32_t clr_mask)
{
WRITE_PERI_REG(UART_INT_CLR(uart_no), clr_mask);
}
void
UART_SetIntrEna(UART_Port uart_no, uint32 ena_mask)
void UART_SetIntrEna(UART_Port uart_no, uint32_t ena_mask)
{
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), ena_mask);
}
void
UART_intr_handler_register(void *fn, void *arg)
void UART_intr_handler_register(void* fn, void* arg)
{
_xt_isr_attach(ETS_UART_INUM, fn, arg);
}
void
UART_SetPrintPort(UART_Port uart_no)
void UART_SetPrintPort(UART_Port uart_no)
{
if (uart_no == 1) {
os_install_putc1(uart1_write_char);
@ -300,8 +278,7 @@ UART_SetPrintPort(UART_Port uart_no)
}
}
void
UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef *pUARTConfig)
void UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef* pUARTConfig)
{
if (uart_no == UART1) {
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
@ -324,11 +301,10 @@ UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef *pUARTConfig)
UART_ResetFifo(uart_no);
}
void
UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef *pUARTIntrConf)
void UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef* pUARTIntrConf)
{
uint32 reg_val = 0;
uint32_t reg_val = 0;
UART_ClearIntrStatus(uart_no, UART_INTR_MASK);
reg_val = READ_PERI_REG(UART_CONF1(uart_no)) & ((UART_RX_FLOW_THRHD << UART_RX_FLOW_THRHD_S) | UART_RX_FLOW_EN) ;
@ -346,17 +322,16 @@ UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef *pUARTIntrConf)
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), pUARTIntrConf->UART_IntrEnMask);
}
LOCAL void
uart0_rx_intr_handler(void *para)
static void uart0_rx_intr_handler(void* para)
{
/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
* uart1 and uart0 respectively
*/
uint8 uart_no = UART0;//UartDev.buff_uart_no;
uint8 fifo_len = 0;
uint8 buf_idx = 0;
uint8_t uart_no = UART0;//UartDev.buff_uart_no;
uint8_t fifo_len = 0;
uint8_t buf_idx = 0;
uint32 uart_intr_status = READ_PERI_REG(UART_INT_ST(uart_no)) ;
uint32_t uart_intr_status = READ_PERI_REG(UART_INT_ST(uart_no)) ;
while (uart_intr_status != 0x0) {
if (UART_FRM_ERR_INT_ST == (uart_intr_status & UART_FRM_ERR_INT_ST)) {
@ -396,8 +371,7 @@ uart0_rx_intr_handler(void *para)
}
}
void
uart_init_new(void)
void uart_init_new(void)
{
UART_WaitTxFifoEmpty(UART0);
UART_WaitTxFifoEmpty(UART1);
@ -430,5 +404,4 @@ uart_init_new(void)
UART_SetBaudrate(UART0,74880);
UART_SetFlowCtrl(UART0,USART_HardwareFlowControl_None,0);
*/
}

175
components/esp8266/include/driver/gpio.h

@ -1,26 +1,16 @@
/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __GPIO_H__
#define __GPIO_H__
@ -28,6 +18,9 @@
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "esp8266/gpio_register.h"
#define ETS_GPIO_INTR_ENABLE() _xt_isr_unmask(1 << ETS_GPIO_INUM)
@ -105,8 +98,8 @@ typedef enum {
typedef enum {
GPIO_Mode_Input = 0x0, /**< GPIO mode : Input */
GPIO_Mode_Out_OD, /**< GPIO mode : Output_OD */
GPIO_Mode_Output , /**< GPIO mode : Output */
GPIO_Mode_Sigma_Delta , /**< GPIO mode : Sigma_Delta */
GPIO_Mode_Output, /**< GPIO mode : Output */
GPIO_Mode_Sigma_Delta, /**< GPIO mode : Sigma_Delta */
} GPIOMode_TypeDef;
typedef enum {
@ -115,7 +108,7 @@ typedef enum {
} GPIO_Pullup_IF;
typedef struct {
uint16 GPIO_Pin; /**< GPIO pin */
uint16_t GPIO_Pin; /**< GPIO pin */
GPIOMode_TypeDef GPIO_Mode; /**< GPIO mode */
GPIO_Pullup_IF GPIO_Pullup; /**< GPIO pullup */
GPIO_INT_TYPE GPIO_IntrType; /**< GPIO interrupt type */
@ -137,164 +130,164 @@ typedef struct {
* @{
*/
/**
/**
* @brief Set GPIO pin output level.
*
*
* @param gpio_no : The GPIO sequence number.
* @param bit_value : GPIO pin output level.
*
* @param bit_value : GPIO pin output level.
*
* @return null
*/
#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
gpio_output_conf(bit_value<<gpio_no, ((~bit_value)&0x01)<<gpio_no, 1<<gpio_no, 0)
/**
/**
* @brief Set GPIO pin output level.
*
*
* @param gpio_bits : The GPIO bit number.
* @param bit_value : GPIO pin output level.
*
* @param bit_value : GPIO pin output level.
*
* @return null
*/
#define GPIO_OUTPUT(gpio_bits, bit_value) \
if(bit_value) gpio_output_conf(gpio_bits, 0, gpio_bits, 0);\
else gpio_output_conf(0, gpio_bits, gpio_bits, 0)
/**
/**
* @brief Disable GPIO pin output.
*
*
* @param gpio_no : The GPIO sequence number.
*
*
* @return null
*/
#define GPIO_DIS_OUTPUT(gpio_no) gpio_output_conf(0, 0, 0, 1<<gpio_no)
/**
/**
* @brief Enable GPIO pin intput.
*
*
* @param gpio_bits : The GPIO bit number.
*
*
* @return null
*/
#define GPIO_AS_INPUT(gpio_bits) gpio_output_conf(0, 0, 0, gpio_bits)
/**
/**
* @brief Enable GPIO pin output.
*
*
* @param gpio_bits : The GPIO bit number.
*
*
* @return null
*/
#define GPIO_AS_OUTPUT(gpio_bits) gpio_output_conf(0, 0, gpio_bits, 0)
/**
/**
* @brief Sample the level of GPIO input.
*
*
* @param gpio_no : The GPIO sequence number.
*
* @return the level of GPIO input
*
* @return the level of GPIO input
*/
#define GPIO_INPUT_GET(gpio_no) ((gpio_input_get()>>gpio_no)&BIT(0))
/**
/**
* @brief Enable GPIO16 output.
*
*
* @param null
*
*
* @return null
*/
void gpio16_output_conf(void);
/**
/**
* @brief Set GPIO16 output level.
*
* @param uint8 value : GPIO16 output level.
*
*
* @param uint8_t value : GPIO16 output level.
*
* @return null
*/
void gpio16_output_set(uint8 value);
void gpio16_output_set(uint8_t value);
/**
/**
* @brief Enable GPIO pin intput.
*
*
* @param null
*
*
* @return null
*/
void gpio16_input_conf(void);
/**
/**
* @brief Sample the value of GPIO16 input.
*
*
* @param null
*
*
* @return the level of GPIO16 input.
*/
uint8 gpio16_input_get(void);
uint8_t gpio16_input_get(void);
/**
/**
* @brief Configure Gpio pins out or input.
*
* @param uint32 set_mask : Set the output for the high bit, the
*
* @param uint32_t set_mask : Set the output for the high bit, the
* corresponding bit is 1, the output of high,
* the corresponding bit is 0, do not change the state.
* @param uint32 set_mask : Set the output for the high bit, the
* @param uint32_t set_mask : Set the output for the high bit, the
* corresponding bit is 1, the output of low,
* the corresponding bit is 0, do not change the state.
* @param uint32 enable_mask : Enable Output
* @param uint32 disable_mask : Enable Input
* @param uint32_t enable_mask : Enable Output
* @param uint32_t disable_mask : Enable Input
*
* @return null
*/
void gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, uint32 disable_mask);
void gpio_output_conf(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
/**
* @brief Register an application-specific interrupt handler for GPIO pin interrupts.
*
*
* @param void *fn:interrupt handler for GPIO pin interrupts.
* @param void *arg:interrupt handler's arg
*
*
* @return null
*/
void gpio_intr_handler_register(void *fn, void *arg);
void gpio_intr_handler_register(void* fn, void* arg);
/**
/**
* @brief Configure GPIO wake up to light sleep,Only level way is effective.
*
* @param uint32 i : Gpio sequence number
*
* @param uint32_t i : Gpio sequence number
* @param GPIO_INT_TYPE intr_state : the level of wake up to light sleep
*
*
* @return null
*/
void gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state);
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
/**
/**
* @brief Disable GPIO wake up to light sleep.
*
*
* @param null
*
*
* @return null
*/
void gpio_pin_wakeup_disable();
/**
/**
* @brief Config interrupt types of GPIO pin.
*
* @param uint32 i : The GPIO sequence number.
*
* @param uint32_t i : The GPIO sequence number.
* @param GPIO_INT_TYPE intr_state : GPIO interrupt types.
*
*
* @return null
*/
void gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state);
void gpio_pin_intr_state_set(uint32_t i, GPIO_INT_TYPE intr_state);
/**
/**
* @brief Sample the value of GPIO input pins and returns a bitmask.
*
*
* @param null
*
* @return bitmask of GPIO pins input
*
* @return bitmask of GPIO pins input
*/
uint32 gpio_input_get(void);
uint32_t gpio_input_get(void);
/**
* @}

48
components/esp8266/include/driver/hw_timer.h

@ -1,26 +1,16 @@
/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __HW_TIMER_H__
#define __HW_TIMER_H__
@ -53,21 +43,21 @@ void hw_timer_init(void);
/**
* @brief Set a trigger timer delay to enable this timer.
*
* @param uint32 val : Timing
* @param uint32_t val : Timing
* - In autoload mode, range : 50 ~ 0x7fffff
* - In non-autoload mode, range : 10 ~ 0x7fffff
*
* @param uint8 req : 0, not autoload; 1, autoload mode.
*
* @param uint8_t req : 0, not autoload; 1, autoload mode.
*
* @return null
*/
void hw_timer_arm(uint32 val, bool req);
void hw_timer_arm(uint32_t val, bool req);
/**
* @brief disable this timer.
*
* @param null
*
*
* @return null
*/
void hw_timer_disarm(void);
@ -77,7 +67,7 @@ void hw_timer_disarm(void);
*
* For enabled timer, timer callback has to be set.
*
* @param uint32 val : Timing
* @param uint32_t val : Timing
* - In autoload mode, range : 50 ~ 0x7fffff
* - In non-autoload mode, range : 10 ~ 0x7fffff
*

91
components/esp8266/include/driver/i2c_master.h

@ -1,7 +1,22 @@
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __I2C_MASTER_H__
#define __I2C_MASTER_H__
#include "esp8266/pin_mux_register.h"
#define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_GPIO2_U
#define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_GPIO4_U
#define I2C_MASTER_SDA_GPIO 2
@ -56,20 +71,20 @@
* @{
*/
/**
/**
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
*
*
* @param null
*
*
* @return null
*/
void i2c_master_gpio_init(void);
/**
/**
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
*
*
* @param initilize I2C bus to enable i2c operations.
*
*
* @return null
*/
void i2c_master_init(void);
@ -77,83 +92,83 @@ void i2c_master_init(void);
#define i2c_master_wait os_delay_us
/**
/**
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
*
*
* @param set i2c to stop sending state.
*
*
* @return null
*/
void i2c_master_stop(void);
/**
/**
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
*
*
* @param set i2c to start sending state.
*
*
* @return null
*/
void i2c_master_start(void);
/**
/**
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
*
*
* @param set ack to i2c bus as level value.
*
*
* @return null
*/
void i2c_master_setAck(uint8 level);
void i2c_master_setAck(uint8_t level);
/**
/**
* @brief confirm if peer send ack.
*
*
* @param null
*
*
* @return null
*/
uint8 i2c_master_getAck(void);
uint8_t i2c_master_getAck(void);
/**
/**
* @brief read Byte from i2c bus.
*
*
* @param null
*
*
* @return the byte which read from i2c bus.
*/
uint8 i2c_master_readByte(void);
uint8_t i2c_master_readByte(void);
/**
/**
* @brief write wrdata value(one byte) into i2c.
*
* @param uint8 wrdata:write value
*
*
* @param uint8_t wrdata:write value
*
* @return null
*/
void i2c_master_writeByte(uint8 wrdata);
void i2c_master_writeByte(uint8_t wrdata);
/**
/**
* @brief i2c_master_checkAck.
*
*
* @param null
*
*
* @return the result of check ack
*/
bool i2c_master_checkAck(void);
/**
/**
* @brief i2c master send Ack.
*
*
* @param null
*
*
* @return null
*/
void i2c_master_send_ack(void);
/**
/**
* @brief i2c master send Nack.
*
*
* @param null
*
*
* @return null
*/
void i2c_master_send_nack(void);

69
components/esp8266/include/driver/spi_interface.h

@ -1,19 +1,17 @@
/**
* spi_interface.h
*
* Defines and Macros for the SPI.
*
* Copyright @ 2015 Espressif System Co., Ltd.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are NOT permitted except as agreed by
* Espressif System Co., Ltd.
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/**
* @file spi_interface.h
* @brief Defines and Macros for the SPI.
@ -49,8 +47,7 @@ extern "C"
* @brief Support HSPI and SPI module.
*
*/
typedef enum
{
typedef enum {
SpiNum_SPI = 0,
SpiNum_HSPI = 1,
} SpiNum;
@ -59,8 +56,7 @@ typedef enum
* @brief The SPI module can work in either master or slave mode.
*
*/
typedef enum
{
typedef enum {
SpiMode_Master = 0,
SpiMode_Slave = 1,
} SpiMode;
@ -75,8 +71,7 @@ typedef enum
* 1 0 2
* 1 1 3
*/
typedef enum
{
typedef enum {
SpiSubMode_0 = 0,
SpiSubMode_1 = 1,
SpiSubMode_2 = 2,
@ -89,8 +84,7 @@ typedef enum
* @attention Max speed 80MHz
*
*/
typedef enum
{
typedef enum {
SpiSpeed_2MHz = 40 - 1,
SpiSpeed_5MHz = 16 - 1,
SpiSpeed_10MHz = 8 - 1,
@ -102,15 +96,13 @@ typedef enum
* @brief The SPI mode working speed.
*
*/
typedef enum
{
typedef enum {
SpiBitOrder_MSBFirst = 0,
SpiBitOrder_LSBFirst = 1,
} SpiBitOrder;
// @brief SPI interrupt soource defined.
typedef enum
{
typedef enum {
SpiIntSrc_TransDoneEn = SPI_TRANS_DONE_EN,
SpiIntSrc_WrStaDoneEn = SPI_SLV_WR_STA_DONE_EN,
SpiIntSrc_RdStaDoneEn = SPI_SLV_RD_STA_DONE_EN,
@ -119,8 +111,7 @@ typedef enum
} SpiIntSrc;
// @brief SPI CS pin.
typedef enum
{
typedef enum {
SpiPinCS_0 = 0,
SpiPinCS_1 = 1,
SpiPinCS_2 = 2,
@ -129,8 +120,7 @@ typedef enum
/**
* @brief SPI attribute
*/
typedef struct
{
typedef struct {
SpiMode mode; ///< Master or slave mode
SpiSubMode subMode; ///< SPI SPI_CPOL SPI_CPHA mode
SpiSpeed speed; ///< SPI Clock
@ -140,13 +130,12 @@ typedef struct
/**
* @brief SPI attribute
*/
typedef struct
{
typedef struct {
uint16_t cmd; ///< Command value
uint8_t cmdLen; ///< Command byte length
uint32_t *addr; ///< Point to address value
uint32_t* addr; ///< Point to address value
uint8_t addrLen; ///< Address byte length
uint32_t *data; ///< Point to data buffer
uint32_t* data; ///< Point to data buffer
uint8_t dataLen; ///< Data byte length.
} SpiData;
@ -156,7 +145,7 @@ typedef struct
* @brief Print debug information.
*
*/
void __ShowRegValue(const char * func, uint32_t line);
void __ShowRegValue(const char* func, uint32_t line);
/**
* @brief Initialize SPI module.
@ -204,7 +193,7 @@ void SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd);
*
* @return int, -1:indicates failure,others indicates success.
*/
int SPIMasterSendData(SpiNum spiNum, SpiData* pInData);
int SPIMasterSendData(SpiNum spiNum, SpiData* pInData);
/**
* @brief Receive data from slave by master.
@ -217,7 +206,7 @@ void SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd);
* @return int, -1:indicates failure,others indicates success.
*
*/
int SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData);
int SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData);
/**
* @brief Load data to slave send buffer.
@ -231,7 +220,7 @@ void SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd);
*
* @return int, -1:indicates failure,others indicates success.
*/
int SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uint8_t outLen);
int SPISlaveSendData(SpiNum spiNum, uint32_t* pInData, uint8_t outLen);
/**
* @brief Receive data by slave.

57
components/esp8266/include/driver/spi_register.h

@ -1,7 +1,16 @@
/*
* Copyright (c) 2010 - 2011 Espressif System
*
*/
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef SPI_REGISTER_H_INCLUDED
#define SPI_REGISTER_H_INCLUDED
@ -35,9 +44,9 @@
#define SPI_FASTRD_MODE (BIT(13))
#define SPI_CTRL1(i) (REG_SPI_BASE(i) + 0xc)
#define SPI_CS_HOLD_DELAY 0xf
#define SPI_CS_HOLD_DELAY 0xf
#define SPI_CS_HOLD_DELAY_S 28
#define SPI_CS_HOLD_DELAY_RES 0xfff
#define SPI_CS_HOLD_DELAY_RES 0xfff
#define SPI_CS_HOLD_DELAY_RES_S 16
@ -178,26 +187,26 @@
#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
#define SPI_SLV_RDBUF_CMD_VALUE_S 0
#define SPI_W0(i) (REG_SPI_BASE(i) +0x40)
#define SPI_W1(i) (REG_SPI_BASE(i) +0x44)
#define SPI_W2(i) (REG_SPI_BASE(i) +0x48)
#define SPI_W3(i) (REG_SPI_BASE(i) +0x4C)
#define SPI_W4(i) (REG_SPI_BASE(i) +0x50)
#define SPI_W5(i) (REG_SPI_BASE(i) +0x54)
#define SPI_W6(i) (REG_SPI_BASE(i) +0x58)
#define SPI_W7(i) (REG_SPI_BASE(i) +0x5C)
#define SPI_W8(i) (REG_SPI_BASE(i) +0x60)
#define SPI_W9(i) (REG_SPI_BASE(i) +0x64)
#define SPI_W10(i) (REG_SPI_BASE(i) +0x68)
#define SPI_W11(i) (REG_SPI_BASE(i) +0x6C)
#define SPI_W12(i) (REG_SPI_BASE(i) +0x70)
#define SPI_W13(i) (REG_SPI_BASE(i) +0x74)
#define SPI_W14(i) (REG_SPI_BASE(i) +0x78)
#define SPI_W15(i) (REG_SPI_BASE(i) +0x7C)
#define SPI_W0(i) (REG_SPI_BASE(i) +0x40)
#define SPI_W1(i) (REG_SPI_BASE(i) +0x44)
#define SPI_W2(i) (REG_SPI_BASE(i) +0x48)
#define SPI_W3(i) (REG_SPI_BASE(i) +0x4C)
#define SPI_W4(i) (REG_SPI_BASE(i) +0x50)
#define SPI_W5(i) (REG_SPI_BASE(i) +0x54)
#define SPI_W6(i) (REG_SPI_BASE(i) +0x58)
#define SPI_W7(i) (REG_SPI_BASE(i) +0x5C)
#define SPI_W8(i) (REG_SPI_BASE(i) +0x60)
#define SPI_W9(i) (REG_SPI_BASE(i) +0x64)
#define SPI_W10(i) (REG_SPI_BASE(i) +0x68)
#define SPI_W11(i) (REG_SPI_BASE(i) +0x6C)
#define SPI_W12(i) (REG_SPI_BASE(i) +0x70)
#define SPI_W13(i) (REG_SPI_BASE(i) +0x74)
#define SPI_W14(i) (REG_SPI_BASE(i) +0x78)
#define SPI_W15(i) (REG_SPI_BASE(i) +0x7C)
#define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
#define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
#define SPI_INT_HOLD_ENA 0x00000003
#define SPI_INT_HOLD_ENA_S 0
#endif // SPI_REGISTER_H_INCLUDED

162
components/esp8266/include/driver/uart.h

@ -1,26 +1,16 @@
/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __UART_H__
#define __UART_H__
@ -29,6 +19,8 @@
extern "C" {
#endif
#include "esp8266/uart_register.h"
#define ETS_UART_INTR_ENABLE() _xt_isr_unmask(1 << ETS_UART_INUM)
#define ETS_UART_INTR_DISABLE() _xt_isr_mask(1 << ETS_UART_INUM)
#define UART_INTR_MASK 0x1ff
@ -103,15 +95,15 @@ typedef struct {
UART_ParityMode parity; // chip size in byte
UART_StopBits stop_bits;
UART_HwFlowCtrl flow_ctrl;
uint8 UART_RxFlowThresh ;
uint32 UART_InverseMask;
uint8_t UART_RxFlowThresh ;
uint32_t UART_InverseMask;
} UART_ConfigTypeDef;
typedef struct {
uint32 UART_IntrEnMask;
uint8 UART_RX_TimeOutIntrThresh;
uint8 UART_TX_FifoEmptyIntrThresh;
uint8 UART_RX_FifoFullIntrThresh;
uint32_t UART_IntrEnMask;
uint8_t UART_RX_TimeOutIntrThresh;
uint8_t UART_TX_FifoEmptyIntrThresh;
uint8_t UART_RX_FifoFullIntrThresh;
} UART_IntrConfTypeDef;
//=======================================
@ -132,149 +124,149 @@ typedef struct {
* @{
*/
/**
/**
* @brief Wait uart tx fifo empty, do not use it if tx flow control enabled.
*
*
* @param UART_Port uart_no:UART0 or UART1
*
*
* @return null
*/
void UART_WaitTxFifoEmpty(UART_Port uart_no); //do not use if tx flow control enabled
/**
/**
* @brief Clear uart tx fifo and rx fifo.
*
*
* @param UART_Port uart_no : UART0 or UART1
*
*
* @return null
*/
void UART_ResetFifo(UART_Port uart_no);
/**
/**
* @brief Clear uart interrupt flags.
*
*
* @param UART_Port uart_no : UART0 or UART1
* @param uint32 clr_mask : To clear the interrupt bits
*
* @param uint32_t clr_mask : To clear the interrupt bits
*
* @return null
*/
void UART_ClearIntrStatus(UART_Port uart_no, uint32 clr_mask);
void UART_ClearIntrStatus(UART_Port uart_no, uint32_t clr_mask);
/**
/**
* @brief Enable uart interrupts .
*
*
* @param UART_Port uart_no : UART0 or UART1
* @param uint32 ena_mask : To enable the interrupt bits
*
* @param uint32_t ena_mask : To enable the interrupt bits
*
* @return null
*/
void UART_SetIntrEna(UART_Port uart_no, uint32 ena_mask);
void UART_SetIntrEna(UART_Port uart_no, uint32_t ena_mask);
/**
/**
* @brief Register an application-specific interrupt handler for Uarts interrupts.
*
*
* @param void *fn : interrupt handler for Uart interrupts.
* @param void *arg : interrupt handler's arg.
*
*
* @return null
*/
void UART_intr_handler_register(void *fn, void *arg);
void UART_intr_handler_register(void* fn, void* arg);
/**
/**
* @brief Config from which serial output printf function.
*
*
* @param UART_Port uart_no : UART0 or UART1
*
*
* @return null
*/
void UART_SetPrintPort(UART_Port uart_no);
/**
/**
* @brief Config Common parameters of serial ports.
*
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_ConfigTypeDef *pUARTConfig : parameters structure
*
*
* @return null
*/
void UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef *pUARTConfig);
void UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef* pUARTConfig);
/**
/**
* @brief Config types of uarts.
*
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_IntrConfTypeDef *pUARTIntrConf : parameters structure
*
*
* @return null
*/
void UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef *pUARTIntrConf);
void UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef* pUARTIntrConf);
/**
/**
* @brief Config the length of the uart communication data bits.
*
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_WordLength len : the length of the uart communication data bits
*
*
* @return null
*/
void UART_SetWordLength(UART_Port uart_no, UART_WordLength len);
/**
/**
* @brief Config the length of the uart communication stop bits.
*
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_StopBits bit_num : the length uart communication stop bits
*
*
* @return null
*/
void UART_SetStopBits(UART_Port uart_no, UART_StopBits bit_num);
/**
/**
* @brief Configure whether to open the parity.
*
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_ParityMode Parity_mode : the enum of uart parity configuration
*
*
* @return null
*/
void UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode) ;
/**
/**
* @brief Configure the Baud rate.
*
*
* @param UART_Port uart_no : UART0 or UART1
* @param uint32 baud_rate : the Baud rate
*
* @param uint32_t baud_rate : the Baud rate
*
* @return null
*/
void UART_SetBaudrate(UART_Port uart_no, uint32 baud_rate);
void UART_SetBaudrate(UART_Port uart_no, uint32_t baud_rate);
/**
/**
* @brief Configure Hardware flow control.
*
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_HwFlowCtrl flow_ctrl : Hardware flow control mode
* @param uint8 rx_thresh : threshold of Hardware flow control
*
* @param uint8_t rx_thresh : threshold of Hardware flow control
*
* @return null
*/
void UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8 rx_thresh);
void UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8_t rx_thresh);
/**
/**
* @brief Configure trigging signal of uarts.
*
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_LineLevelInverse inverse_mask : Choose need to flip the IO
*
*
* @return null
*/
void UART_SetLineInverse(UART_Port uart_no, UART_LineLevelInverse inverse_mask) ;
/**
/**
* @brief An example illustrates how to configure the serial port.
*
*
* @param null
*
*
* @return null
*/
void uart_init_new(void);

6
components/esp8266/include/esp8266/eagle_soc.h

@ -25,6 +25,8 @@
#ifndef _EAGLE_SOC_H_
#define _EAGLE_SOC_H_
#include <stdint.h>
//Register Bits{{
#define BIT31 0x80000000
#define BIT30 0x40000000
@ -64,8 +66,8 @@
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#define READ_PERI_REG(addr) (*((volatile uint32 *)ETS_UNCACHED_ADDR(addr)))
#define WRITE_PERI_REG(addr, val) (*((volatile uint32 *)ETS_UNCACHED_ADDR(addr))) = (uint32)(val)
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg) & (~(mask))))
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg) | (mask)))
#define GET_PERI_REG_BITS(reg, hipos, lowpos) ((READ_PERI_REG(reg) >> (lowpos)) & ((1 << ((hipos) - (lowpos) + 1)) - 1))

4
components/esp8266/include/esp8266/ets_sys.h

@ -25,6 +25,8 @@
#ifndef __ETS_SYS_H__
#define __ETS_SYS_H__
#include <stdint.h>
/* interrupt related */
#define ETS_SPI_INUM 2
#define ETS_GPIO_INUM 4
@ -35,7 +37,7 @@
#define ETS_FRC_TIMER1_INUM 9
extern char NMIIrqIsOn;
extern uint32 WDEV_INTEREST_EVENT;
extern uint32_t WDEV_INTEREST_EVENT;
#define INT_ENA_WDEV 0x3ff20c18
#define WDEV_TSF0_REACH_INT (BIT(27))