feat(freertos): Simplify xtensa platform code

All normal ISRs are called by "_xt_isr_handler".

components/esp8266/include/driver/soc.h

@@ -20,6 +20,7 @@
 extern "C" {
 #endif
 
+#define ETS_INT_MASK    0x00003FFF
 #define ESP_TICKS_MAX   UINT32_MAX
 
 typedef uint32_t esp_tick_t;
@@ -63,6 +64,70 @@ static inline void soc_restore_local_irq(esp_irqflag_t flag)
     );
 }
 
+static inline void soc_set_ccompare(uint32_t ticks)
+{
+    __asm__ __volatile__(
+            "wsr    %0, ccompare0\n"
+            : 
+            : "a"(ticks)
+            : "memory"
+    );   
+}
+
+static inline uint32_t soc_get_ccompare(void)
+{
+    uint32_t ticks;
+
+    __asm__ __volatile__(
+            "rsr    %0, ccompare0\n"
+            : "=a"(ticks)
+            :
+            : "memory"
+    );
+
+    return ticks;
+}
+
+static inline uint32_t soc_get_ccount(void)
+{
+    uint32_t ticks;
+
+    __asm__ __volatile__(
+            "rsr    %0, ccount\n"
+            : "=a"(ticks)
+            :
+            : "memory"
+    );
+
+    return ticks;
+}
+
+static inline void soc_clear_int_mask(uint32_t mask)
+{
+    __asm__ __volatile__(
+            "wsr    %0, intclear\n"
+            : 
+            : "a"(mask)
+            : "memory"
+    );   
+}
+
+static inline uint32_t soc_get_int_mask(void)
+{
+    uint32_t mask, enable;
+
+    __asm__ __volatile__(
+            "rsr    %0, interrupt\n"
+            "rsr    %1, intenable\n"
+            "rsync\n"
+            : "=a"(mask), "=a"(enable)
+            :
+            : "memory"
+    );
+
+    return mask & enable & ETS_INT_MASK;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/esp8266/include/esp8266/eagle_soc.h

@@ -26,6 +26,7 @@
 #define _EAGLE_SOC_H_
 
 #include <stdint.h>
+#include "driver/soc.h"
 
 /* IO definitions (access restrictions to peripheral registers) */
 

components/esp8266/include/rom/ets_sys.h

@@ -42,6 +42,7 @@ extern "C" {
 #define ETS_SOFT_INUM       7
 #define ETS_WDT_INUM        8
 #define ETS_FRC_TIMER1_INUM 9
+#define ETS_INT_MAX         14
 
 extern char NMIIrqIsOn;
 extern uint32_t WDEV_INTEREST_EVENT;