Merge branch 'feature/add_throughput_mode' into 'master'

Add full icache mode

See merge request sdk/ESP8266_RTOS_SDK!352

components/bootloader/subproject/main/esp8266.bootloader.ld

@@ -16,7 +16,7 @@ MEMORY
   dram_seg  :    org = 0x3FFE8000, len = 0x18000
 
   /* Functions which are critical should be put in this segment. */
-  iram_seg  :    org = 0x40100000, len = 0xC000
+  iram_seg  :    org = 0x40100000, len = 0x8000
 }
 
 /*  Default entry point:  */

components/esp8266/Kconfig

@@ -28,6 +28,13 @@ config NEWLIB_STDOUT_LINE_ENDING_CR
     bool "CR"
 endchoice
 
+config SOC_FULL_ICACHE
+    bool "Enable full cache mode"
+    default n
+    help
+        Enable this option, full 32 KB iram instead of 16 KB iram will be used as icache, so the heap use can use
+        may reduce a lot.
+
 endmenu
 
 menu WIFI

components/esp8266/include/esp8266/rom_functions.h

@@ -33,5 +33,6 @@ int SPI_read_status(esp_spi_flash_chip_t *chip, uint32_t *status);
 int Enable_QMode(esp_spi_flash_chip_t *chip);
 
 void Cache_Read_Disable();
+void Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v);
 
 #endif

components/esp8266/lib/VERSION

@@ -1,7 +1,7 @@
 gwen:
     crypto:     8943c89
     espnow:     8943c89
-    core:       2f2b0ef
+    core:       f4f0d3d
     net80211:   80fc165
     pp:         06e0988
     pwm:        0181338

components/esp8266/source/chip_boot.c

@@ -52,9 +52,8 @@ void chip_boot(size_t start_addr, size_t map)
 
     extern esp_spi_flash_chip_t flashchip;
     extern void phy_get_bb_evm(void);
-    extern void cache_init(uint32_t , uint32_t, uint32_t);
+    extern void cache_init(uint8_t);
     extern void user_spi_flash_dio_to_qio_pre_init(void);
-    extern int esp_get_boot_param(uint32_t, uint32_t, void *, uint32_t);
 
     phy_get_bb_evm();
 
@@ -93,7 +92,7 @@ void chip_boot(size_t start_addr, size_t map)
     SET_PERI_REG_BITS(PERIPHS_SPI_FLASH_CTRL, 0xfff, freqbits, 0);
 
     ESP_EARLY_LOGD(TAG, "SPI flash cache map is %d\n", map);
-    cache_init(map, 0, 0);
+    cache_init(map);
 
     if (fhdr.spi_mode == ESP_IMAGE_SPI_MODE_QIO) {
         ESP_EARLY_LOGD(TAG, "SPI flash enable QIO mode\n");

components/esp8266/source/esp_cache.c

@@ -0,0 +1,39 @@
+// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "sdkconfig.h"
+#include <stdint.h>
+#include "esp_attr.h"
+#include "esp8266/rom_functions.h"
+
+#ifdef CONFIG_SOC_FULL_ICACHE
+#define SOC_CACHE_SIZE 1 // 32KB
+#else
+#define SOC_CACHE_SIZE 0 // 16KB
+#endif
+
+static uint8_t s_cache_map;
+static uint8_t s_cache_size = SOC_CACHE_SIZE;
+
+void IRAM_ATTR Cache_Read_Enable_New(void)
+{
+    Cache_Read_Enable(s_cache_map, 0, s_cache_size);
+}
+
+void cache_init(int map)
+{
+    s_cache_map = map;
+
+    Cache_Read_Enable_New();
+}

components/freertos/port/esp8266/heap_5.c

@@ -105,6 +105,8 @@
  * Note 0x80000000 is the lower address so appears in the array first.
  *
  */
+#include "sdkconfig.h"
+
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -363,8 +365,10 @@ static bool is_inited = false;
         xHeapRegions[0].pucStartAddress = ( uint8_t * )&_heap_start;
         xHeapRegions[0].xSizeInBytes = (( size_t)( 0x40000000 - (uint32_t)&_heap_start));
         
+#ifndef CONFIG_SOC_FULL_ICACHE
         xHeapRegions[1].pucStartAddress = ( uint8_t * )&_lit4_end;
         xHeapRegions[1].xSizeInBytes = (( size_t)( 0x4010C000 - (uint32_t)&_lit4_end));
+#endif
 
         is_inited = true;
         vPortDefineHeapRegions(xHeapRegions);

components/lwip/Kconfig

@@ -4,6 +4,18 @@ config LWIP_USE_IRAM
     bool "Enable lwip use iram option"
     default n
 
+config LWIP_HIGH_THROUGHPUT
+    bool "Enable lwip high throughput"
+    default n
+    select TCP_QUEUE_OOSEQ
+    select TCP_HIGH_SPEED_RETRANSMISSION
+    select SOC_FULL_ICACHE
+    help
+        Enable this option, also enable "TCP_QUEUE_OOSEQ", "TCP_HIGH_SPEED_RETRANSMISSION" and
+        "SOC_FULL_ICACHE", so lwip should cache TCP message received in disorder sequence and
+        chip should full 32 KB IRAM as icache. For these 2 reasons, the global heap user can used
+        may reduce a lot.
+
 menu "ARP"
 
 config LWIP_ARP_TABLE_SIZE
@@ -229,6 +241,12 @@ config LWIP_LOOPBACK_MAX_PBUFS
 
 menu "TCP"
 
+config TCP_HIGH_SPEED_RETRANSMISSION
+    bool "TCP high speed retransmissions"
+    default n
+    help
+        "Enable this option, TCP retransmissions time will always be set to 500ms forcely."
+
 config LWIP_MAX_ACTIVE_TCP
     int "Maximum active TCP Connections"
     range 1 32

components/lwip/lwip/src/core/tcp.c

@@ -108,8 +108,13 @@ static u16_t tcp_port = TCP_LOCAL_PORT_RANGE_START;
 
 /* Incremented every coarse grained timer shot (typically every 500 ms). */
 u32_t tcp_ticks;
+#if TCP_HIGH_SPEED_RETRANSMISSION
+static const u8_t tcp_backoff[13] =
+    { 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7};
+#else
 static const u8_t tcp_backoff[13] =
     { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7};
+#endif
  /* Times per slowtmr hits */
 static const u8_t tcp_persist_backoff[7] = { 3, 6, 12, 24, 48, 96, 120 };
 

components/lwip/lwip/src/include/lwip/priv/tcp_priv.h

@@ -114,7 +114,11 @@ err_t            tcp_process_refused_data(struct tcp_pcb *pcb);
 #define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
 
 #ifndef TCP_TMR_INTERVAL
+#if TCP_HIGH_SPEED_RETRANSMISSION
+#define TCP_TMR_INTERVAL       125  /* The TCP timer interval in milliseconds. */
+#else
 #define TCP_TMR_INTERVAL       250  /* The TCP timer interval in milliseconds. */
+#endif
 #endif /* TCP_TMR_INTERVAL */
 
 #ifndef TCP_FAST_INTERVAL

components/lwip/port/esp8266/include/lwipopts.h

@@ -62,6 +62,7 @@
 
 //#define SOCKETS_TCP_TRACE
 
+#define TCP_HIGH_SPEED_RETRANSMISSION CONFIG_TCP_HIGH_SPEED_RETRANSMISSION
 
  /*
    ------------------------------------