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https://github.com/espressif/ESP8266_RTOS_SDK.git
synced 2025-07-15 08:32:42 +08:00
feat(freertos): Reduce close NMI time
This commit is contained in:
@ -51,13 +51,9 @@ extern uint32_t WDEV_INTEREST_EVENT;
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#define ETS_NMI_LOCK() \
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#define ETS_NMI_LOCK() \
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do { \
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do { \
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char m = 10; \
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do { \
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do { \
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REG_WRITE(INT_ENA_WDEV, 0); \
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m = 10; \
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for (; m > 0; m--) {} \
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REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT); \
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REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT); \
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} while(0); \
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} while(REG_READ(INT_ENA_WDEV) != WDEV_TSF0_REACH_INT); \
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} while (0)
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} while (0)
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#define ETS_NMI_UNLOCK() \
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#define ETS_NMI_UNLOCK() \
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@ -68,13 +64,9 @@ extern uint32_t WDEV_INTEREST_EVENT;
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#define ETS_INTR_LOCK() do { \
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#define ETS_INTR_LOCK() do { \
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if (NMIIrqIsOn == 0) { \
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if (NMIIrqIsOn == 0) { \
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vPortEnterCritical(); \
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vPortEnterCritical(); \
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char m = 10; \
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do { \
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do { \
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REG_WRITE(INT_ENA_WDEV, 0); \
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m = 10; \
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for (; m > 0; m--) {} \
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REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT); \
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REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT); \
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} while(0); \
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} while(REG_READ(INT_ENA_WDEV) != WDEV_TSF0_REACH_INT); \
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} \
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} \
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} while(0)
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} while(0)
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@ -1,10 +1,10 @@
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gwen:
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gwen:
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core: f0128c3
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core: 021ebb5
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net80211: f0128c3
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net80211: 021ebb5
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pp: f0128c3
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pp: 021ebb5
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wpa: f0128c3
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wpa: 021ebb5
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espnow: f0128c3
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espnow: 021ebb5
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wps: f0128c3
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wps: 021ebb5
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smartconfig: 2.8.1
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smartconfig: 2.8.1
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phy: 1055_8
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phy: 1055_8
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@ -88,7 +88,7 @@ typedef unsigned int INT32U;
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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/* Scheduler utilities. */
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/* Scheduler utilities. */
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extern void PendSV(char req);
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extern void PendSV(int req);
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//#define portYIELD() vPortYield()
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//#define portYIELD() vPortYield()
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#define portYIELD() PendSV(1)
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#define portYIELD() PendSV(1)
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@ -50,8 +50,7 @@
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#define PORT_ASSERT(x) do { if (!(x)) {ets_printf("%s %u\n", "rtos_port", __LINE__); while(1){}; }} while (0)
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#define PORT_ASSERT(x) do { if (!(x)) {ets_printf("%s %u\n", "rtos_port", __LINE__); while(1){}; }} while (0)
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extern char NMIIrqIsOn;
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extern char NMIIrqIsOn;
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static uint8_t HdlMacSig = 0;
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static int SWReq = 0;
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static uint8_t SWReq = 0;
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unsigned cpu_sr;
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unsigned cpu_sr;
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@ -102,7 +101,7 @@ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, pdTASK_CODE pxCode
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return (StackType_t *)sp;
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return (StackType_t *)sp;
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}
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}
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void IRAM_ATTR PendSV(char req)
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void IRAM_ATTR PendSV(int req)
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{
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{
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if (req == 1) {
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if (req == 1) {
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vPortEnterCritical();
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vPortEnterCritical();
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@ -110,35 +109,18 @@ void IRAM_ATTR PendSV(char req)
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xthal_set_intset(1 << ETS_SOFT_INUM);
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xthal_set_intset(1 << ETS_SOFT_INUM);
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vPortExitCritical();
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vPortExitCritical();
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} else if (req == 2) {
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} else if (req == 2) {
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HdlMacSig = 1;
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xthal_set_intset(1 << ETS_SOFT_INUM);
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xthal_set_intset(1 << ETS_SOFT_INUM);
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}
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}
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}
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}
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void IRAM_ATTR HDL_MAC_SIG_IN_LV1_ISR(void)
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{
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PendSV(2);
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}
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extern portBASE_TYPE MacIsrSigPostDefHdl(void);
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void TASK_SW_ATTR SoftIsrHdl(void* arg)
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void TASK_SW_ATTR SoftIsrHdl(void* arg)
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{
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{
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ETS_NMI_LOCK();
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extern int MacIsrSigPostDefHdl(void);
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portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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if (MacIsrSigPostDefHdl() || (SWReq == 1)) {
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if (HdlMacSig == 1) {
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HdlMacSig = 0;
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xHigherPriorityTaskWoken = MacIsrSigPostDefHdl();
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}
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if (xHigherPriorityTaskWoken || (SWReq == 1)) {
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_xt_timer_int1();
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_xt_timer_int1();
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SWReq = 0;
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SWReq = 0;
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}
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}
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ETS_NMI_UNLOCK();
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}
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}
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void esp_increase_tick_cnt(const TickType_t ticks)
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void esp_increase_tick_cnt(const TickType_t ticks)
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@ -243,7 +225,6 @@ void IRAM_ATTR vPortExitCritical(void)
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void show_critical_info(void)
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void show_critical_info(void)
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{
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{
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ets_printf("ShowCritical:%u\n", uxCriticalNesting);
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ets_printf("ShowCritical:%u\n", uxCriticalNesting);
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ets_printf("HdlMacSig:%u\n", HdlMacSig);
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ets_printf("SWReq:%u\n", SWReq);
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ets_printf("SWReq:%u\n", SWReq);
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}
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}
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