feat(freertos): Reduce close NMI time

This commit is contained in:
dongheng
2019-03-07 20:34:34 +08:00
parent 05b7351a06
commit 7e25156286
10 changed files with 13 additions and 40 deletions

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@ -51,13 +51,9 @@ extern uint32_t WDEV_INTEREST_EVENT;
#define ETS_NMI_LOCK() \ #define ETS_NMI_LOCK() \
do { \ do { \
char m = 10; \
do { \ do { \
REG_WRITE(INT_ENA_WDEV, 0); \
m = 10; \
for (; m > 0; m--) {} \
REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT); \ REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT); \
} while(0); \ } while(REG_READ(INT_ENA_WDEV) != WDEV_TSF0_REACH_INT); \
} while (0) } while (0)
#define ETS_NMI_UNLOCK() \ #define ETS_NMI_UNLOCK() \
@ -68,13 +64,9 @@ extern uint32_t WDEV_INTEREST_EVENT;
#define ETS_INTR_LOCK() do { \ #define ETS_INTR_LOCK() do { \
if (NMIIrqIsOn == 0) { \ if (NMIIrqIsOn == 0) { \
vPortEnterCritical(); \ vPortEnterCritical(); \
char m = 10; \
do { \ do { \
REG_WRITE(INT_ENA_WDEV, 0); \
m = 10; \
for (; m > 0; m--) {} \
REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT); \ REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT); \
} while(0); \ } while(REG_READ(INT_ENA_WDEV) != WDEV_TSF0_REACH_INT); \
} \ } \
} while(0) } while(0)

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@ -1,10 +1,10 @@
gwen: gwen:
core: f0128c3 core: 021ebb5
net80211: f0128c3 net80211: 021ebb5
pp: f0128c3 pp: 021ebb5
wpa: f0128c3 wpa: 021ebb5
espnow: f0128c3 espnow: 021ebb5
wps: f0128c3 wps: 021ebb5
smartconfig: 2.8.1 smartconfig: 2.8.1
phy: 1055_8 phy: 1055_8

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@ -88,7 +88,7 @@ typedef unsigned int INT32U;
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Scheduler utilities. */ /* Scheduler utilities. */
extern void PendSV(char req); extern void PendSV(int req);
//#define portYIELD() vPortYield() //#define portYIELD() vPortYield()
#define portYIELD() PendSV(1) #define portYIELD() PendSV(1)

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@ -50,8 +50,7 @@
#define PORT_ASSERT(x) do { if (!(x)) {ets_printf("%s %u\n", "rtos_port", __LINE__); while(1){}; }} while (0) #define PORT_ASSERT(x) do { if (!(x)) {ets_printf("%s %u\n", "rtos_port", __LINE__); while(1){}; }} while (0)
extern char NMIIrqIsOn; extern char NMIIrqIsOn;
static uint8_t HdlMacSig = 0; static int SWReq = 0;
static uint8_t SWReq = 0;
unsigned cpu_sr; unsigned cpu_sr;
@ -102,7 +101,7 @@ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, pdTASK_CODE pxCode
return (StackType_t *)sp; return (StackType_t *)sp;
} }
void IRAM_ATTR PendSV(char req) void IRAM_ATTR PendSV(int req)
{ {
if (req == 1) { if (req == 1) {
vPortEnterCritical(); vPortEnterCritical();
@ -110,35 +109,18 @@ void IRAM_ATTR PendSV(char req)
xthal_set_intset(1 << ETS_SOFT_INUM); xthal_set_intset(1 << ETS_SOFT_INUM);
vPortExitCritical(); vPortExitCritical();
} else if (req == 2) { } else if (req == 2) {
HdlMacSig = 1;
xthal_set_intset(1 << ETS_SOFT_INUM); xthal_set_intset(1 << ETS_SOFT_INUM);
} }
} }
void IRAM_ATTR HDL_MAC_SIG_IN_LV1_ISR(void)
{
PendSV(2);
}
extern portBASE_TYPE MacIsrSigPostDefHdl(void);
void TASK_SW_ATTR SoftIsrHdl(void* arg) void TASK_SW_ATTR SoftIsrHdl(void* arg)
{ {
ETS_NMI_LOCK(); extern int MacIsrSigPostDefHdl(void);
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; if (MacIsrSigPostDefHdl() || (SWReq == 1)) {
if (HdlMacSig == 1) {
HdlMacSig = 0;
xHigherPriorityTaskWoken = MacIsrSigPostDefHdl();
}
if (xHigherPriorityTaskWoken || (SWReq == 1)) {
_xt_timer_int1(); _xt_timer_int1();
SWReq = 0; SWReq = 0;
} }
ETS_NMI_UNLOCK();
} }
void esp_increase_tick_cnt(const TickType_t ticks) void esp_increase_tick_cnt(const TickType_t ticks)
@ -243,7 +225,6 @@ void IRAM_ATTR vPortExitCritical(void)
void show_critical_info(void) void show_critical_info(void)
{ {
ets_printf("ShowCritical:%u\n", uxCriticalNesting); ets_printf("ShowCritical:%u\n", uxCriticalNesting);
ets_printf("HdlMacSig:%u\n", HdlMacSig);
ets_printf("SWReq:%u\n", SWReq); ets_printf("SWReq:%u\n", SWReq);
} }