diff --git a/components/esp8266/include/esp8266/i2s_register.h b/components/esp8266/include/esp8266/i2s_register.h new file mode 100644 index 00000000..a08b7b76 --- /dev/null +++ b/components/esp8266/include/esp8266/i2s_register.h @@ -0,0 +1,130 @@ +// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SLC_REGISTER_H_ +#define _SLC_REGISTER_H_ + +#include "eagle_soc.h" + +#define REG_I2S_BASE (0x60000e00) + +#define I2STXFIFO (REG_I2S_BASE + 0x0000) +#define I2SRXFIFO (REG_I2S_BASE + 0x0004) + +#define I2SCONF (REG_I2S_BASE + 0x0008) +#define I2S_BCK_DIV_NUM 0x0000003F +#define I2S_BCK_DIV_NUM_S 22 +#define I2S_CLKM_DIV_NUM 0x0000003F +#define I2S_CLKM_DIV_NUM_S 16 +#define I2S_BITS_MOD 0x0000000F +#define I2S_BITS_MOD_S 12 +#define I2S_RECE_MSB_SHIFT (BIT(11)) +#define I2S_TRANS_MSB_SHIFT (BIT(10)) +#define I2S_I2S_RX_START (BIT(9)) +#define I2S_I2S_TX_START (BIT(8)) +#define I2S_MSB_RIGHT (BIT(7)) +#define I2S_RIGHT_FIRST (BIT(6)) +#define I2S_RECE_SLAVE_MOD (BIT(5)) +#define I2S_TRANS_SLAVE_MOD (BIT(4)) +#define I2S_I2S_RX_FIFO_RESET (BIT(3)) +#define I2S_I2S_TX_FIFO_RESET (BIT(2)) +#define I2S_I2S_RX_RESET (BIT(1)) +#define I2S_I2S_TX_RESET (BIT(0)) +#define I2S_I2S_RESET_MASK 0xf + +#define I2SINT_RAW (REG_I2S_BASE + 0x000c) +#define I2S_I2S_TX_REMPTY_INT_RAW (BIT(5)) +#define I2S_I2S_TX_WFULL_INT_RAW (BIT(4)) +#define I2S_I2S_RX_REMPTY_INT_RAW (BIT(3)) +#define I2S_I2S_RX_WFULL_INT_RAW (BIT(2)) +#define I2S_I2S_TX_PUT_DATA_INT_RAW (BIT(1)) +#define I2S_I2S_RX_TAKE_DATA_INT_RAW (BIT(0)) + + +#define I2SINT_ST (REG_I2S_BASE + 0x0010) +#define I2S_I2S_TX_REMPTY_INT_ST (BIT(5)) +#define I2S_I2S_TX_WFULL_INT_ST (BIT(4)) +#define I2S_I2S_RX_REMPTY_INT_ST (BIT(3)) +#define I2S_I2S_RX_WFULL_INT_ST (BIT(2)) +#define I2S_I2S_TX_PUT_DATA_INT_ST (BIT(1)) +#define I2S_I2S_RX_TAKE_DATA_INT_ST (BIT(0)) + +#define I2SINT_ENA (REG_I2S_BASE + 0x0014) +#define I2S_I2S_TX_REMPTY_INT_ENA (BIT(5)) +#define I2S_I2S_TX_WFULL_INT_ENA (BIT(4)) +#define I2S_I2S_RX_REMPTY_INT_ENA (BIT(3)) +#define I2S_I2S_RX_WFULL_INT_ENA (BIT(2)) +#define I2S_I2S_TX_PUT_DATA_INT_ENA (BIT(1)) +#define I2S_I2S_RX_TAKE_DATA_INT_ENA (BIT(0)) + +#define I2SINT_CLR (REG_I2S_BASE + 0x0018) +#define I2S_I2S_TX_REMPTY_INT_CLR (BIT(5)) +#define I2S_I2S_TX_WFULL_INT_CLR (BIT(4)) +#define I2S_I2S_RX_REMPTY_INT_CLR (BIT(3)) +#define I2S_I2S_RX_WFULL_INT_CLR (BIT(2)) +#define I2S_I2S_PUT_DATA_INT_CLR (BIT(1)) +#define I2S_I2S_TAKE_DATA_INT_CLR (BIT(0)) + +#define I2STIMING (REG_I2S_BASE + 0x001c) +#define I2S_TRANS_BCK_IN_INV (BIT(22)) +#define I2S_RECE_DSYNC_SW (BIT(21)) +#define I2S_TRANS_DSYNC_SW (BIT(20)) +#define I2S_RECE_BCK_OUT_DELAY 0x00000003 +#define I2S_RECE_BCK_OUT_DELAY_S 18 +#define I2S_RECE_WS_OUT_DELAY 0x00000003 +#define I2S_RECE_WS_OUT_DELAY_S 16 +#define I2S_TRANS_SD_OUT_DELAY 0x00000003 +#define I2S_TRANS_SD_OUT_DELAY_S 14 +#define I2S_TRANS_WS_OUT_DELAY 0x00000003 +#define I2S_TRANS_WS_OUT_DELAY_S 12 +#define I2S_TRANS_BCK_OUT_DELAY 0x00000003 +#define I2S_TRANS_BCK_OUT_DELAY_S 10 +#define I2S_RECE_SD_IN_DELAY 0x00000003 +#define I2S_RECE_SD_IN_DELAY_S 8 +#define I2S_RECE_WS_IN_DELAY 0x00000003 +#define I2S_RECE_WS_IN_DELAY_S 6 +#define I2S_RECE_BCK_IN_DELAY 0x00000003 +#define I2S_RECE_BCK_IN_DELAY_S 4 +#define I2S_TRANS_WS_IN_DELAY 0x00000003 +#define I2S_TRANS_WS_IN_DELAY_S 2 +#define I2S_TRANS_BCK_IN_DELAY 0x00000003 +#define I2S_TRANS_BCK_IN_DELAY_S 0 + +#define I2S_FIFO_CONF (REG_I2S_BASE + 0x0020) +#define I2S_I2S_RX_FIFO_MOD 0x00000007 +#define I2S_I2S_RX_FIFO_MOD_S 16 +#define I2S_I2S_TX_FIFO_MOD 0x00000007 +#define I2S_I2S_TX_FIFO_MOD_S 13 +#define I2S_I2S_DSCR_EN (BIT(12)) +#define I2S_I2S_TX_DATA_NUM 0x0000003F +#define I2S_I2S_TX_DATA_NUM_S 6 +#define I2S_I2S_RX_DATA_NUM 0x0000003F +#define I2S_I2S_RX_DATA_NUM_S 0 + + +#define I2SRXEOF_NUM (REG_I2S_BASE + 0x0024) +#define I2S_I2S_RX_EOF_NUM 0xFFFFFFFF +#define I2S_I2S_RX_EOF_NUM_S 0 + +#define I2SCONF_SIGLE_DATA (REG_I2S_BASE + 0x0028) +#define I2S_I2S_SIGLE_DATA 0xFFFFFFFF +#define I2S_I2S_SIGLE_DATA_S 0 + +#define I2SCONF_CHAN (REG_I2S_BASE + 0x002c) +#define I2S_RX_CHAN_MOD 0x00000003 +#define I2S_RX_CHAN_MOD_S 3 +#define I2S_TX_CHAN_MOD 0x00000007 +#define I2S_TX_CHAN_MOD_S 0 + +#endif diff --git a/components/esp8266/include/esp8266/i2s_struct.h b/components/esp8266/include/esp8266/i2s_struct.h new file mode 100644 index 00000000..991979b4 --- /dev/null +++ b/components/esp8266/include/esp8266/i2s_struct.h @@ -0,0 +1,145 @@ +// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "esp8266/eagle_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* ESP8266 I2S Register Definitions */ + +typedef volatile struct { + uint32_t tx_fifo; + uint32_t rx_fifo; + union { + struct { + uint32_t tx_reset: 1; + uint32_t rx_reset: 1; + uint32_t tx_fifo_reset: 1; + uint32_t rx_fifo_reset: 1; + uint32_t tx_slave_mod: 1; + uint32_t rx_slave_mod: 1; + uint32_t right_first: 1; + uint32_t msb_right: 1; + uint32_t tx_start: 1; + uint32_t rx_start: 1; + uint32_t tx_msb_shift: 1; + uint32_t rx_msb_shift: 1; + uint32_t bits_mod: 4; + uint32_t clkm_div_num: 6; + uint32_t bck_div_num: 6; + uint32_t reserved28: 4; + }; + uint32_t val; + } conf; + union { + struct { + uint32_t rx_take_data: 1; + uint32_t tx_put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rx_take_data: 1; + uint32_t tx_put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t rx_take_data: 1; + uint32_t tx_put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t take_data: 1; + uint32_t put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t tx_bck_in_delay: 2; + uint32_t tx_ws_in_delay: 2; + uint32_t rx_bck_in_delay: 2; + uint32_t rx_ws_in_delay: 2; + uint32_t rx_sd_in_delay: 2; + uint32_t tx_bck_out_delay: 2; + uint32_t tx_ws_out_delay: 2; + uint32_t tx_sd_out_delay: 2; + uint32_t rx_ws_out_delay: 2; + uint32_t rx_bck_out_delay: 2; + uint32_t tx_dsync_sw: 1; + uint32_t rx_dsync_sw: 1; + uint32_t tx_bck_in_inv: 1; + uint32_t reserved23: 9; + }; + uint32_t val; + } timing; + union { + struct { + uint32_t rx_data_num: 6; + uint32_t tx_data_num: 6; + uint32_t dscr_en: 1; + uint32_t tx_fifo_mod: 3; + uint32_t rx_fifo_mod: 3; + uint32_t reserved19: 13; + }; + uint32_t val; + } fifo_conf; + uint32_t rx_eof_num; + uint32_t conf_single_data; + union { + struct { + uint32_t tx_chan_mod: 3; + uint32_t rx_chan_mod: 2; + uint32_t reserved5: 27; + }; + uint32_t val; + } conf_chan; +} i2s_struct_t; + +extern volatile i2s_struct_t I2S; + +#ifdef __cplusplus +} +#endif /* end of __cplusplus */ + diff --git a/components/esp8266/include/esp8266/slc_register.h b/components/esp8266/include/esp8266/slc_register.h new file mode 100644 index 00000000..39c4342f --- /dev/null +++ b/components/esp8266/include/esp8266/slc_register.h @@ -0,0 +1,289 @@ +// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SLC_REGISTER_H_ +#define _SLC_REGISTER_H_ + +#include "eagle_soc.h" + +#define REG_SLC_BASE 0x60000B00 +//version value:32'h091700 + +#define SLC_CONF0 (REG_SLC_BASE + 0x0) +#ifndef ESP_MAC_5 +#define SLC_MODE 0x00000003 +#define SLC_MODE_S 12 +#endif +#define SLC_DATA_BURST_EN (BIT(9)) +#define SLC_DSCR_BURST_EN (BIT(8)) +#define SLC_RX_NO_RESTART_CLR (BIT(7)) +#define SLC_RX_AUTO_WRBACK (BIT(6)) +#define SLC_RX_LOOP_TEST (BIT(5)) +#define SLC_TX_LOOP_TEST (BIT(4)) +#define SLC_AHBM_RST (BIT(3)) +#define SLC_AHBM_FIFO_RST (BIT(2)) +#define SLC_RXLINK_RST (BIT(1)) +#define SLC_TXLINK_RST (BIT(0)) + +#define SLC_INT_RAW (REG_SLC_BASE + 0x4) +#define SLC_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SLC_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SLC_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SLC_TOHOST_INT_RAW (BIT(18)) +#define SLC_RX_EOF_INT_RAW (BIT(17)) +#define SLC_RX_DONE_INT_RAW (BIT(16)) +#define SLC_TX_EOF_INT_RAW (BIT(15)) +#define SLC_TX_DONE_INT_RAW (BIT(14)) +#define SLC_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SLC_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SLC_TX_OVF_INT_RAW (BIT(11)) +#define SLC_RX_UDF_INT_RAW (BIT(10)) +#define SLC_TX_START_INT_RAW (BIT(9)) +#define SLC_RX_START_INT_RAW (BIT(8)) +#define SLC_FRHOST_BIT7_INT_RAW (BIT(7)) +#define SLC_FRHOST_BIT6_INT_RAW (BIT(6)) +#define SLC_FRHOST_BIT5_INT_RAW (BIT(5)) +#define SLC_FRHOST_BIT4_INT_RAW (BIT(4)) +#define SLC_FRHOST_BIT3_INT_RAW (BIT(3)) +#define SLC_FRHOST_BIT2_INT_RAW (BIT(2)) +#define SLC_FRHOST_BIT1_INT_RAW (BIT(1)) +#define SLC_FRHOST_BIT0_INT_RAW (BIT(0)) + +#define SLC_INT_STATUS (REG_SLC_BASE + 0x8) +#define SLC_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SLC_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SLC_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SLC_TOHOST_INT_ST (BIT(18)) +#define SLC_RX_EOF_INT_ST (BIT(17)) +#define SLC_RX_DONE_INT_ST (BIT(16)) +#define SLC_TX_EOF_INT_ST (BIT(15)) +#define SLC_TX_DONE_INT_ST (BIT(14)) +#define SLC_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SLC_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SLC_TX_OVF_INT_ST (BIT(11)) +#define SLC_RX_UDF_INT_ST (BIT(10)) +#define SLC_TX_START_INT_ST (BIT(9)) +#define SLC_RX_START_INT_ST (BIT(8)) +#define SLC_FRHOST_BIT7_INT_ST (BIT(7)) +#define SLC_FRHOST_BIT6_INT_ST (BIT(6)) +#define SLC_FRHOST_BIT5_INT_ST (BIT(5)) +#define SLC_FRHOST_BIT4_INT_ST (BIT(4)) +#define SLC_FRHOST_BIT3_INT_ST (BIT(3)) +#define SLC_FRHOST_BIT2_INT_ST (BIT(2)) +#define SLC_FRHOST_BIT1_INT_ST (BIT(1)) +#define SLC_FRHOST_BIT0_INT_ST (BIT(0)) + +#define SLC_INT_ENA (REG_SLC_BASE + 0xC) +#define SLC_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SLC_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SLC_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SLC_TOHOST_INT_ENA (BIT(18)) +#define SLC_RX_EOF_INT_ENA (BIT(17)) +#define SLC_RX_DONE_INT_ENA (BIT(16)) +#define SLC_TX_EOF_INT_ENA (BIT(15)) +#define SLC_TX_DONE_INT_ENA (BIT(14)) +#define SLC_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SLC_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SLC_TX_OVF_INT_ENA (BIT(11)) +#define SLC_RX_UDF_INT_ENA (BIT(10)) +#define SLC_TX_START_INT_ENA (BIT(9)) +#define SLC_RX_START_INT_ENA (BIT(8)) +#define SLC_FRHOST_BIT7_INT_ENA (BIT(7)) +#define SLC_FRHOST_BIT6_INT_ENA (BIT(6)) +#define SLC_FRHOST_BIT5_INT_ENA (BIT(5)) +#define SLC_FRHOST_BIT4_INT_ENA (BIT(4)) +#define SLC_FRHOST_BIT3_INT_ENA (BIT(3)) +#define SLC_FRHOST_BIT2_INT_ENA (BIT(2)) +#define SLC_FRHOST_BIT1_INT_ENA (BIT(1)) +#define SLC_FRHOST_BIT0_INT_ENA (BIT(0)) + +#define SLC_FRHOST_BIT_INT_ENA_ALL 0xff + +#define SLC_INT_CLR (REG_SLC_BASE + 0x10) +#define SLC_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SLC_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SLC_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SLC_TOHOST_INT_CLR (BIT(18)) +#define SLC_RX_EOF_INT_CLR (BIT(17)) +#define SLC_RX_DONE_INT_CLR (BIT(16)) +#define SLC_TX_EOF_INT_CLR (BIT(15)) +#define SLC_TX_DONE_INT_CLR (BIT(14)) +#define SLC_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SLC_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SLC_TX_OVF_INT_CLR (BIT(11)) +#define SLC_RX_UDF_INT_CLR (BIT(10)) +#define SLC_TX_START_INT_CLR (BIT(9)) +#define SLC_RX_START_INT_CLR (BIT(8)) +#define SLC_FRHOST_BIT7_INT_CLR (BIT(7)) +#define SLC_FRHOST_BIT6_INT_CLR (BIT(6)) +#define SLC_FRHOST_BIT5_INT_CLR (BIT(5)) +#define SLC_FRHOST_BIT4_INT_CLR (BIT(4)) +#define SLC_FRHOST_BIT3_INT_CLR (BIT(3)) +#define SLC_FRHOST_BIT2_INT_CLR (BIT(2)) +#define SLC_FRHOST_BIT1_INT_CLR (BIT(1)) +#define SLC_FRHOST_BIT0_INT_CLR (BIT(0)) + +#define SLC_RX_STATUS (REG_SLC_BASE + 0x14) +#define SLC_RX_EMPTY (BIT(1)) +#define SLC_RX_FULL (BIT(0)) + +#define SLC_RX_FIFO_PUSH (REG_SLC_BASE + 0x18) +#define SLC_RXFIFO_PUSH (BIT(16)) +#define SLC_RXFIFO_WDATA 0x000001FF +#define SLC_RXFIFO_WDATA_S 0 + +#define SLC_TX_STATUS (REG_SLC_BASE + 0x1C) +#define SLC_TX_EMPTY (BIT(1)) +#define SLC_TX_FULL (BIT(0)) + +#define SLC_TX_FIFO_POP (REG_SLC_BASE + 0x20) +#define SLC_TXFIFO_POP (BIT(16)) +#define SLC_TXFIFO_RDATA 0x000007FF +#define SLC_TXFIFO_RDATA_S 0 + +#define SLC_RX_LINK (REG_SLC_BASE + 0x24) +#define SLC_RXLINK_PARK (BIT(31)) +#define SLC_RXLINK_RESTART (BIT(30)) +#define SLC_RXLINK_START (BIT(29)) +#define SLC_RXLINK_STOP (BIT(28)) +#define SLC_RXLINK_DESCADDR_MASK 0x000FFFFF +#define SLC_RXLINK_ADDR_S 0 + +#define SLC_TX_LINK (REG_SLC_BASE + 0x28) +#define SLC_TXLINK_PARK (BIT(31)) +#define SLC_TXLINK_RESTART (BIT(30)) +#define SLC_TXLINK_START (BIT(29)) +#define SLC_TXLINK_STOP (BIT(28)) +#define SLC_TXLINK_DESCADDR_MASK 0x000FFFFF +#define SLC_TXLINK_ADDR_S 0 + +#define SLC_INTVEC_TOHOST (REG_SLC_BASE + 0x2C) +#define SLC_TOHOST_INTVEC 0x000000FF +#define SLC_TOHOST_INTVEC_S 0 + +#define SLC_TOKEN0 (REG_SLC_BASE + 0x30) +#define SLC_TOKEN0_MASK 0x00000FFF +#define SLC_TOKEN0_S 16 +#define SLC_TOKEN0_LOCAL_INC_MORE (BIT(14)) +#define SLC_TOKEN0_LOCAL_INC (BIT(13)) +#define SLC_TOKEN0_LOCAL_WR (BIT(12)) +#define SLC_TOKEN0_LOCAL_WDATA_MASK 0x00000FFF +#define SLC_TOKEN0_LOCAL_WDATA_S 0 + +#define SLC_TOKEN1 (REG_SLC_BASE + 0x34) +#define SLC_TOKEN1_MASK 0x00000FFF +#define SLC_TOKEN1_S 16 +#define SLC_TOKEN1_LOCAL_INC_MORE (BIT(14)) +#define SLC_TOKEN1_LOCAL_INC (BIT(13)) +#define SLC_TOKEN1_LOCAL_WR (BIT(12)) +#define SLC_TOKEN1_LOCAL_WDATA 0x00000FFF +#define SLC_TOKEN1_LOCAL_WDATA_S 0 + +#define SLC_CONF1 (REG_SLC_BASE + 0x38) +#define SLC_STATE0 (REG_SLC_BASE + 0x3C) +#define SLC_STATE1 (REG_SLC_BASE + 0x40) + +#define SLC_BRIDGE_CONF (REG_SLC_BASE + 0x44) +#ifndef ESP_MAC_5 +#define SLC_TX_PUSH_IDLE_NUM 0x0000FFFF +#define SLC_TX_PUSH_IDLE_NUM_S 16 +#define SLC_TX_DUMMY_MODE (BIT(12)) +#endif +#define SLC_FIFO_MAP_ENA 0x0000000F +#define SLC_FIFO_MAP_ENA_S 8 +#define SLC_TXEOF_ENA 0x0000003F +#define SLC_TXEOF_ENA_S 0 + +#define SLC_RX_EOF_DES_ADDR (REG_SLC_BASE + 0x48) +#define SLC_TX_EOF_DES_ADDR (REG_SLC_BASE + 0x4C) +#define SLC_FROM_HOST_LAST_DESC SLC_TX_EOF_DES_ADDR +#define SLC_TO_HOST_LAST_DESC SLC_RX_EOF_DES_ADDR + +#define SLC_RX_EOF_BFR_DES_ADDR (REG_SLC_BASE + 0x50) +#define SLC_AHB_TEST (REG_SLC_BASE + 0x54) +#define SLC_AHB_TESTADDR 0x00000003 +#define SLC_AHB_TESTADDR_S 4 +#define SLC_AHB_TESTMODE 0x00000007 +#define SLC_AHB_TESTMODE_S 0 + +#define SLC_SDIO_ST (REG_SLC_BASE + 0x58) +#define SLC_BUS_ST 0x00000007 +#define SLC_BUS_ST_S 12 +#define SLC_SDIO_WAKEUP (BIT(8)) +#define SLC_FUNC_ST 0x0000000F +#define SLC_FUNC_ST_S 4 +#define SLC_CMD_ST 0x00000007 +#define SLC_CMD_ST_S 0 + +#define SLC_RX_DSCR_CONF (REG_SLC_BASE + 0x5C) +#ifdef ESP_MAC_5 +#define SLC_INFOR_NO_REPLACE (BIT(9)) +#define SLC_TOKEN_NO_REPLACE (BIT(8)) +#define SLC_POP_IDLE_CNT 0x000000FF +#else +#define SLC_RX_FILL_EN (BIT(20)) +#define SLC_RX_EOF_MODE (BIT(19)) +#define SLC_RX_FILL_MODE (BIT(18)) +#define SLC_INFOR_NO_REPLACE (BIT(17)) +#define SLC_TOKEN_NO_REPLACE (BIT(16)) // +#define SLC_POP_IDLE_CNT 0x0000FFFF +#endif +#define SLC_POP_IDLE_CNT_S 0 + +#define SLC_TXLINK_DSCR (REG_SLC_BASE + 0x60) +#define SLC_TXLINK_DSCR_BF0 (REG_SLC_BASE + 0x64) +#define SLC_TXLINK_DSCR_BF1 (REG_SLC_BASE + 0x68) +#define SLC_RXLINK_DSCR (REG_SLC_BASE + 0x6C) +#define SLC_RXLINK_DSCR_BF0 (REG_SLC_BASE + 0x70) +#define SLC_RXLINK_DSCR_BF1 (REG_SLC_BASE + 0x74) +#define SLC_DATE (REG_SLC_BASE + 0x78) +#define SLC_ID (REG_SLC_BASE + 0x7C) + +#define SLC_HOST_CONF_W0 (REG_SLC_BASE + 0x80 + 0x14) +#define SLC_HOST_CONF_W1 (REG_SLC_BASE + 0x80 + 0x18) +#define SLC_HOST_CONF_W2 (REG_SLC_BASE + 0x80 + 0x20) +#define SLC_HOST_CONF_W3 (REG_SLC_BASE + 0x80 + 0x24) +#define SLC_HOST_CONF_W4 (REG_SLC_BASE + 0x80 + 0x28) + +#define SLC_HOST_INTR_ST (REG_SLC_BASE + 0x80 + 0x1c) +#define SLC_HOST_INTR_CLR (REG_SLC_BASE + 0x80 + 0x30) +#define SLC_HOST_INTR_SOF_BIT (BIT(12)) + +#define SLC_HOST_INTR_ENA (REG_SLC_BASE + 0x80 + 0x34) +#define SLC_RX_NEW_PACKET_INT_ENA (BIT23) +#define SLC_HOST_TOHOST_BIT0_INT_ENA (BIT0) +#define SLC_HOST_CONF_W5 (REG_SLC_BASE + 0x80 + 0x3C) +#define SLC_HOST_INTR_RAW (REG_SLC_BASE + 0x80 + 0x8) +#define SLC_HOST_INTR_ENA_BIT (BIT(23)) +//[15:12]: 0x3ff9xxxx -- 0b01 from_host +// 0x3ffaxxxx -- 0b10 general +// 0x3ffbxxxx -- 0b11 to_host +#define SLC_DATA_ADDR_CLEAR_MASK (~(0xf<<12)) +#define SLC_FROM_HOST_ADDR_MASK (0x1<<12) +#define SLC_TO_HOST_ADDR_MASK (0x3<<12) + +#define SLC_SET_FROM_HOST_ADDR_MASK(v) do { \ + (v) &= SLC_DATA_ADDR_CLEAR_MASK; \ + (v) |= SLC_FROM_HOST_ADDR_MASK; \ + } while(0); + +#define SLC_SET_TO_HOST_ADDR_MASK(v) do { \ + (v) &= SLC_DATA_ADDR_CLEAR_MASK; \ + (v) |= SLC_TO_HOST_ADDR_MASK; \ + } while(0); + + +#define SLC_TX_DESC_DEBUG_REG 0x3ff0002c //[15:0] set to 0xcccc + +#endif diff --git a/components/esp8266/include/esp8266/slc_struct.h b/components/esp8266/include/esp8266/slc_struct.h new file mode 100644 index 00000000..fcb0227c --- /dev/null +++ b/components/esp8266/include/esp8266/slc_struct.h @@ -0,0 +1,348 @@ +// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "esp8266/eagle_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ESP8266 SLC Register Definitions */ + +typedef struct { + union { + struct { + uint32_t tx_rst: 1; + uint32_t rx_rst: 1; + uint32_t ahbm_fifo_rst: 1; + uint32_t ahbm_rst: 1; + uint32_t tx_loop_test: 1; + uint32_t rx_loop_test: 1; + uint32_t rx_auto_wrback: 1; + uint32_t rx_no_restart_clr: 1; + uint32_t rxdscr_burst_en: 1; + uint32_t rxdata_burst_en: 1; + uint32_t rxlink_auto_ret: 1; + uint32_t txlink_auto_ret: 1; + uint32_t txdscr_burst_en: 1; + uint32_t txdata_burst_en: 1; + uint32_t reserved14: 18; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t frhost_bit0: 1; + uint32_t frhost_bit1: 1; + uint32_t frhost_bit2: 1; + uint32_t frhost_bit3: 1; + uint32_t frhost_bit4: 1; + uint32_t frhost_bit5: 1; + uint32_t frhost_bit6: 1; + uint32_t frhost_bit7: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t reserved22: 10; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t frhost_bit0: 1; + uint32_t frhost_bit1: 1; + uint32_t frhost_bit2: 1; + uint32_t frhost_bit3: 1; + uint32_t frhost_bit4: 1; + uint32_t frhost_bit5: 1; + uint32_t frhost_bit6: 1; + uint32_t frhost_bit7: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t reserved22: 10; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t frhost_bit0: 1; + uint32_t frhost_bit1: 1; + uint32_t frhost_bit2: 1; + uint32_t frhost_bit3: 1; + uint32_t frhost_bit4: 1; + uint32_t frhost_bit5: 1; + uint32_t frhost_bit6: 1; + uint32_t frhost_bit7: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t reserved22: 10; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t frhost_bit0: 1; + uint32_t frhost_bit1: 1; + uint32_t frhost_bit2: 1; + uint32_t frhost_bit3: 1; + uint32_t frhost_bit4: 1; + uint32_t frhost_bit5: 1; + uint32_t frhost_bit6: 1; + uint32_t frhost_bit7: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t reserved22: 10; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t rx_full: 1; + uint32_t rx_empty: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } rx_status; + union { + struct { + uint32_t rxfifo_wdata: 9; + uint32_t reserved9: 7; + uint32_t rxfifo_push: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } rxfifo_push; + union { + struct { + uint32_t tx_full: 1; + uint32_t tx_empty: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } tx_status; + union { + struct { + uint32_t txfifo_rdata: 11; + uint32_t reserved11: 5; + uint32_t txfifo_pop: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } txfifo_pop; + union { + struct { + uint32_t addr: 20; + uint32_t reserved20: 8; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; + }; + uint32_t val; + } rx_link; + union { + struct { + uint32_t addr: 20; + uint32_t reserved20: 8; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; + }; + uint32_t val; + } tx_link; + union { + struct { + uint32_t intvec: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } intvec_tohost; + union { + struct { + uint32_t wdata: 12; + uint32_t wr: 1; + uint32_t inc: 1; + uint32_t inc_more: 1; + uint32_t reserved15: 1; + uint32_t token0: 12; + uint32_t reserved28: 4; + }; + uint32_t val; + } token0; + union { + struct { + uint32_t wdata: 12; + uint32_t wr: 1; + uint32_t inc: 1; + uint32_t inc_more: 1; + uint32_t reserved15: 1; + uint32_t token1: 12; + uint32_t reserved28: 4; + }; + uint32_t val; + } token1; + uint32_t conf1; + uint32_t state0; + uint32_t state1; + union { + struct { + uint32_t txeof_ena: 6; + uint32_t reserved6: 2; + uint32_t fifo_map_ena: 4; + uint32_t tx_dummy_mode: 1; + uint32_t reserved13: 3; + uint32_t tx_push_idle_num: 16; + }; + uint32_t val; + } bridge_conf; + uint32_t rx_eof_des_addr; + uint32_t tx_eof_des_addr; + uint32_t to_eof_bfr_des_addr; + union { + struct { + uint32_t mode: 3; + uint32_t reserved3: 1; + uint32_t addr: 2; + uint32_t reserved6: 26; + }; + uint32_t val; + } ahb_test; + union { + struct { + uint32_t cmd_st: 3; + uint32_t reserved3: 1; + uint32_t func_st: 4; + uint32_t sdio_wakeup: 1; + uint32_t reserved9: 3; + uint32_t bus_st: 3; + uint32_t reserved15: 17; + }; + uint32_t val; + } sdio_st; + union { + struct { + uint32_t pop_idle_cnt: 16; + uint32_t token_no_replace: 1; + uint32_t infor_no_replace: 1; + uint32_t rx_fill_mode: 1; + uint32_t rx_eof_mode: 1; + uint32_t rx_fill_en: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } rx_dscr_conf; + uint32_t txlink_dscr; + uint32_t txlink_dscr_bf0; + uint32_t txlink_dscr_bf1; + uint32_t rxlink_dscr; + uint32_t rxlink_dscr_bf0; + uint32_t rxlink_dscr_bf1; + uint32_t date; + uint32_t id; + uint32_t reserved_80[2]; + union { + struct { + uint32_t reserved0: 23; + uint32_t intr_ena: 1; + uint32_t reserved24: 8; + }; + uint32_t val; + } host_intr_raw; + uint32_t reserved_8C[2]; + uint32_t host_conf_w0; + uint32_t host_conf_w1; + uint32_t host_intr_status; + uint32_t host_conf_w2; + uint32_t host_conf_w3; + uint32_t host_conf_w4; + uint32_t reserved_AC[1]; + union { + struct { + uint32_t reserved0: 12; + uint32_t sof_bit: 1; + uint32_t reserved13: 19; + }; + uint32_t val; + } host_intr_clr; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t reserved1: 22; + uint32_t rx_new_packet: 1; + uint32_t reserved24: 8; + }; + uint32_t val; + } host_intr_ena; + uint32_t reserved_BC[1]; + uint32_t host_conf_w5; +} slc_struct_t; + +extern volatile slc_struct_t SLC; + +#ifdef __cplusplus +} +#endif /* end of __cplusplus */ + diff --git a/components/esp8266/ld/esp8266.peripherals.ld b/components/esp8266/ld/esp8266.peripherals.ld index 1cad1737..6fa3dc81 100644 --- a/components/esp8266/ld/esp8266.peripherals.ld +++ b/components/esp8266/ld/esp8266.peripherals.ld @@ -5,4 +5,6 @@ PROVIDE ( uart1 = 0x60000f00 ); PROVIDE ( frc1 = 0x60000600 ); -PROVIDE ( rtc_sys_info = 0x60001100 ); \ No newline at end of file +PROVIDE ( rtc_sys_info = 0x60001100 ); +PROVIDE ( SLC = 0x60000B00 ); +PROVIDE ( I2S = 0x60000e00 );