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Merge branch 'feature/hspi_test' into 'master'

Browse Source 
feat(spi): fix some bugs and restructure the spi driver and the demo

See merge request sdk/ESP8266_RTOS_SDK!1113
This commit is contained in:
Dong Heng
2019-11-13 10:00:35 +08:00
parent 1e509f6b89 916906d09a
commit 73bf28b991
44 changed files with 1879 additions and 660 deletions
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1
components/esp8266/CMakeLists.txt
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@ -46,6 +46,7 @@ else()
"driver/i2s.c"
"driver/pwm.c"
"driver/spi.c"
"driver/hspi_logic_layer.c"
"driver/uart.c"
"driver/ir_tx.c"
"driver/ir_rx.c"

9
components/esp8266/Kconfig
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@ -627,3 +627,12 @@ config ESP8266_PHY_MAX_WIFI_TX_POWER
endmenu # PHY
menu HSPI
config ESP8266_HSPI_HIGH_THROUGHPUT
bool "Do some optimization to improve throughput"
default n
help
If enable this configuration, some spi api will be placed into iram.
And it will reduce iram memory.
endmenu # Driver

278
components/esp8266/driver/hspi_logic_layer.c Normal file
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@ -0,0 +1,278 @@
#include <stdio.h>
#include <string.h>
#include <sys/time.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "freertos/event_groups.h"
#include "freertos/stream_buffer.h"
#include "ringbuf.h"
#include "esp8266/spi_struct.h"
#include "esp8266/gpio_struct.h"
#include "esp_system.h"
#include "esp_log.h"
#include "driver/gpio.h"
#include "driver/spi.h"
#include "driver/hspi_logic_layer.h"
static const char *TAG = "hspi_logic";
#define SPI_CHECK(a, str, ret_val) \
do { \
if (!(a)) { \
ESP_LOGE(TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
return (ret_val); \
} \
} while(0)
typedef struct {
gpio_num_t trigger_pin;
uint8_t trigger_level;
bool is_sending;
bool is_blocking_recv;
uint32_t sending_len;
uint32_t recving_len;
StreamBufferHandle_t* tx_buffer;
StreamBufferHandle_t* rx_buffer;
SemaphoreHandle_t semphor;
spi_event_callback_t event_cb;
} spi_logic_device_t;
static spi_logic_device_t * spi_logic_device;
static void IRAM_ATTR hspi_slave_event_callback(int event, void *arg)
{
int x;
BaseType_t xHigherPriorityTaskWoken;
uint32_t status;
uint32_t trans_done;
uint32_t data[16];
spi_trans_t trans;
uint16_t cmd = 0;
bool trigger_flag = false;
switch (event) {
case SPI_TRANS_DONE_EVENT: {
gpio_set_level(spi_logic_device->trigger_pin, !spi_logic_device->trigger_level);
trans_done = *(uint32_t *)arg;
if (trans_done & SPI_SLV_RD_BUF_DONE) {
if (spi_logic_device->sending_len == 0) {
spi_logic_device->is_sending = false;
spi_logic_device->sending_len = xStreamBufferBytesAvailable(spi_logic_device->tx_buffer);
if (spi_logic_device->sending_len > 0) {
spi_slave_set_status(HSPI_HOST, (uint32_t*)&spi_logic_device->sending_len);
spi_logic_device->is_sending = true;
trigger_flag = true;
}
} else {
memset(&trans, 0x0, sizeof(trans));
trans.cmd = &cmd;
trans.addr = NULL;
trans.bits.val = 0;
// In Slave mode, spi cmd must be longer than 3 bits and shorter than 16 bits
trans.bits.cmd = 8 * 1;
// In Slave mode, spi addr must be longer than 1 bits and shorter than 32 bits
trans.bits.addr = 8 * 1;
trans.bits.mosi = 0;
trans.miso = data;
trans.bits.miso = xStreamBufferReceiveFromISR(spi_logic_device->tx_buffer, data, 64, &xHigherPriorityTaskWoken);
if (trans.bits.miso != 0) {
spi_logic_device->sending_len -= trans.bits.miso;
trans.bits.miso <<= 3;
spi_trans(HSPI_HOST, &trans);
trigger_flag = true;;
}
}
}
if (trans_done & SPI_SLV_WR_BUF_DONE) {
uint32_t len = spi_logic_device->recving_len;
if (len > 64) {
len = 64;
}
if (len > 0) {
for (x = 0; x < 16; x++) {
data[x] = SPI1.data_buf[x];
}
xStreamBufferSendFromISR(spi_logic_device->rx_buffer, (void *) data, len, &xHigherPriorityTaskWoken);
spi_logic_device->recving_len -= len;
} else {
ets_printf("remained %d\r\n", len);
}
if (xStreamBufferSpacesAvailable(spi_logic_device->rx_buffer) >= 64) {
trigger_flag = true;
} else {
spi_logic_device->is_blocking_recv = true;
}
}
if (trans_done & SPI_SLV_WR_STA_DONE) {
spi_slave_get_status(HSPI_HOST, &status);
spi_logic_device->recving_len = status;
uint32_t tx_size = xStreamBufferBytesAvailable(spi_logic_device->tx_buffer);
if (spi_logic_device->recving_len > 0) {
trigger_flag = true;
} else if (tx_size > 0) {
if (spi_logic_device->is_sending == false) {
spi_slave_set_status(HSPI_HOST, &tx_size);
}
trigger_flag = true;
}
}
if (trans_done & SPI_SLV_RD_STA_DONE) {
memset(&trans, 0x0, sizeof(trans));
trans.cmd = &cmd;
trans.addr = NULL;
trans.bits.val = 0;
// In Slave mode, spi cmd must be longer than 3 bits and shorter than 16 bits
trans.bits.cmd = 8 * 1;
// In Slave mode, spi addr must be longer than 1 bits and shorter than 32 bits
trans.bits.addr = 8 * 1;
trans.bits.mosi = 0;
trans.miso = data;
trans.bits.miso = xStreamBufferReceiveFromISR(spi_logic_device->tx_buffer, data, 64, &xHigherPriorityTaskWoken);
if (trans.bits.miso != 0) {
spi_logic_device->sending_len -= trans.bits.miso;
trans.bits.miso <<= 3;
spi_trans(HSPI_HOST, &trans);
trigger_flag = true;
}
}
if (trigger_flag) {
gpio_set_level(spi_logic_device->trigger_pin, spi_logic_device->trigger_level);
}
if (spi_logic_device->event_cb) {
spi_logic_device->event_cb(event, arg);
}
if (xHigherPriorityTaskWoken == pdTRUE) {
taskYIELD();
}
}
break;
case SPI_DEINIT_EVENT: {
}
break;
}
}
uint32_t hspi_slave_logic_read_data(uint8_t*data, uint32_t len, TickType_t xTicksToWait)
{
uint32_t ret = 0;
ret = xStreamBufferReceive(spi_logic_device->rx_buffer, data, len, xTicksToWait);
if (spi_logic_device->is_blocking_recv) {
if (xStreamBufferBytesAvailable(spi_logic_device->rx_buffer) > 64) {
gpio_set_level(spi_logic_device->trigger_pin, spi_logic_device->trigger_level);
spi_logic_device->is_blocking_recv = false;
}
}
return ret;
}
uint32_t hspi_slave_logic_write_data(uint8_t*data, uint32_t len, TickType_t xTicksToWait)
{
uint32_t ret = 0;
uint32_t avail_spaces = 0;
if (!spi_logic_device->is_sending) {
portENTER_CRITICAL();
avail_spaces = xStreamBufferSpacesAvailable(spi_logic_device->tx_buffer);
if (avail_spaces > len) {
avail_spaces = len;
}
ret = xStreamBufferSend(spi_logic_device->tx_buffer, data, avail_spaces, xTicksToWait); //
spi_logic_device->sending_len = xStreamBufferBytesAvailable(spi_logic_device->tx_buffer);
spi_slave_set_status(HSPI_HOST, (uint32_t*)&spi_logic_device->sending_len);
spi_logic_device->is_sending = true;
gpio_set_level(spi_logic_device->trigger_pin, spi_logic_device->trigger_level);
portEXIT_CRITICAL();
}
if (ret < len) {
ret += xStreamBufferSend(spi_logic_device->tx_buffer, data + ret, len - ret, xTicksToWait);
}
return ret;
}
esp_err_t hspi_slave_logic_device_create(gpio_num_t trigger_pin, uint32_t trigger_level,uint32_t tx_buffer_size, uint32_t rx_buffer_size)
{
SPI_CHECK(GPIO_IS_VALID_GPIO(trigger_pin), "gpio num error", ESP_ERR_INVALID_ARG);
SPI_CHECK(tx_buffer_size != 0, "tx buffer error", ESP_ERR_INVALID_ARG);
SPI_CHECK(rx_buffer_size != 0, "rx buffer error", ESP_ERR_INVALID_ARG);
gpio_config_t io_conf;
if (spi_logic_device) {
hspi_slave_logic_device_delete();
}
spi_logic_device = (spi_logic_device_t*)malloc(sizeof(spi_logic_device_t));
assert(spi_logic_device);
memset(spi_logic_device, 0x0, sizeof(spi_logic_device_t));
spi_logic_device->tx_buffer = xStreamBufferCreate(tx_buffer_size,1);
if (!spi_logic_device->tx_buffer) {
free(spi_logic_device);
spi_logic_device = NULL;
return ESP_ERR_NO_MEM;
}
spi_logic_device->rx_buffer = xStreamBufferCreate(rx_buffer_size,1);
if (!spi_logic_device->rx_buffer) {
vStreamBufferDelete(spi_logic_device->tx_buffer);
spi_logic_device->tx_buffer = NULL;
free(spi_logic_device);
spi_logic_device = NULL;
return ESP_ERR_NO_MEM;
}
spi_logic_device->trigger_pin = trigger_pin;
spi_logic_device->trigger_level = (trigger_level==1)?1:0;
memset(&io_conf, 0x0, sizeof(io_conf));
io_conf.intr_type = GPIO_INTR_DISABLE;
io_conf.mode = GPIO_MODE_OUTPUT;
io_conf.pin_bit_mask = (1ULL << trigger_pin);
io_conf.pull_down_en = 0;
io_conf.pull_up_en = 0;
gpio_config(&io_conf);
gpio_set_level(trigger_pin, !spi_logic_device->trigger_level);
spi_get_event_callback(HSPI_HOST, &spi_logic_device->event_cb);
spi_event_callback_t event_cb = hspi_slave_event_callback;
spi_set_event_callback(HSPI_HOST, &event_cb);
return ESP_OK;
}
esp_err_t hspi_slave_logic_device_delete(void)
{
if (spi_logic_device == NULL) {
return ESP_ERR_INVALID_STATE;
}
vStreamBufferDelete(spi_logic_device->tx_buffer);
spi_logic_device->tx_buffer = NULL;
vStreamBufferDelete(spi_logic_device->rx_buffer);
spi_logic_device->rx_buffer = NULL;
free(spi_logic_device);
spi_logic_device = NULL;
return ESP_OK;
}

283
components/esp8266/driver/spi.c
View File

@ -15,10 +15,9 @@
#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include "FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "esp8266/eagle_soc.h"
#include "esp8266/spi_struct.h"
#include "esp8266/pin_mux_register.h"
@ -27,21 +26,45 @@
#include "esp_attr.h"
#include "esp_err.h"
#include "esp_log.h"
#include "esp_heap_caps.h"
#include "rom/ets_sys.h"
#include "spi.h"
#define ENTER_CRITICAL() portENTER_CRITICAL()
#define EXIT_CRITICAL() portEXIT_CRITICAL()
#define SPI_CHECK(a, str, ret_val) \
do { \
if (!(a)) { \
ESP_LOGE(TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
return (ret_val); \
} \
} while(0)
#define portYIELD_FROM_ISR() taskYIELD()
#ifndef CONFIG_ESP8266_HSPI_HIGH_THROUGHPUT
#define ENTER_CRITICAL_HIGH_THROUGHPUT() ENTER_CRITICAL()
#define EXIT_CRITICAL_HIGH_THROUGHPUT() EXIT_CRITICAL()
#define SPI_HIGH_THROUGHPUT_ATTR
#define SPI_CHECK_HIGH_THROUGHPUT(a, str, ret_val) SPI_CHECK(a, str, ret_val)
#else
#define SPI_HIGH_THROUGHPUT_ATTR IRAM_ATTR
#define ENTER_CRITICAL_HIGH_THROUGHPUT() do{} while(0)
#define EXIT_CRITICAL_HIGH_THROUGHPUT() do{} while(0)
#define SPI_CHECK_HIGH_THROUGHPUT(a, str, ret_val) \
do { \
if (!(a)) { \
ets_printf("%s(%d): %s", __FUNCTION__, __LINE__, str); \
return (ret_val); \
} \
} while(0)
#endif
static const char *TAG = "spi";
#define SPI_CHECK(a, str, ret_val) \
if (!(a)) { \
ESP_LOGE(TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
return (ret_val); \
}
#define spi_intr_enable() _xt_isr_unmask(1 << ETS_SPI_INUM)
#define spi_intr_disable() _xt_isr_mask(1 << ETS_SPI_INUM)
#define spi_intr_register(a, b) _xt_isr_attach(ETS_SPI_INUM, (a), (b))
@ -56,6 +79,8 @@ typedef struct {
spi_interface_t interface;
SemaphoreHandle_t trans_mux;
spi_event_callback_t event_cb;
spi_intr_enable_t intr_enable;
uint32_t *buf;
} spi_object_t;
static spi_object_t *spi_object[SPI_NUM_MAX] = {NULL, NULL};
@ -164,6 +189,8 @@ esp_err_t spi_set_intr_enable(spi_host_t host, spi_intr_enable_t *intr_enable)
SPI[host]->slave.trans_done = false;
EXIT_CRITICAL();
spi_object[host]->intr_enable.val = intr_enable->val;
return ESP_OK;
}
@ -209,16 +236,25 @@ esp_err_t spi_set_mode(spi_host_t host, spi_mode_t *mode)
// Set to Slave mode
SPI[host]->pin.slave_mode = true;
SPI[host]->slave.slave_mode = true;
SPI[host]->user.usr_miso_highpart = true;
SPI[host]->user.usr_mosi_highpart = false;
SPI[host]->user.usr_miso_highpart = false;
SPI[host]->user.usr_addr = 1;
// MOSI signals are delayed by APB_CLK(80MHz) mosi_delay_num cycles
SPI[host]->ctrl2.mosi_delay_num = 2;
SPI[host]->ctrl2.miso_delay_num = 0;
SPI[host]->slave.wr_rd_buf_en = 1;
SPI[host]->slave.wr_rd_sta_en = 1;
SPI[host]->slave1.status_bitlen = 31;
SPI[host]->slave1.status_readback = 0;
// Put the slave's miso on the highpart, so you can only send 256bits
// Put the slave's miso on the highpart, so you can only send 512bits
// In Slave mode miso, mosi length is the same
SPI[host]->slave1.buf_bitlen = 255;
SPI[host]->slave1.buf_bitlen = 511;
SPI[host]->slave1.wr_addr_bitlen = 7;
SPI[host]->slave1.rd_addr_bitlen = 7;
SPI[host]->user1.usr_addr_bitlen = 7;
SPI[host]->user1.usr_miso_bitlen = 31;
SPI[host]->user1.usr_mosi_bitlen = 31;
SPI[host]->user2.usr_command_bitlen = 7;
SPI[host]->cmd.usr = 1;
}
@ -231,6 +267,7 @@ esp_err_t spi_set_mode(spi_host_t host, spi_mode_t *mode)
SPI[host]->ctrl.fread_dio = false;
SPI[host]->ctrl.fread_qio = false;
SPI[host]->ctrl.fastrd_mode = true;
SPI[host]->slave.sync_reset = 1;
EXIT_CRITICAL();
return ESP_OK;
@ -396,71 +433,81 @@ esp_err_t spi_slave_get_status(spi_host_t host, uint32_t *status)
return ESP_OK;
}
esp_err_t spi_slave_set_status(spi_host_t host, uint32_t *status)
esp_err_t SPI_HIGH_THROUGHPUT_ATTR spi_slave_set_status(spi_host_t host, uint32_t *status)
{
SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
SPI_CHECK(SPI_SLAVE_MODE == spi_object[host]->mode, "this function must used by spi slave mode", ESP_FAIL);
SPI_CHECK(status, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
SPI_CHECK_HIGH_THROUGHPUT(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
SPI_CHECK_HIGH_THROUGHPUT(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
SPI_CHECK_HIGH_THROUGHPUT(SPI_SLAVE_MODE == spi_object[host]->mode, "this function must used by spi slave mode", ESP_FAIL);
SPI_CHECK_HIGH_THROUGHPUT(status, "parameter pointer is empty", ESP_ERR_INVALID_ARG);
ENTER_CRITICAL();
ENTER_CRITICAL_HIGH_THROUGHPUT();
SPI[host]->rd_status.val = *status;
EXIT_CRITICAL();
EXIT_CRITICAL_HIGH_THROUGHPUT();
return ESP_OK;
}
static esp_err_t spi_master_trans(spi_host_t host, spi_trans_t trans)
static esp_err_t SPI_HIGH_THROUGHPUT_ATTR spi_master_trans(spi_host_t host, spi_trans_t *trans)
{
SPI_CHECK(trans.bits.cmd <= 16, "spi cmd must be shorter than 16 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK(trans.bits.addr <= 32, "spi addr must be shorter than 32 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK(trans.bits.mosi <= 512, "spi mosi must be shorter than 512 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK(trans.bits.miso <= 512, "spi miso must be shorter than 512 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK_HIGH_THROUGHPUT(trans->bits.cmd <= 16, "spi cmd must be shorter than 16 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK_HIGH_THROUGHPUT(trans->bits.addr <= 32, "spi addr must be shorter than 32 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK_HIGH_THROUGHPUT(trans->bits.mosi <= 512, "spi mosi must be shorter than 512 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK_HIGH_THROUGHPUT(trans->bits.miso <= 512, "spi miso must be shorter than 512 bits", ESP_ERR_INVALID_ARG);
int x, y;
// Waiting for an incomplete transfer
while (SPI[host]->cmd.usr);
ENTER_CRITICAL();
ENTER_CRITICAL_HIGH_THROUGHPUT();
// Set the cmd length and transfer cmd
if (trans.bits.cmd && trans.cmd) {
if (trans->bits.cmd && trans->cmd) {
SPI[host]->user.usr_command = 1;
SPI[host]->user2.usr_command_bitlen = trans.bits.cmd - 1;
SPI[host]->user2.usr_command_value = *trans.cmd;
SPI[host]->user2.usr_command_bitlen = trans->bits.cmd - 1;
SPI[host]->user2.usr_command_value = *trans->cmd;
} else {
SPI[host]->user.usr_command = 0;
}
// Set addr length and transfer addr
if (trans.bits.addr && trans.addr) {
if (trans->bits.addr && trans->addr) {
SPI[host]->user.usr_addr = 1;
SPI[host]->user1.usr_addr_bitlen = trans.bits.addr - 1;
SPI[host]->addr = *trans.addr;
SPI[host]->user1.usr_addr_bitlen = trans->bits.addr - 1;
SPI[host]->addr = *trans->addr;
} else {
SPI[host]->user.usr_addr = 0;
}
// Set mosi length and transmit mosi
if (trans.bits.mosi && trans.mosi) {
if (trans->bits.mosi && trans->mosi) {
SPI[host]->user.usr_mosi = 1;
SPI[host]->user1.usr_mosi_bitlen = trans.bits.mosi - 1;
for (x = 0; x < trans.bits.mosi; x += 32) {
y = x / 32;
SPI[host]->data_buf[y] = trans.mosi[y];
SPI[host]->user1.usr_mosi_bitlen = trans->bits.mosi - 1;
if ((uint32_t)(trans->mosi) % 4 == 0) {
for (x = 0; x < trans->bits.mosi; x += 32) {
y = x / 32;
SPI[host]->data_buf[y] = trans->mosi[y];
}
} else {
ESP_LOGW(TAG,"Using unaligned data may reduce transmission efficiency");
memset(spi_object[host]->buf, 0, sizeof(uint32_t) * 16);
memcpy(spi_object[host]->buf, trans->mosi, trans->bits.mosi / 8 + (trans->bits.mosi % 8) ? 1 : 0);
for (x = 0; x < trans->bits.mosi; x += 32) {
y = x / 32;
SPI[host]->data_buf[y] = spi_object[host]->buf[y];
}
}
} else {
SPI[host]->user.usr_mosi = 0;
}
// Set the length of the miso
if (trans.bits.miso && trans.miso) {
if (trans->bits.miso && trans->miso) {
SPI[host]->user.usr_miso = 1;
SPI[host]->user1.usr_miso_bitlen = trans.bits.miso - 1;
SPI[host]->user1.usr_miso_bitlen = trans->bits.miso - 1;
} else {
SPI[host]->user.usr_miso = 0;
}
@ -474,74 +521,98 @@ static esp_err_t spi_master_trans(spi_host_t host, spi_trans_t trans)
SPI[host]->cmd.usr = 1;
// Receive miso data
if (trans.bits.miso && trans.miso) {
if (trans->bits.miso && trans->miso) {
while (SPI[host]->cmd.usr);
for (x = 0; x < trans.bits.miso; x += 32) {
y = x / 32;
trans.miso[y] = SPI[host]->data_buf[y];
if ((uint32_t)(trans->miso) % 4 == 0) {
for (x = 0; x < trans->bits.miso; x += 32) {
y = x / 32;
trans->miso[y] = SPI[host]->data_buf[y];
}
} else {
ESP_LOGW(TAG,"Using unaligned data may reduce transmission efficiency");
memset(spi_object[host]->buf, 0, sizeof(uint32_t) * 16);
for (x = 0; x < trans->bits.miso; x += 32) {
y = x / 32;
spi_object[host]->buf[y] = SPI[host]->data_buf[y];
}
memcpy(trans->miso, spi_object[host]->buf, trans->bits.miso / 8 + (trans->bits.miso % 8) ? 1 : 0);
}
}
EXIT_CRITICAL();
EXIT_CRITICAL_HIGH_THROUGHPUT();
return ESP_OK;
}
static esp_err_t spi_slave_trans(spi_host_t host, spi_trans_t trans)
static esp_err_t SPI_HIGH_THROUGHPUT_ATTR spi_slave_trans(spi_host_t host, spi_trans_t *trans)
{
SPI_CHECK(trans.bits.cmd >= 3 && trans.bits.cmd <= 16, "spi cmd must be longer than 3 bits and shorter than 16 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK(trans.bits.addr >= 1 && trans.bits.addr <= 32, "spi addr must be longer than 1 bits and shorter than 32 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK(trans.bits.miso <= 256, "spi miso must be shorter than 256 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK(trans.bits.mosi <= 256, "spi mosi must be shorter than 256 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK_HIGH_THROUGHPUT(trans->bits.cmd >= 3 && trans->bits.cmd <= 16, "spi cmd must be longer than 3 bits and shorter than 16 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK_HIGH_THROUGHPUT(trans->bits.addr >= 1 && trans->bits.addr <= 32, "spi addr must be longer than 1 bits and shorter than 32 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK_HIGH_THROUGHPUT(trans->bits.miso <= 512, "spi miso must be shorter than 512 bits", ESP_ERR_INVALID_ARG);
SPI_CHECK_HIGH_THROUGHPUT(trans->bits.mosi <= 512, "spi mosi must be shorter than 512 bits", ESP_ERR_INVALID_ARG);
int x, y;
ENTER_CRITICAL();
ENTER_CRITICAL_HIGH_THROUGHPUT();
// Set cmd length and receive cmd
SPI[host]->user2.usr_command_bitlen = trans.bits.cmd - 1;
SPI[host]->user2.usr_command_bitlen = trans->bits.cmd - 1;
if (trans.cmd) {
*trans.cmd = SPI[host]->user2.usr_command_value;
if (trans->cmd) {
*trans->cmd = SPI[host]->user2.usr_command_value;
}
// Set addr length and transfer addr
SPI[host]->slave1.wr_addr_bitlen = trans.bits.addr - 1;
SPI[host]->slave1.rd_addr_bitlen = trans.bits.addr - 1;
SPI[host]->slave1.wr_addr_bitlen = trans->bits.addr - 1;
SPI[host]->slave1.rd_addr_bitlen = trans->bits.addr - 1;
if (trans.addr) {
*trans.addr = SPI[host]->addr;
if (trans->addr) {
*trans->addr = SPI[host]->addr;
}
// Set the length of the miso and transfer the miso
if (trans.bits.miso && trans.miso) {
for (x = 0; x < trans.bits.miso; x += 32) {
y = x / 32;
SPI[host]->data_buf[y + 8] = trans.miso[y];
if (trans->bits.miso && trans->miso) {
if ((uint32_t)(trans->miso) % 4 == 0) {
for (x = 0; x < trans->bits.miso; x += 32) {
y = x / 32;
SPI[host]->data_buf[y] = trans->miso[y];
}
} else {
ESP_LOGW(TAG,"Using unaligned data may reduce transmission efficiency");
memset(spi_object[host]->buf, 0, sizeof(uint32_t) * 16);
memcpy(spi_object[host]->buf, trans->miso, trans->bits.miso / 8 + (trans->bits.miso % 8) ? 1 : 0);
for (x = 0; x < trans->bits.miso; x += 32) {
y = x / 32;
SPI[host]->data_buf[y] = spi_object[host]->buf[y];
}
}
}
// Call the event callback function to send a transfer start event
if (spi_object[host]->event_cb) {
spi_object[host]->event_cb(SPI_TRANS_START_EVENT, NULL);
}
// Receive mosi data
if (trans.bits.mosi && trans.mosi) {
for (x = 0; x < trans.bits.mosi; x += 32) {
y = x / 32;
trans.mosi[y] = SPI[host]->data_buf[y];
if (trans->bits.mosi && trans->mosi) {
if ((uint32_t)(trans->mosi) % 4 == 0) {
for (x = 0; x < trans->bits.mosi; x += 32) {
y = x / 32;
trans->mosi[y] = SPI[host]->data_buf[y];
}
} else {
ESP_LOGW(TAG,"Using unaligned data may reduce transmission efficiency");
memset(spi_object[host]->buf, 0, sizeof(uint32_t) * 16);
for (x = 0; x < trans->bits.mosi; x += 32) {
y = x / 32;
spi_object[host]->buf[y] = SPI[host]->data_buf[y];
}
memcpy(trans->mosi, spi_object[host]->buf, trans->bits.mosi / 8 + (trans->bits.mosi % 8) ? 1 : 0);
}
}
EXIT_CRITICAL();
EXIT_CRITICAL_HIGH_THROUGHPUT();
return ESP_OK;
}
static esp_err_t spi_trans_static(spi_host_t host, spi_trans_t trans)
static esp_err_t SPI_HIGH_THROUGHPUT_ATTR spi_trans_static(spi_host_t host, spi_trans_t *trans)
{
int ret;
if (SPI_MASTER_MODE == spi_object[host]->mode) {
ret = spi_master_trans(host, trans);
} else {
@ -551,17 +622,30 @@ static esp_err_t spi_trans_static(spi_host_t host, spi_trans_t trans)
return ret;
}
esp_err_t spi_trans(spi_host_t host, spi_trans_t trans)
esp_err_t SPI_HIGH_THROUGHPUT_ATTR spi_trans(spi_host_t host, spi_trans_t *trans)
{
SPI_CHECK(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
SPI_CHECK(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
SPI_CHECK(trans.bits.val, "trans bits is empty", ESP_ERR_INVALID_ARG);
SPI_CHECK_HIGH_THROUGHPUT(host < SPI_NUM_MAX, "host num error", ESP_ERR_INVALID_ARG);
SPI_CHECK_HIGH_THROUGHPUT(spi_object[host], "spi has not been initialized yet", ESP_FAIL);
SPI_CHECK_HIGH_THROUGHPUT(trans->bits.val, "trans bits is empty", ESP_ERR_INVALID_ARG);
int ret;
xSemaphoreTake(spi_object[host]->trans_mux, portMAX_DELAY);
ret = spi_trans_static(host, trans);
xSemaphoreGive(spi_object[host]->trans_mux);
if (xPortInIsrContext()) {
/* In ISR Context */
BaseType_t higher_task_woken = false;
if (xSemaphoreTakeFromISR(spi_object[host]->trans_mux, NULL) != pdTRUE) {
return ESP_FAIL;
}
ret = spi_trans_static(host, trans);
xSemaphoreGiveFromISR(spi_object[host]->trans_mux, &higher_task_woken);
if (higher_task_woken) {
portYIELD_FROM_ISR();
}
}
else {
xSemaphoreTake(spi_object[host]->trans_mux, portMAX_DELAY);
ret = spi_trans_static(host, trans);
xSemaphoreGive(spi_object[host]->trans_mux);
}
return ret;
}
@ -569,7 +653,7 @@ static IRAM_ATTR void spi_intr(void *arg)
{
spi_host_t host;
uint32_t trans_done;
uint32_t cnt = 0;
if (READ_PERI_REG(DPORT_SPI_INT_STATUS_REG) & DPORT_SPI_INT_STATUS_SPI0) { // DPORT_SPI_INT_STATUS_SPI0
trans_done = SPI0.slave.val & 0x1F;
SPI0.slave.val &= ~0x3FF;
@ -577,13 +661,25 @@ static IRAM_ATTR void spi_intr(void *arg)
} else if (READ_PERI_REG(DPORT_SPI_INT_STATUS_REG) & DPORT_SPI_INT_STATUS_SPI1) { // DPORT_SPI_INT_STATUS_SPI1
trans_done = SPI1.slave.val & 0x1F;
SPI1.slave.val &= ~0x1F;
// Hardware issues: We need to wait for the hardware to clear the registers successfully.
while ((SPI1.slave.val & 0x1F) != 0) {
if (cnt >= 50) {
ets_printf("WARNING: waiting too much time, maybe error\r\n");
cnt = 0;
}
SPI1.slave.val &= ~0x1F;
cnt++;
}
host = HSPI_HOST;
} else {
return;
}
if (spi_object[host]) {
if (spi_object[host]->event_cb) {
// Hardware has no interrupt flag, which can be generated by software.
trans_done &= spi_object[host]->intr_enable.val;
if (spi_object[host]->event_cb && trans_done != 0) {
spi_object[host]->event_cb(SPI_TRANS_DONE_EVENT, &trans_done);
}
}
@ -621,7 +717,10 @@ esp_err_t spi_deinit(spi_host_t host)
if (spi_object[host]->trans_mux) {
vSemaphoreDelete(spi_object[host]->trans_mux);
}
free(spi_object[host]);
heap_caps_free(spi_object[host]->buf);
spi_object[host]->buf = NULL;
heap_caps_free(spi_object[host]);
spi_object[host] = NULL;
return ESP_OK;
@ -633,20 +732,25 @@ esp_err_t spi_init(spi_host_t host, spi_config_t *config)
SPI_CHECK(host > CSPI_HOST, "CSPI_HOST can't support now", ESP_FAIL);
SPI_CHECK(NULL == spi_object[host], "spi has been initialized", ESP_FAIL);
spi_object[host] = (spi_object_t *)malloc(sizeof(spi_object_t));
spi_object[host] = (spi_object_t *)heap_caps_malloc(sizeof(spi_object_t), MALLOC_CAP_8BIT);
SPI_CHECK(spi_object[host], "malloc fail", ESP_ERR_NO_MEM);
spi_object[host]->trans_mux = xSemaphoreCreateMutex();
if (NULL == spi_object[host]->trans_mux) {
#ifdef CONFIG_ESP8266_HSPI_HIGH_THROUGHPUT
spi_object[host]->buf = (uint32_t *)heap_caps_malloc(sizeof(uint32_t) * 16, MALLOC_CAP_8BIT);
#else
spi_object[host]->buf = (uint32_t *)heap_caps_malloc(sizeof(uint32_t) * 16, MALLOC_CAP_32BIT);
#endif
if (NULL == spi_object[host]->trans_mux || NULL == spi_object[host]->buf) {
spi_deinit(host);
SPI_CHECK(false, "Semaphore create fail", ESP_ERR_NO_MEM);
SPI_CHECK(false, "no memory", ESP_ERR_NO_MEM);
}
uint16_t dummy_bitlen = 0;
spi_set_event_callback(host, &config->event_cb);
spi_set_mode(host, &config->mode);
spi_set_interface(host, &config->interface);
spi_set_clk_div(host, &config->clk_div);
spi_set_dummy(host, &dummy_bitlen);
spi_set_intr_enable(host, &config->intr_enable);
spi_intr_register(spi_intr, NULL);
spi_intr_enable();
@ -654,6 +758,5 @@ esp_err_t spi_init(spi_host_t host, spi_config_t *config)
if (spi_object[host]->event_cb) {
spi_object[host]->event_cb(SPI_INIT_EVENT, NULL);
}
return ESP_OK;
}
}

88
components/esp8266/include/driver/hspi_logic_layer.h Normal file
View File

@ -0,0 +1,88 @@
// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include "esp_err.h"
#include "driver/gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Receive SPI data
*
* @param data Data buffer to receive
* @param len Data length
* @param xTicksToWait Ticks to wait until receive data; use portMAX_DELAY to
* never time out.
* @return
* - Actual length received
*/
uint32_t hspi_slave_logic_read_data(uint8_t*data, uint32_t len, TickType_t xTicksToWait);
/**
* @brief Send SPI data
*
* @param data Data buffer to send
* @param len Data length
* @param xTicksToWait Ticks to wait until send data; use portMAX_DELAY to
* never time out.
* @return
* - Actual length received
*/
uint32_t hspi_slave_logic_write_data(uint8_t*data, uint32_t len, TickType_t xTicksToWait);
/**
* @brief Create a SPI device to transmit SPI data
*
* @param trigger_pin The pin used for handshake
* @param trigger_level The number of bytes that must be in the stream
* buffer before a task that is blocked on the stream buffer to wait for data is
* moved out of the blocked state. For example, if a task is blocked on a read
* of an empty stream buffer that has a trigger level of 1 then the task will be
* unblocked when a single byte is written to the buffer or the task's block
* time expires. As another example, if a task is blocked on a read of an empty
* stream buffer that has a trigger level of 10 then the task will not be
* unblocked until the stream buffer contains at least 10 bytes or the task's
* block time expires. If a reading task's block time expires before the
* trigger level is reached then the task will still receive however many bytes
* are actually available. Setting a trigger level of 0 will result in a
* trigger level of 1 being used. It is not valid to specify a trigger level
* that is greater than the buffer size.
* @param tx_buffer_size The total number of bytes the send stream buffer will be
* able to hold at any one time.
* @param rx_buffer_size The total number of bytes the receive stream buffer will be
* able to hold at any one time.
*
* @return
* - ESP_OK Success
* - ESP_ERR_NO_MEM No memory
*/
esp_err_t hspi_slave_logic_device_create(gpio_num_t trigger_pin, uint32_t trigger_level,uint32_t tx_buffer_size, uint32_t rx_buffer_size);
/**
* @brief Delete the SPI slave bus
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_STATE SPI slave already deleted
*/
esp_err_t hspi_slave_logic_device_delete(void);
#ifdef __cplusplus
}
#endif

10
components/esp8266/include/driver/spi.h
View File

@ -36,7 +36,7 @@ extern "C" {
#define SPI_BYTE_ORDER_LSB_FIRST 0
/* SPI default bus interface parameter definition */
#define SPI_DEFAULT_INTERFACE 0x1F0 /* CS_EN:1, MISO_EN:1, MOSI_EN:1, BYTE_TX_ORDER:1, BYTE_TX_ORDER:1, BIT_RX_ORDER:0, BIT_TX_ORDER:0, CPHA:0, CPOL:0 */
#define SPI_DEFAULT_INTERFACE 0x1C0 /* CS_EN:1, MISO_EN:1, MOSI_EN:1, BYTE_TX_ORDER:0, BYTE_TX_ORDER:0, BIT_RX_ORDER:0, BIT_TX_ORDER:0, CPHA:0, CPOL:0 */
/* SPI master default interrupt enable definition */
#define SPI_MASTER_DEFAULT_INTR_ENABLE 0x10 /* TRANS_DONE: true, WRITE_STATUS: false, READ_STATUS: false, WRITE_BUFFER: false, READ_BUFFER: false */
@ -140,8 +140,8 @@ typedef union {
typedef struct {
uint16_t *cmd; /*!< SPI transmission command */
uint32_t *addr; /*!< SPI transmission address */
uint32_t *mosi; /*!< SPI transmission MOSI buffer */
uint32_t *miso; /*!< SPI transmission MISO buffer */
uint32_t *mosi; /*!< SPI transmission MOSI buffer, in order to improve the transmission efficiency, it is recommended that the external incoming data is (uint32_t *) type data, do not use other type data. */
uint32_t *miso; /*!< SPI transmission MISO buffer, in order to improve the transmission efficiency, it is recommended that the external incoming data is (uint32_t *) type data, do not use other type data. */
union {
struct {
uint32_t cmd: 5; /*!< SPI transmission command bits */
@ -403,14 +403,14 @@ esp_err_t spi_slave_set_status(spi_host_t host, uint32_t *status);
* - CSPI_HOST SPI0
* - HSPI_HOST SPI1
*
* @param trans Transmission parameter structure
* @param trans Pointer to transmission parameter structure
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
* - ESP_FAIL spi has not been initialized yet
*/
esp_err_t spi_trans(spi_host_t host, spi_trans_t trans);
esp_err_t spi_trans(spi_host_t host, spi_trans_t *trans);
/**
* @brief Deinit the spi