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Merge branch 'feature/spi_ram' into 'master'

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feature(spi_ram): add spi ram

See merge request sdk/ESP8266_RTOS_SDK!887
This commit is contained in:
Wu Jian Gang
2019-04-18 14:24:57 +08:00
parent 33463b3ddf 0b0d82ca19
commit 6ab1c01c53
6 changed files with 974 additions and 4 deletions
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8
components/esp8266/include/esp8266/spi_struct.h
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@ -113,10 +113,10 @@ typedef volatile struct {
uint32_t reserved8: 2; /*reserved*/
uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian*/
uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/
uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/
uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/
uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/
uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/
uint32_t fwrite_dual: 1; /*In the write operations write-data phase apply 2 signals*/
uint32_t fwrite_quad: 1; /*In the write operations write-data phase apply 4 signals*/
uint32_t fwrite_dio: 1; /*In the write operations address phase and write-data phase apply 2 signals.*/
uint32_t fwrite_qio: 1; /*In the write operations address phase and write-data phase apply 4 signals.*/
uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/
uint32_t reserved17: 7; /*reserved*/
uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/