diff --git a/components/esp8266/include/esp8266/eagle_soc.h b/components/esp8266/include/esp8266/eagle_soc.h
index 0a83c636..d1345553 100644
--- a/components/esp8266/include/esp8266/eagle_soc.h
+++ b/components/esp8266/include/esp8266/eagle_soc.h
@@ -117,6 +117,7 @@
 //}}
 
 //Interrupt remap control registers define{{
+#define NMI_INT_ENABLE_REG          (PERIPHS_DPORT_BASEADDR)
 #define EDGE_INT_ENABLE_REG         (PERIPHS_DPORT_BASEADDR + 0x04)
 #define WDT_EDGE_INT_ENABLE()       SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT0)
 #define TM1_EDGE_INT_ENABLE()       SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
diff --git a/components/freertos/port/esp8266/port.c b/components/freertos/port/esp8266/port.c
index b0c314d3..ad906957 100644
--- a/components/freertos/port/esp8266/port.c
+++ b/components/freertos/port/esp8266/port.c
@@ -267,24 +267,36 @@ void esp_dport_close_nmi(void)
 void IRAM_ATTR vPortETSIntrLock(void)
 {
     if (NMIIrqIsOn == 0) {
+        uint32_t regval = REG_READ(NMI_INT_ENABLE_REG);
+
+        REG_WRITE(NMI_INT_ENABLE_REG, 0);
+
         vPortEnterCritical();
         if (!ESP_NMI_IS_CLOSED()) {
             do {
                 REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT);
             } while(REG_READ(INT_ENA_WDEV) != WDEV_TSF0_REACH_INT);
         }
+
+        REG_WRITE(NMI_INT_ENABLE_REG, regval);
     }
 }
 
 void IRAM_ATTR vPortETSIntrUnlock(void)
 {
     if (NMIIrqIsOn == 0) {
+        uint32_t regval = REG_READ(NMI_INT_ENABLE_REG);
+
+        REG_WRITE(NMI_INT_ENABLE_REG, 0);
+
         if (!ESP_NMI_IS_CLOSED()) {
             extern uint32_t WDEV_INTEREST_EVENT;
 
             REG_WRITE(INT_ENA_WDEV, WDEV_INTEREST_EVENT);
         }
         vPortExitCritical();
+
+        REG_WRITE(NMI_INT_ENABLE_REG, regval);
     }
 }