diff --git a/components/esp8266/include/esp8266/eagle_soc.h b/components/esp8266/include/esp8266/eagle_soc.h
index 490ecab9..0a83c636 100644
--- a/components/esp8266/include/esp8266/eagle_soc.h
+++ b/components/esp8266/include/esp8266/eagle_soc.h
@@ -123,6 +123,8 @@
 #define TM1_EDGE_INT_DISABLE()      CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
 //}}
 
+#define INT_ENA_WDEV                0x3ff20c18
+#define WDEV_TSF0_REACH_INT         (BIT(27))
 
 //Watch dog reg {{
 #define PERIPHS_WDT_BASEADDR        0x60000900
diff --git a/components/esp8266/include/rom/ets_sys.h b/components/esp8266/include/rom/ets_sys.h
index d9057d0a..4a8505ef 100644
--- a/components/esp8266/include/rom/ets_sys.h
+++ b/components/esp8266/include/rom/ets_sys.h
@@ -53,39 +53,9 @@ typedef enum {
     CANCEL,
 } STATUS;
 
-extern char NMIIrqIsOn;
-extern uint32_t WDEV_INTEREST_EVENT;
+void vPortETSIntrLock(void);
 
-#define INT_ENA_WDEV        0x3ff20c18
-#define WDEV_TSF0_REACH_INT (BIT(27))
-
-#define ETS_NMI_LOCK()  \
-    do {    \
-        do {    \
-            REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT);   \
-        } while(REG_READ(INT_ENA_WDEV) != WDEV_TSF0_REACH_INT); \
-    } while (0)
-
-#define ETS_NMI_UNLOCK()    \
-    do {    \
-        REG_WRITE(INT_ENA_WDEV, WDEV_INTEREST_EVENT);   \
-    } while (0)
-
-#define ETS_INTR_LOCK() do {    \
-    if (NMIIrqIsOn == 0) { \
-        vPortEnterCritical();   \
-        do {    \
-            REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT);   \
-        } while(REG_READ(INT_ENA_WDEV) != WDEV_TSF0_REACH_INT); \
-    }   \
-    } while(0)
-
-#define ETS_INTR_UNLOCK()   do {    \
-    if (NMIIrqIsOn == 0) { \
-        REG_WRITE(INT_ENA_WDEV, WDEV_INTEREST_EVENT);   \
-        vPortExitCritical(); \
-    }   \
-    } while(0)
+void vPortETSIntrUnlock(void);
 
 #define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
 #define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
diff --git a/components/esp8266/lib/VERSION b/components/esp8266/lib/VERSION
index 1c5cab17..79814977 100644
--- a/components/esp8266/lib/VERSION
+++ b/components/esp8266/lib/VERSION
@@ -1,7 +1,7 @@
 gwen:
-    core:       33a48e5
-    net80211:   71f5b94
-    pp:         c32a629
+    core:       381d974
+    net80211:   381d974
+    pp:         381d974
     wpa:        33a48e5
     espnow:     da96924
     wps:        da96924
diff --git a/components/esp8266/lib/libcore.a b/components/esp8266/lib/libcore.a
index 29659cd9..39e282fa 100644
Binary files a/components/esp8266/lib/libcore.a and b/components/esp8266/lib/libcore.a differ
diff --git a/components/esp8266/lib/libcore_dbg.a b/components/esp8266/lib/libcore_dbg.a
index 5a796588..1bf879cf 100644
Binary files a/components/esp8266/lib/libcore_dbg.a and b/components/esp8266/lib/libcore_dbg.a differ
diff --git a/components/esp8266/lib/libpp.a b/components/esp8266/lib/libpp.a
index 125fc5fb..b6d3f40e 100644
Binary files a/components/esp8266/lib/libpp.a and b/components/esp8266/lib/libpp.a differ
diff --git a/components/esp8266/lib/libpp_dbg.a b/components/esp8266/lib/libpp_dbg.a
index d22da73a..f97267f1 100644
Binary files a/components/esp8266/lib/libpp_dbg.a and b/components/esp8266/lib/libpp_dbg.a differ
diff --git a/components/freertos/port/esp8266/port.c b/components/freertos/port/esp8266/port.c
index 0aced897..6e4e7091 100644
--- a/components/freertos/port/esp8266/port.c
+++ b/components/freertos/port/esp8266/port.c
@@ -50,7 +50,7 @@
 #define SET_STKREG(r,v)     sp[(r) >> 2] = (uint32_t)(v)
 #define PORT_ASSERT(x)      do { if (!(x)) {ets_printf("%s %u\n", "rtos_port", __LINE__); while(1){}; }} while (0)
 
-extern char NMIIrqIsOn;
+extern uint8_t NMIIrqIsOn;
 static int SWReq = 0;
 
 uint32_t cpu_sr;
@@ -250,12 +250,22 @@ void show_critical_info(void)
 
 void IRAM_ATTR vPortETSIntrLock(void)
 {
-    ETS_INTR_LOCK();
+    if (NMIIrqIsOn == 0) {
+        vPortEnterCritical();
+        do {
+            REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT);
+        } while(REG_READ(INT_ENA_WDEV) != WDEV_TSF0_REACH_INT);
+    }
 }
 
 void IRAM_ATTR vPortETSIntrUnlock(void)
 {
-    ETS_INTR_UNLOCK();
+    if (NMIIrqIsOn == 0) {
+        extern uint32_t WDEV_INTEREST_EVENT;
+
+        REG_WRITE(INT_ENA_WDEV, WDEV_INTEREST_EVENT);
+        vPortExitCritical();
+    }
 }
 
 /*