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feat(esp2866): Move driver to esp8266 of components

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Dong Heng
2018-04-08 10:38:18 +08:00
parent 3a008481cb
commit 3e1f0b973e
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307
components/esp8266/include/driver/gpio.h Normal file
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/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __GPIO_H__
#define __GPIO_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "esp8266/gpio_register.h"
#define GPIO_Pin_0 (BIT(0)) /* Pin 0 selected */
#define GPIO_Pin_1 (BIT(1)) /* Pin 1 selected */
#define GPIO_Pin_2 (BIT(2)) /* Pin 2 selected */
#define GPIO_Pin_3 (BIT(3)) /* Pin 3 selected */
#define GPIO_Pin_4 (BIT(4)) /* Pin 4 selected */
#define GPIO_Pin_5 (BIT(5)) /* Pin 5 selected */
#define GPIO_Pin_6 (BIT(6)) /* Pin 6 selected */
#define GPIO_Pin_7 (BIT(7)) /* Pin 7 selected */
#define GPIO_Pin_8 (BIT(8)) /* Pin 8 selected */
#define GPIO_Pin_9 (BIT(9)) /* Pin 9 selected */
#define GPIO_Pin_10 (BIT(10)) /* Pin 10 selected */
#define GPIO_Pin_11 (BIT(11)) /* Pin 11 selected */
#define GPIO_Pin_12 (BIT(12)) /* Pin 12 selected */
#define GPIO_Pin_13 (BIT(13)) /* Pin 13 selected */
#define GPIO_Pin_14 (BIT(14)) /* Pin 14 selected */
#define GPIO_Pin_15 (BIT(15)) /* Pin 15 selected */
#define GPIO_Pin_All (0xFFFF) /* All pins selected */
#define GPIO_PIN_REG_0 PERIPHS_IO_MUX_GPIO0_U
#define GPIO_PIN_REG_1 PERIPHS_IO_MUX_U0TXD_U
#define GPIO_PIN_REG_2 PERIPHS_IO_MUX_GPIO2_U
#define GPIO_PIN_REG_3 PERIPHS_IO_MUX_U0RXD_U
#define GPIO_PIN_REG_4 PERIPHS_IO_MUX_GPIO4_U
#define GPIO_PIN_REG_5 PERIPHS_IO_MUX_GPIO5_U
#define GPIO_PIN_REG_6 PERIPHS_IO_MUX_SD_CLK_U
#define GPIO_PIN_REG_7 PERIPHS_IO_MUX_SD_DATA0_U
#define GPIO_PIN_REG_8 PERIPHS_IO_MUX_SD_DATA1_U
#define GPIO_PIN_REG_9 PERIPHS_IO_MUX_SD_DATA2_U
#define GPIO_PIN_REG_10 PERIPHS_IO_MUX_SD_DATA3_U
#define GPIO_PIN_REG_11 PERIPHS_IO_MUX_SD_CMD_U
#define GPIO_PIN_REG_12 PERIPHS_IO_MUX_MTDI_U
#define GPIO_PIN_REG_13 PERIPHS_IO_MUX_MTCK_U
#define GPIO_PIN_REG_14 PERIPHS_IO_MUX_MTMS_U
#define GPIO_PIN_REG_15 PERIPHS_IO_MUX_MTDO_U
#define GPIO_PIN_REG(i) \
(i==0) ? GPIO_PIN_REG_0: \
(i==1) ? GPIO_PIN_REG_1: \
(i==2) ? GPIO_PIN_REG_2: \
(i==3) ? GPIO_PIN_REG_3: \
(i==4) ? GPIO_PIN_REG_4: \
(i==5) ? GPIO_PIN_REG_5: \
(i==6) ? GPIO_PIN_REG_6: \
(i==7) ? GPIO_PIN_REG_7: \
(i==8) ? GPIO_PIN_REG_8: \
(i==9) ? GPIO_PIN_REG_9: \
(i==10)? GPIO_PIN_REG_10: \
(i==11)? GPIO_PIN_REG_11: \
(i==12)? GPIO_PIN_REG_12: \
(i==13)? GPIO_PIN_REG_13: \
(i==14)? GPIO_PIN_REG_14: \
GPIO_PIN_REG_15
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_ADDRESS + i*4)
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
typedef enum {
GPIO_PIN_INTR_DISABLE = 0, /**< disable GPIO interrupt */
GPIO_PIN_INTR_POSEDGE = 1, /**< GPIO interrupt type : rising edge */
GPIO_PIN_INTR_NEGEDGE = 2, /**< GPIO interrupt type : falling edge */
GPIO_PIN_INTR_ANYEDGE = 3, /**< GPIO interrupt type : bothe rising and falling edge */
GPIO_PIN_INTR_LOLEVEL = 4, /**< GPIO interrupt type : low level */
GPIO_PIN_INTR_HILEVEL = 5 /**< GPIO interrupt type : high level */
} GPIO_INT_TYPE;
typedef enum {
GPIO_Mode_Input = 0x0, /**< GPIO mode : Input */
GPIO_Mode_Out_OD, /**< GPIO mode : Output_OD */
GPIO_Mode_Output , /**< GPIO mode : Output */
GPIO_Mode_Sigma_Delta , /**< GPIO mode : Sigma_Delta */
} GPIOMode_TypeDef;
typedef enum {
GPIO_PullUp_DIS = 0x0, /**< disable GPIO pullup */
GPIO_PullUp_EN = 0x1, /**< enable GPIO pullup */
} GPIO_Pullup_IF;
typedef struct {
uint16 GPIO_Pin; /**< GPIO pin */
GPIOMode_TypeDef GPIO_Mode; /**< GPIO mode */
GPIO_Pullup_IF GPIO_Pullup; /**< GPIO pullup */
GPIO_INT_TYPE GPIO_IntrType; /**< GPIO interrupt type */
} GPIO_ConfigTypeDef;
/** \defgroup Driver_APIs Driver APIs
* @brief Driver APIs
*/
/** @addtogroup Driver_APIs
* @{
*/
/** \defgroup GPIO_Driver_APIs GPIO Driver APIs
* @brief GPIO APIs
*/
/** @addtogroup GPIO_Driver_APIs
* @{
*/
/**
* @brief Set GPIO pin output level.
*
* @param gpio_no : The GPIO sequence number.
* @param bit_value : GPIO pin output level.
*
* @return null
*/
#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
gpio_output_conf(bit_value<<gpio_no, ((~bit_value)&0x01)<<gpio_no, 1<<gpio_no, 0)
/**
* @brief Set GPIO pin output level.
*
* @param gpio_bits : The GPIO bit number.
* @param bit_value : GPIO pin output level.
*
* @return null
*/
#define GPIO_OUTPUT(gpio_bits, bit_value) \
if(bit_value) gpio_output_conf(gpio_bits, 0, gpio_bits, 0);\
else gpio_output_conf(0, gpio_bits, gpio_bits, 0)
/**
* @brief Disable GPIO pin output.
*
* @param gpio_no : The GPIO sequence number.
*
* @return null
*/
#define GPIO_DIS_OUTPUT(gpio_no) gpio_output_conf(0, 0, 0, 1<<gpio_no)
/**
* @brief Enable GPIO pin intput.
*
* @param gpio_bits : The GPIO bit number.
*
* @return null
*/
#define GPIO_AS_INPUT(gpio_bits) gpio_output_conf(0, 0, 0, gpio_bits)
/**
* @brief Enable GPIO pin output.
*
* @param gpio_bits : The GPIO bit number.
*
* @return null
*/
#define GPIO_AS_OUTPUT(gpio_bits) gpio_output_conf(0, 0, gpio_bits, 0)
/**
* @brief Sample the level of GPIO input.
*
* @param gpio_no : The GPIO sequence number.
*
* @return the level of GPIO input
*/
#define GPIO_INPUT_GET(gpio_no) ((gpio_input_get()>>gpio_no)&BIT(0))
/**
* @brief Enable GPIO16 output.
*
* @param null
*
* @return null
*/
void gpio16_output_conf(void);
/**
* @brief Set GPIO16 output level.
*
* @param uint8 value : GPIO16 output level.
*
* @return null
*/
void gpio16_output_set(uint8 value);
/**
* @brief Enable GPIO pin intput.
*
* @param null
*
* @return null
*/
void gpio16_input_conf(void);
/**
* @brief Sample the value of GPIO16 input.
*
* @param null
*
* @return the level of GPIO16 input.
*/
uint8 gpio16_input_get(void);
/**
* @brief Configure Gpio pins out or input.
*
* @param uint32 set_mask : Set the output for the high bit, the
* corresponding bit is 1, the output of high,
* the corresponding bit is 0, do not change the state.
* @param uint32 set_mask : Set the output for the high bit, the
* corresponding bit is 1, the output of low,
* the corresponding bit is 0, do not change the state.
* @param uint32 enable_mask : Enable Output
* @param uint32 disable_mask : Enable Input
*
* @return null
*/
void gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, uint32 disable_mask);
/**
* @brief Register an application-specific interrupt handler for GPIO pin interrupts.
*
* @param void *fn:interrupt handler for GPIO pin interrupts.
* @param void *arg:interrupt handler's arg
*
* @return null
*/
void gpio_intr_handler_register(void *fn, void *arg);
/**
* @brief Configure GPIO wake up to light sleep,Only level way is effective.
*
* @param uint32 i : Gpio sequence number
* @param GPIO_INT_TYPE intr_state : the level of wake up to light sleep
*
* @return null
*/
void gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state);
/**
* @brief Disable GPIO wake up to light sleep.
*
* @param null
*
* @return null
*/
void gpio_pin_wakeup_disable();
/**
* @brief Config interrupt types of GPIO pin.
*
* @param uint32 i : The GPIO sequence number.
* @param GPIO_INT_TYPE intr_state : GPIO interrupt types.
*
* @return null
*/
void gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state);
/**
* @brief Sample the value of GPIO input pins and returns a bitmask.
*
* @param null
*
* @return bitmask of GPIO pins input
*/
uint32 gpio_input_get(void);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __HW_TIMER_H__
#define __HW_TIMER_H__
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup HW_Timer_APIs Hardware timer APIs
* @brief Hardware timer APIs
*
* @attention Hardware timer can not interrupt other ISRs.
*
*/
/** @addtogroup HW_Timer_APIs
* @{
*/
/**
* @brief Initialize the hardware ISR timer.
*
* @param null
*
* @return null
*/
void hw_timer_init(void);
/**
* @brief Set a trigger timer delay to enable this timer.
*
* @param uint32 val : Timing
* - In autoload mode, range : 50 ~ 0x7fffff
* - In non-autoload mode, range : 10 ~ 0x7fffff
*
* @param uint8 req : 0, not autoload; 1, autoload mode.
*
* @return null
*/
void hw_timer_arm(uint32 val, bool req);
/**
* @brief disable this timer.
*
* @param null
*
* @return null
*/
void hw_timer_disarm(void);
/**
* @brief Set timer callback function.
*
* For enabled timer, timer callback has to be set.
*
* @param uint32 val : Timing
* - In autoload mode, range : 50 ~ 0x7fffff
* - In non-autoload mode, range : 10 ~ 0x7fffff
*
* @return null
*/
void hw_timer_set_func(void (* user_hw_timer_cb_set)(void));
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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components/esp8266/include/driver/i2c_master.h Normal file
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#ifndef __I2C_MASTER_H__
#define __I2C_MASTER_H__
#include "esp8266/pin_mux_register.h"
#define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_GPIO2_U
#define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_GPIO4_U
#define I2C_MASTER_SDA_GPIO 2
#define I2C_MASTER_SCL_GPIO 4
#define I2C_MASTER_SDA_FUNC FUNC_GPIO2
#define I2C_MASTER_SCL_FUNC FUNC_GPIO4
//#define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_GPIO2_U
//#define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_GPIO0_U
//#define I2C_MASTER_SDA_GPIO 2
//#define I2C_MASTER_SCL_GPIO 0
//#define I2C_MASTER_SDA_FUNC FUNC_GPIO2
//#define I2C_MASTER_SCL_FUNC FUNC_GPIO0
#if 0
#define I2C_MASTER_GPIO_SET(pin) \
gpio_output_set(1<<pin,0,1<<pin,0)
#define I2C_MASTER_GPIO_CLR(pin) \
gpio_output_set(0,1<<pin,1<<pin,0)
#define I2C_MASTER_GPIO_OUT(pin,val) \
if(val) I2C_MASTER_GPIO_SET(pin);\
else I2C_MASTER_GPIO_CLR(pin)
#endif
#define I2C_MASTER_SDA_HIGH_SCL_HIGH() \
gpio_output_set(1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0)
#define I2C_MASTER_SDA_HIGH_SCL_LOW() \
gpio_output_set(1<<I2C_MASTER_SDA_GPIO, 1<<I2C_MASTER_SCL_GPIO, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0)
#define I2C_MASTER_SDA_LOW_SCL_HIGH() \
gpio_output_set(1<<I2C_MASTER_SCL_GPIO, 1<<I2C_MASTER_SDA_GPIO, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0)
#define I2C_MASTER_SDA_LOW_SCL_LOW() \
gpio_output_set(0, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0)
/** \defgroup Driver_APIs Driver APIs
* @brief Driver APIs
*/
/** @addtogroup Driver_APIs
* @{
*/
/** \defgroup I2C_Driver_APIs I2C_MASTER Driver APIs
* @brief UART driver APIs
*/
/** @addtogroup I2C_MASTER_Driver_APIs
* @{
*/
/**
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
*
* @param null
*
* @return null
*/
void i2c_master_gpio_init(void);
/**
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
*
* @param initilize I2C bus to enable i2c operations.
*
* @return null
*/
void i2c_master_init(void);
#define i2c_master_wait os_delay_us
/**
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
*
* @param set i2c to stop sending state.
*
* @return null
*/
void i2c_master_stop(void);
/**
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
*
* @param set i2c to start sending state.
*
* @return null
*/
void i2c_master_start(void);
/**
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
*
* @param set ack to i2c bus as level value.
*
* @return null
*/
void i2c_master_setAck(uint8 level);
/**
* @brief confirm if peer send ack.
*
* @param null
*
* @return null
*/
uint8 i2c_master_getAck(void);
/**
* @brief read Byte from i2c bus.
*
* @param null
*
* @return the byte which read from i2c bus.
*/
uint8 i2c_master_readByte(void);
/**
* @brief write wrdata value(one byte) into i2c.
*
* @param uint8 wrdata:write value
*
* @return null
*/
void i2c_master_writeByte(uint8 wrdata);
/**
* @brief i2c_master_checkAck.
*
* @param null
*
* @return the result of check ack
*/
bool i2c_master_checkAck(void);
/**
* @brief i2c master send Ack.
*
* @param null
*
* @return null
*/
void i2c_master_send_ack(void);
/**
* @brief i2c master send Nack.
*
* @param null
*
* @return null
*/
void i2c_master_send_nack(void);
/**
* @}
*/
/**
* @}
*/
#endif

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/**
* spi_interface.h
*
* Defines and Macros for the SPI.
*
* Copyright @ 2015 Espressif System Co., Ltd.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are NOT permitted except as agreed by
* Espressif System Co., Ltd.
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
/**
* @file spi_interface.h
* @brief Defines and Macros for the SPI.
*/
#ifndef __SPI_INTERFACE_H__
#define __SPI_INTERFACE_H__
#include "spi_register.h"
#include "c_types.h"
//*****************************************************************************
//
// Make sure all of the definitions in this header have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @brief Defines slave commands. Default value based on slave ESP8266.
*/
#define MASTER_WRITE_DATA_TO_SLAVE_CMD 2
#define MASTER_READ_DATA_FROM_SLAVE_CMD 3
#define MASTER_WRITE_STATUS_TO_SLAVE_CMD 1
#define MASTER_READ_STATUS_FROM_SLAVE_CMD 4
/**
* @brief Support HSPI and SPI module.
*
*/
typedef enum
{
SpiNum_SPI = 0,
SpiNum_HSPI = 1,
} SpiNum;
/**
* @brief The SPI module can work in either master or slave mode.
*
*/
typedef enum
{
SpiMode_Master = 0,
SpiMode_Slave = 1,
} SpiMode;
/**
* @brief SPI sub mode
*
* Support 4 sub modes based on SPI clock polarity and phase.
* SPI_CPOL SPI_CPHA SubMode
* 0 0 0
* 0 1 1
* 1 0 2
* 1 1 3
*/
typedef enum
{
SpiSubMode_0 = 0,
SpiSubMode_1 = 1,
SpiSubMode_2 = 2,
SpiSubMode_3 = 3,
} SpiSubMode;
/**
* @brief The SPI module working speed.
*
* @attention Max speed 80MHz
*
*/
typedef enum
{
SpiSpeed_2MHz = 40 - 1,
SpiSpeed_5MHz = 16 - 1,
SpiSpeed_10MHz = 8 - 1,
SpiSpeed_16MHz = 5 - 1,
SpiSpeed_20MHz = 4 - 1,
} SpiSpeed;
/**
* @brief The SPI mode working speed.
*
*/
typedef enum
{
SpiBitOrder_MSBFirst = 0,
SpiBitOrder_LSBFirst = 1,
} SpiBitOrder;
// @brief SPI interrupt soource defined.
typedef enum
{
SpiIntSrc_TransDoneEn = SPI_TRANS_DONE_EN,
SpiIntSrc_WrStaDoneEn = SPI_SLV_WR_STA_DONE_EN,
SpiIntSrc_RdStaDoneEn = SPI_SLV_RD_STA_DONE_EN,
SpiIntSrc_WrBufDoneEn = SPI_SLV_WR_BUF_DONE_EN,
SpiIntSrc_RdBufDoneEn = SPI_SLV_RD_BUF_DONE_EN,
} SpiIntSrc;
// @brief SPI CS pin.
typedef enum
{
SpiPinCS_0 = 0,
SpiPinCS_1 = 1,
SpiPinCS_2 = 2,
} SpiPinCS;
#pragma pack (1)
/**
* @brief SPI attribute
*/
typedef struct
{
SpiMode mode; ///< Master or slave mode
SpiSubMode subMode; ///< SPI SPI_CPOL SPI_CPHA mode
SpiSpeed speed; ///< SPI Clock
SpiBitOrder bitOrder; ///< SPI bit order
} SpiAttr;
/**
* @brief SPI attribute
*/
typedef struct
{
uint16_t cmd; ///< Command value
uint8_t cmdLen; ///< Command byte length
uint32_t *addr; ///< Point to address value
uint8_t addrLen; ///< Address byte length
uint32_t *data; ///< Point to data buffer
uint8_t dataLen; ///< Data byte length.
} SpiData;
#pragma upack (1)
#define SHOWREG() __ShowRegValue(__func__, __LINE__);
/**
* @brief Print debug information.
*
*/
void __ShowRegValue(const char * func, uint32_t line);
/**
* @brief Initialize SPI module.
*
* @param [in] spiNum
* Indicates which submode to be used, SPI or HSPI.
* @param [in] pAttr
* Pointer to a struct SpiAttr that indicates SPI working attribution.
*
* @return void.
*/
void SPIInit(SpiNum spiNum, SpiAttr* pAttr);
/**
* @brief Set slave address value by master.
*
* @param [in] spiNum
* Indicates which submode to be used, SPI or HSPI.
* @param [in] addr
* Slave address to be set.
*
* @return void.
*/
void SPIMasterCfgAddr(SpiNum spiNum, uint32_t addr);
/**
* @brief Set command value by master.
*
* @param [in] spiNum
* Indicates which submode to be used, SPI or HSPI.
* @param [in] cmd
* Command will be send to slave.
*
* @return void.
*/
void SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd);
/**
* @brief Send data to slave from master.
*
* @param [in] spiNum
* Indicates which submode to be used, SPI or HSPI.
* @param [in] pInData
* Pointer to a strcuture that will be send.
*
* @return int, -1:indicates failure,others indicates success.
*/
int SPIMasterSendData(SpiNum spiNum, SpiData* pInData);
/**
* @brief Receive data from slave by master.
*
* @param [in] spiNum
* Indicates which submode to be used, SPI or HSPI.
* @param [in] pOutData
* Point to data buffer.
*
* @return int, -1:indicates failure,others indicates success.
*
*/
int SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData);
/**
* @brief Load data to slave send buffer.
*
* @param [in] spiNum
* Indicates which submode to be used, SPI or HSPI.
* @param [in] pInData
* Point to data buffer.
* @param [in] outLen
* The number of bytes to be set.
*
* @return int, -1:indicates failure,others indicates success.
*/
int SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uint8_t outLen);
/**
* @brief Receive data by slave.
*
* @param [in] spiNum
* Indicates which submode to be used, SPI or HSPI.
* @param [in] isrFunc
* isrFunc is a pointer to the function to be called when the SPI interrupt occurs.
*
* @return int, -1:indicates failure,others indicates success.
*/
int SPISlaveRecvData(SpiNum spiNum, void(*isrFunc)(void*));
/**
* @brief Set slave status by master.
*
* @param [in] spiNum
* Indicates which submode to be used, SPI or HSPI.
* @param [in] data
* Data will be write to slave SPI_WR_STATUS.
*
* @return void.
*
* @attention Just for ESP8266(slave) register of RD_STATUS or WR_STATUS.
*/
void SPIMasterSendStatus(SpiNum spiNum, uint8_t data);
/**
* @brief Get salve status by master.
*
* @param [in] spiNum
* Indicates which submode to be used, SPI or HSPI.
*
* @return int, -1: indicates failure; other value in slave status.
*
* @attention Just for ESP8266(slave) register of RD_STATUS or WR_STATUS.
*/
int SPIMasterRecvStatus(SpiNum spiNum);
/**
* @brief Select SPI CS pin.
*
* @param [in] spiNum
* Indicates which submode to be used, SPI or HSPI.
* @param [in] pinCs
* Indicates which SPI pin to choose.
*
* @return void.
*/
void SPICsPinSelect(SpiNum spiNum, SpiPinCS pinCs);
/**
* @brief Enable SPI module interrupt source.
*
* @param [in] spiNum
* Indicates which submode to be used, SPI or HSPI.
* @param [in] intSrc
* Indicates which interrupt source to enable.
*
* @return void.
*/
void SPIIntEnable(SpiNum spiNum, SpiIntSrc intSrc);
/**
* @brief Disable SPI module interrupt source.
*
* @param [in] spiNum
* Indicates which submode to be used, SPI or HSPI.
* @param [in] intSrc
* Indicates which interrupt source to disable.
*
* @return void.
*/
void SPIIntDisable(SpiNum spiNum, SpiIntSrc intSrc);
/**
* @brief Clear all of spi interrupt.
*
* @param [in] spiNum
* Indicates which submode to be used, SPI or HSPI.
*
* @return void.
*/
void SPIIntClear(SpiNum spiNum);
#ifdef __cplusplus
}
#endif
#endif // __SPI_INTERFACE_H__

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/*
* Copyright (c) 2010 - 2011 Espressif System
*
*/
#ifndef SPI_REGISTER_H_INCLUDED
#define SPI_REGISTER_H_INCLUDED
#define REG_SPI_BASE(i) (0x60000200-i*0x100)
#define SPI_CMD(i) (REG_SPI_BASE(i) + 0x0)
#define SPI_FLASH_READ BIT31
#define SPI_FLASH_WREN BIT30
#define SPI_FLASH_WRDI BIT29
#define SPI_FLASH_RDID BIT28
#define SPI_FLASH_RDSR BIT27
#define SPI_FLASH_WRSR BIT26
#define SPI_FLASH_PP BIT25
#define SPI_FLASH_SE BIT24
#define SPI_FLASH_BE BIT23
#define SPI_FLASH_CE BIT22
#define SPI_FLASH_RES BIT20
#define SPI_USR (BIT(18))
#define SPI_ADDR(i) (REG_SPI_BASE(i) + 0x4)
#define SPI_CTRL(i) (REG_SPI_BASE(i) + 0x8)
#define SPI_WR_BIT_ORDER (BIT(26))
#define SPI_RD_BIT_ORDER (BIT(25))
#define SPI_QIO_MODE (BIT(24))
#define SPI_DIO_MODE (BIT(23))
#define SPI_QOUT_MODE (BIT(20))
#define SPI_DOUT_MODE (BIT(14))
#define SPI_FASTRD_MODE (BIT(13))
#define SPI_CTRL1(i) (REG_SPI_BASE(i) + 0xc)
#define SPI_CS_HOLD_DELAY 0xf
#define SPI_CS_HOLD_DELAY_S 28
#define SPI_CS_HOLD_DELAY_RES 0xfff
#define SPI_CS_HOLD_DELAY_RES_S 16
#define SPI_RD_STATUS(i) (REG_SPI_BASE(i) + 0x10)
#define SPI_CTRL2(i) (REG_SPI_BASE(i) + 0x14)
#define SPI_CS_DELAY_NUM 0x0000000F
#define SPI_CS_DELAY_NUM_S 28
#define SPI_CS_DELAY_MODE 0x00000003
#define SPI_CS_DELAY_MODE_S 26
#define SPI_MOSI_DELAY_NUM 0x00000007
#define SPI_MOSI_DELAY_NUM_S 23
#define SPI_MOSI_DELAY_MODE 0x00000003
#define SPI_MOSI_DELAY_MODE_S 21
#define SPI_MISO_DELAY_NUM 0x00000007
#define SPI_MISO_DELAY_NUM_S 18
#define SPI_MISO_DELAY_MODE 0x00000003
#define SPI_MISO_DELAY_MODE_S 16
#define SPI_CLOCK(i) (REG_SPI_BASE(i) + 0x18)
#define SPI_CLK_EQU_SYSCLK (BIT(31))
#define SPI_CLKDIV_PRE 0x00001FFF
#define SPI_CLKDIV_PRE_S 18
#define SPI_CLKCNT_N 0x0000003F
#define SPI_CLKCNT_N_S 12
#define SPI_CLKCNT_H 0x0000003F
#define SPI_CLKCNT_H_S 6
#define SPI_CLKCNT_L 0x0000003F
#define SPI_CLKCNT_L_S 0
#define SPI_USER(i) (REG_SPI_BASE(i) + 0x1C)
#define SPI_USR_COMMAND (BIT(31))
#define SPI_USR_ADDR (BIT(30))
#define SPI_USR_DUMMY (BIT(29))
#define SPI_USR_MISO (BIT(28))
#define SPI_USR_MOSI (BIT(27))
#define SPI_USR_MOSI_HIGHPART (BIT(25))
#define SPI_USR_MISO_HIGHPART (BIT(24))
#define SPI_SIO (BIT(16))
#define SPI_FWRITE_QIO (BIT(15))
#define SPI_FWRITE_DIO (BIT(14))
#define SPI_FWRITE_QUAD (BIT(13))
#define SPI_FWRITE_DUAL (BIT(12))
#define SPI_WR_BYTE_ORDER (BIT(11))
#define SPI_RD_BYTE_ORDER (BIT(10))
#define SPI_CK_OUT_EDGE (BIT(7))
#define SPI_CK_I_EDGE (BIT(6))
#define SPI_CS_SETUP (BIT(5))
#define SPI_CS_HOLD (BIT(4))
#define SPI_FLASH_MODE (BIT(2))
#define SPI_USER1(i) (REG_SPI_BASE(i) + 0x20)
#define SPI_USR_ADDR_BITLEN 0x0000003F
#define SPI_USR_ADDR_BITLEN_S 26
#define SPI_USR_MOSI_BITLEN 0x000001FF
#define SPI_USR_MOSI_BITLEN_S 17
#define SPI_USR_MISO_BITLEN 0x000001FF
#define SPI_USR_MISO_BITLEN_S 8
#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
#define SPI_USR_DUMMY_CYCLELEN_S 0
#define SPI_USER2(i) (REG_SPI_BASE(i) + 0x24)
#define SPI_USR_COMMAND_BITLEN 0x0000000F
#define SPI_USR_COMMAND_BITLEN_S 28
#define SPI_USR_COMMAND_VALUE 0x0000FFFF
#define SPI_USR_COMMAND_VALUE_S 0
#define SPI_WR_STATUS(i) (REG_SPI_BASE(i) + 0x28)
#define SPI_PIN(i) (REG_SPI_BASE(i) + 0x2C)
#define SPI_IDLE_EDGE (BIT(29))
#define SPI_CS2_DIS (BIT(2))
#define SPI_CS1_DIS (BIT(1))
#define SPI_CS0_DIS (BIT(0))
#define SPI_SLAVE(i) (REG_SPI_BASE(i) + 0x30)
#define SPI_SYNC_RESET (BIT(31))
#define SPI_SLAVE_MODE (BIT(30))
#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
#define SPI_SLV_WR_RD_STA_EN (BIT(28))
#define SPI_SLV_CMD_DEFINE (BIT(27))
#define SPI_TRANS_CNT 0x0000000F
#define SPI_TRANS_CNT_S 23
#define SPI_TRANS_DONE_EN (BIT(9))
#define SPI_SLV_WR_STA_DONE_EN (BIT(8))
#define SPI_SLV_RD_STA_DONE_EN (BIT(7))
#define SPI_SLV_WR_BUF_DONE_EN (BIT(6))
#define SPI_SLV_RD_BUF_DONE_EN (BIT(5))
#define SLV_SPI_INT_EN 0x0000001f
#define SLV_SPI_INT_EN_S 5
#define SPI_TRANS_DONE (BIT(4))
#define SPI_SLV_WR_STA_DONE (BIT(3))
#define SPI_SLV_RD_STA_DONE (BIT(2))
#define SPI_SLV_WR_BUF_DONE (BIT(1))
#define SPI_SLV_RD_BUF_DONE (BIT(0))
#define SPI_SLAVE1(i) (REG_SPI_BASE(i) + 0x34)
#define SPI_SLV_STATUS_BITLEN 0x0000001F
#define SPI_SLV_STATUS_BITLEN_S 27
#define SPI_SLV_BUF_BITLEN 0x000001FF
#define SPI_SLV_BUF_BITLEN_S 16
#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
#define SPI_SLV_RD_ADDR_BITLEN_S 10
#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
#define SPI_SLV_WR_ADDR_BITLEN_S 4
#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
#define SPI_SLAVE2(i) (REG_SPI_BASE(i) + 0x38)
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0X000000FF
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0X000000FF
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
#define SPI_SLV_WRSTR_DUMMY_CYCLELEN 0X000000FF
#define SPI_SLV_WRSTR_DUMMY_CYCLELEN_S 8
#define SPI_SLV_RDSTR_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_RDSTR_DUMMY_CYCLELEN_S 0
#define SPI_SLAVE3(i) (REG_SPI_BASE(i) + 0x3C)
#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
#define SPI_SLV_WRSTA_CMD_VALUE_S 24
#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
#define SPI_SLV_RDSTA_CMD_VALUE_S 16
#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
#define SPI_SLV_WRBUF_CMD_VALUE_S 8
#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
#define SPI_SLV_RDBUF_CMD_VALUE_S 0
#define SPI_W0(i) (REG_SPI_BASE(i) +0x40)
#define SPI_W1(i) (REG_SPI_BASE(i) +0x44)
#define SPI_W2(i) (REG_SPI_BASE(i) +0x48)
#define SPI_W3(i) (REG_SPI_BASE(i) +0x4C)
#define SPI_W4(i) (REG_SPI_BASE(i) +0x50)
#define SPI_W5(i) (REG_SPI_BASE(i) +0x54)
#define SPI_W6(i) (REG_SPI_BASE(i) +0x58)
#define SPI_W7(i) (REG_SPI_BASE(i) +0x5C)
#define SPI_W8(i) (REG_SPI_BASE(i) +0x60)
#define SPI_W9(i) (REG_SPI_BASE(i) +0x64)
#define SPI_W10(i) (REG_SPI_BASE(i) +0x68)
#define SPI_W11(i) (REG_SPI_BASE(i) +0x6C)
#define SPI_W12(i) (REG_SPI_BASE(i) +0x70)
#define SPI_W13(i) (REG_SPI_BASE(i) +0x74)
#define SPI_W14(i) (REG_SPI_BASE(i) +0x78)
#define SPI_W15(i) (REG_SPI_BASE(i) +0x7C)
#define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
#define SPI_INT_HOLD_ENA 0x00000003
#define SPI_INT_HOLD_ENA_S 0
#endif // SPI_REGISTER_H_INCLUDED

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/*
* ESPRSSIF MIT License
*
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __UART_H__
#define __UART_H__
#ifdef __cplusplus
extern "C" {
#endif
#define ETS_UART_INTR_ENABLE() _xt_isr_unmask(1 << ETS_UART_INUM)
#define ETS_UART_INTR_DISABLE() _xt_isr_mask(1 << ETS_UART_INUM)
#define UART_INTR_MASK 0x1ff
#define UART_LINE_INV_MASK (0x3f<<19)
typedef enum {
UART_WordLength_5b = 0x0,
UART_WordLength_6b = 0x1,
UART_WordLength_7b = 0x2,
UART_WordLength_8b = 0x3
} UART_WordLength;
typedef enum {
USART_StopBits_1 = 0x1,
USART_StopBits_1_5 = 0x2,
USART_StopBits_2 = 0x3,
} UART_StopBits;
typedef enum {
UART0 = 0x0,
UART1 = 0x1,
} UART_Port;
typedef enum {
USART_Parity_None = 0x2,
USART_Parity_Even = 0x0,
USART_Parity_Odd = 0x1
} UART_ParityMode;
typedef enum {
PARITY_DIS = 0x0,
PARITY_EN = 0x2
} UartExistParity;
typedef enum {
BIT_RATE_300 = 300,
BIT_RATE_600 = 600,
BIT_RATE_1200 = 1200,
BIT_RATE_2400 = 2400,
BIT_RATE_4800 = 4800,
BIT_RATE_9600 = 9600,
BIT_RATE_19200 = 19200,
BIT_RATE_38400 = 38400,
BIT_RATE_57600 = 57600,
BIT_RATE_74880 = 74880,
BIT_RATE_115200 = 115200,
BIT_RATE_230400 = 230400,
BIT_RATE_460800 = 460800,
BIT_RATE_921600 = 921600,
BIT_RATE_1843200 = 1843200,
BIT_RATE_3686400 = 3686400,
} UART_BautRate; //you can add any rate you need in this range
typedef enum {
USART_HardwareFlowControl_None = 0x0,
USART_HardwareFlowControl_RTS = 0x1,
USART_HardwareFlowControl_CTS = 0x2,
USART_HardwareFlowControl_CTS_RTS = 0x3
} UART_HwFlowCtrl;
typedef enum {
UART_None_Inverse = 0x0,
UART_Rxd_Inverse = UART_RXD_INV,
UART_CTS_Inverse = UART_CTS_INV,
UART_Txd_Inverse = UART_TXD_INV,
UART_RTS_Inverse = UART_RTS_INV,
} UART_LineLevelInverse;
typedef struct {
UART_BautRate baud_rate;
UART_WordLength data_bits;
UART_ParityMode parity; // chip size in byte
UART_StopBits stop_bits;
UART_HwFlowCtrl flow_ctrl;
uint8 UART_RxFlowThresh ;
uint32 UART_InverseMask;
} UART_ConfigTypeDef;
typedef struct {
uint32 UART_IntrEnMask;
uint8 UART_RX_TimeOutIntrThresh;
uint8 UART_TX_FifoEmptyIntrThresh;
uint8 UART_RX_FifoFullIntrThresh;
} UART_IntrConfTypeDef;
//=======================================
/** \defgroup Driver_APIs Driver APIs
* @brief Driver APIs
*/
/** @addtogroup Driver_APIs
* @{
*/
/** \defgroup UART_Driver_APIs UART Driver APIs
* @brief UART driver APIs
*/
/** @addtogroup UART_Driver_APIs
* @{
*/
/**
* @brief Wait uart tx fifo empty, do not use it if tx flow control enabled.
*
* @param UART_Port uart_no:UART0 or UART1
*
* @return null
*/
void UART_WaitTxFifoEmpty(UART_Port uart_no); //do not use if tx flow control enabled
/**
* @brief Clear uart tx fifo and rx fifo.
*
* @param UART_Port uart_no : UART0 or UART1
*
* @return null
*/
void UART_ResetFifo(UART_Port uart_no);
/**
* @brief Clear uart interrupt flags.
*
* @param UART_Port uart_no : UART0 or UART1
* @param uint32 clr_mask : To clear the interrupt bits
*
* @return null
*/
void UART_ClearIntrStatus(UART_Port uart_no, uint32 clr_mask);
/**
* @brief Enable uart interrupts .
*
* @param UART_Port uart_no : UART0 or UART1
* @param uint32 ena_mask : To enable the interrupt bits
*
* @return null
*/
void UART_SetIntrEna(UART_Port uart_no, uint32 ena_mask);
/**
* @brief Register an application-specific interrupt handler for Uarts interrupts.
*
* @param void *fn : interrupt handler for Uart interrupts.
* @param void *arg : interrupt handler's arg.
*
* @return null
*/
void UART_intr_handler_register(void *fn, void *arg);
/**
* @brief Config from which serial output printf function.
*
* @param UART_Port uart_no : UART0 or UART1
*
* @return null
*/
void UART_SetPrintPort(UART_Port uart_no);
/**
* @brief Config Common parameters of serial ports.
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_ConfigTypeDef *pUARTConfig : parameters structure
*
* @return null
*/
void UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef *pUARTConfig);
/**
* @brief Config types of uarts.
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_IntrConfTypeDef *pUARTIntrConf : parameters structure
*
* @return null
*/
void UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef *pUARTIntrConf);
/**
* @brief Config the length of the uart communication data bits.
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_WordLength len : the length of the uart communication data bits
*
* @return null
*/
void UART_SetWordLength(UART_Port uart_no, UART_WordLength len);
/**
* @brief Config the length of the uart communication stop bits.
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_StopBits bit_num : the length uart communication stop bits
*
* @return null
*/
void UART_SetStopBits(UART_Port uart_no, UART_StopBits bit_num);
/**
* @brief Configure whether to open the parity.
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_ParityMode Parity_mode : the enum of uart parity configuration
*
* @return null
*/
void UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode) ;
/**
* @brief Configure the Baud rate.
*
* @param UART_Port uart_no : UART0 or UART1
* @param uint32 baud_rate : the Baud rate
*
* @return null
*/
void UART_SetBaudrate(UART_Port uart_no, uint32 baud_rate);
/**
* @brief Configure Hardware flow control.
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_HwFlowCtrl flow_ctrl : Hardware flow control mode
* @param uint8 rx_thresh : threshold of Hardware flow control
*
* @return null
*/
void UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8 rx_thresh);
/**
* @brief Configure trigging signal of uarts.
*
* @param UART_Port uart_no : UART0 or UART1
* @param UART_LineLevelInverse inverse_mask : Choose need to flip the IO
*
* @return null
*/
void UART_SetLineInverse(UART_Port uart_no, UART_LineLevelInverse inverse_mask) ;
/**
* @brief An example illustrates how to configure the serial port.
*
* @param null
*
* @return null
*/
void uart_init_new(void);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif