mirror of
https://github.com/espressif/ESP8266_RTOS_SDK.git
synced 2025-07-15 08:32:42 +08:00
feat(esp2866): Move driver to esp8266 of components
This commit is contained in:
Dong Heng
43
components/esp8266/driver/Makefile
Normal file
43
components/esp8266/driver/Makefile
Normal file
@ -0,0 +1,43 @@
|
||||
|
||||
#############################################################
|
||||
# Required variables for each makefile
|
||||
# Discard this section from all parent makefiles
|
||||
# Expected variables (with automatic defaults):
|
||||
# CSRCS (all "C" files in the dir)
|
||||
# SUBDIRS (all subdirs with a Makefile)
|
||||
# GEN_LIBS - list of libs to be generated ()
|
||||
# GEN_IMAGES - list of images to be generated ()
|
||||
# COMPONENTS_xxx - a list of libs/objs in the form
|
||||
# subdir/lib to be extracted and rolled up into
|
||||
# a generated lib/image xxx.a ()
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||||
#
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||||
ifndef PDIR
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||||
GEN_LIBS = libdriver.a
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||||
endif
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||||
|
||||
|
||||
#############################################################
|
||||
# Configuration i.e. compile options etc.
|
||||
# Target specific stuff (defines etc.) goes in here!
|
||||
# Generally values applying to a tree are captured in the
|
||||
# makefile at its root level - these are then overridden
|
||||
# for a subtree within the makefile rooted therein
|
||||
#
|
||||
#DEFINES +=
|
||||
|
||||
#############################################################
|
||||
# Recursion Magic - Don't touch this!!
|
||||
#
|
||||
# Each subtree potentially has an include directory
|
||||
# corresponding to the common APIs applicable to modules
|
||||
# rooted at that subtree. Accordingly, the INCLUDE PATH
|
||||
# of a module can only contain the include directories up
|
||||
# its parent path, and not its siblings
|
||||
#
|
||||
# Required for each makefile to inherit from the parent
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||||
#
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||||
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INCLUDES := $(INCLUDES) -I $(PDIR)include
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PDIR := ../$(PDIR)
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sinclude $(PDIR)Makefile
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213
components/esp8266/driver/gpio.c
Normal file
213
components/esp8266/driver/gpio.c
Normal file
@ -0,0 +1,213 @@
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/*
|
||||
* ESPRSSIF MIT License
|
||||
*
|
||||
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
|
||||
*
|
||||
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
|
||||
* it is free of charge, to any person obtaining a copy of this software and associated
|
||||
* documentation files (the "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
|
||||
* to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all copies or
|
||||
* substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
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#include "espressif/esp_common.h"
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#include "freertos/portmacro.h"
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#include "gpio.h"
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void gpio_config(GPIO_ConfigTypeDef *pGPIOConfig)
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{
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uint16 gpio_pin_mask = pGPIOConfig->GPIO_Pin;
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uint32 io_reg;
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uint8 io_num = 0;
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uint32 pin_reg;
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if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Input) {
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GPIO_AS_INPUT(gpio_pin_mask);
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} else if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Output) {
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GPIO_AS_OUTPUT(gpio_pin_mask);
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}
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do {
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if ((gpio_pin_mask >> io_num) & 0x1) {
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io_reg = GPIO_PIN_REG(io_num);
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if ((0x1 << io_num) & (GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_4 | GPIO_Pin_5)) {
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PIN_FUNC_SELECT(io_reg, 0);
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} else {
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PIN_FUNC_SELECT(io_reg, 3);
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}
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if (pGPIOConfig->GPIO_Pullup) {
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PIN_PULLUP_EN(io_reg);
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} else {
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PIN_PULLUP_DIS(io_reg);
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}
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if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Out_OD) {
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portENTER_CRITICAL();
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(io_num));
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pin_reg &= (~GPIO_PIN_DRIVER_MASK);
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pin_reg |= (GPIO_PAD_DRIVER_ENABLE << GPIO_PIN_DRIVER_LSB);
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GPIO_REG_WRITE(GPIO_PIN_ADDR(io_num), pin_reg);
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portEXIT_CRITICAL();
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} else if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Sigma_Delta) {
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portENTER_CRITICAL();
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(io_num));
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pin_reg &= (~GPIO_PIN_SOURCE_MASK);
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pin_reg |= (0x1 << GPIO_PIN_SOURCE_LSB);
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GPIO_REG_WRITE(GPIO_PIN_ADDR(io_num), pin_reg);
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GPIO_REG_WRITE(GPIO_SIGMA_DELTA_ADDRESS, SIGMA_DELTA_ENABLE);
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portEXIT_CRITICAL();
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}
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gpio_pin_intr_state_set(io_num, pGPIOConfig->GPIO_IntrType);
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}
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io_num++;
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} while (io_num < 16);
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}
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/*
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* Change GPIO pin output by setting, clearing, or disabling pins.
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* In general, it is expected that a bit will be set in at most one
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* of these masks. If a bit is clear in all masks, the output state
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* remains unchanged.
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*
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||||
* There is no particular ordering guaranteed; so if the order of
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* writes is significant, calling code should divide a single call
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* into multiple calls.
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*/
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void gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, uint32 disable_mask)
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{
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GPIO_REG_WRITE(GPIO_OUT_W1TS_ADDRESS, set_mask);
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GPIO_REG_WRITE(GPIO_OUT_W1TC_ADDRESS, clear_mask);
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GPIO_REG_WRITE(GPIO_ENABLE_W1TS_ADDRESS, enable_mask);
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GPIO_REG_WRITE(GPIO_ENABLE_W1TC_ADDRESS, disable_mask);
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}
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/*
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* Sample the value of GPIO input pins and returns a bitmask.
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*/
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uint32 gpio_input_get(void)
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{
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return GPIO_REG_READ(GPIO_IN_ADDRESS);
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}
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|
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/*
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* Register an application-specific interrupt handler for GPIO pin
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||||
* interrupts. Once the interrupt handler is called, it will not
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* be called again until after a call to gpio_intr_ack. Any GPIO
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||||
* interrupts that occur during the interim are masked.
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||||
*
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||||
* The application-specific handler is called with a mask of
|
||||
* pending GPIO interrupts. After processing pin interrupts, the
|
||||
* application-specific handler may wish to use gpio_intr_pending
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||||
* to check for any additional pending interrupts before it returns.
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||||
*/
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void gpio_intr_handler_register(void *fn, void *arg)
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||||
{
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_xt_isr_attach(ETS_GPIO_INUM, fn, arg);
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}
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/*
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only highlevel and lowlevel intr can use for wakeup
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*/
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void gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state)
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||||
{
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uint32 pin_reg;
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if ((intr_state == GPIO_PIN_INTR_LOLEVEL) || (intr_state == GPIO_PIN_INTR_HILEVEL)) {
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portENTER_CRITICAL();
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(i));
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pin_reg &= (~GPIO_PIN_INT_TYPE_MASK);
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pin_reg |= (intr_state << GPIO_PIN_INT_TYPE_LSB);
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pin_reg |= GPIO_PIN_WAKEUP_ENABLE_SET(GPIO_WAKEUP_ENABLE);
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GPIO_REG_WRITE(GPIO_PIN_ADDR(i), pin_reg);
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portEXIT_CRITICAL();
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}
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}
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void gpio_pin_wakeup_disable(void)
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{
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uint8 i;
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uint32 pin_reg;
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for (i = 0; i < GPIO_PIN_COUNT; i++) {
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(i));
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if (pin_reg & GPIO_PIN_WAKEUP_ENABLE_MASK) {
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pin_reg &= (~GPIO_PIN_INT_TYPE_MASK);
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pin_reg |= (GPIO_PIN_INTR_DISABLE << GPIO_PIN_INT_TYPE_LSB);
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pin_reg &= ~(GPIO_PIN_WAKEUP_ENABLE_SET(GPIO_WAKEUP_ENABLE));
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GPIO_REG_WRITE(GPIO_PIN_ADDR(i), pin_reg);
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}
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}
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}
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void gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state)
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{
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uint32 pin_reg;
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portENTER_CRITICAL();
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pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(i));
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pin_reg &= (~GPIO_PIN_INT_TYPE_MASK);
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pin_reg |= (intr_state << GPIO_PIN_INT_TYPE_LSB);
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GPIO_REG_WRITE(GPIO_PIN_ADDR(i), pin_reg);
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portEXIT_CRITICAL();
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}
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void gpio16_output_conf(void)
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{
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WRITE_PERI_REG(PAD_XPD_DCDC_CONF,
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(READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32)0x1); // mux configuration for XPD_DCDC to output rtc_gpio0
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WRITE_PERI_REG(RTC_GPIO_CONF,
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(READ_PERI_REG(RTC_GPIO_CONF) & (uint32)0xfffffffe) | (uint32)0x0); //mux configuration for out enable
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WRITE_PERI_REG(RTC_GPIO_ENABLE,
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(READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe) | (uint32)0x1); //out enable
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}
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void gpio16_output_set(uint8 value)
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{
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WRITE_PERI_REG(RTC_GPIO_OUT,
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(READ_PERI_REG(RTC_GPIO_OUT) & (uint32)0xfffffffe) | (uint32)(value & 1));
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}
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void gpio16_input_conf(void)
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{
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WRITE_PERI_REG(PAD_XPD_DCDC_CONF,
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(READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32)0x1); // mux configuration for XPD_DCDC and rtc_gpio0 connection
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WRITE_PERI_REG(RTC_GPIO_CONF,
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(READ_PERI_REG(RTC_GPIO_CONF) & (uint32)0xfffffffe) | (uint32)0x0); //mux configuration for out enable
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WRITE_PERI_REG(RTC_GPIO_ENABLE,
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READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32)0xfffffffe); //out disable
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}
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uint8 gpio16_input_get(void)
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{
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return (uint8)(READ_PERI_REG(RTC_GPIO_IN_DATA) & 1);
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}
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139
components/esp8266/driver/hw_timer.c
Normal file
139
components/esp8266/driver/hw_timer.c
Normal file
@ -0,0 +1,139 @@
|
||||
/*
|
||||
* ESPRSSIF MIT License
|
||||
*
|
||||
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
|
||||
*
|
||||
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
|
||||
* it is free of charge, to any person obtaining a copy of this software and associated
|
||||
* documentation files (the "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
|
||||
* to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all copies or
|
||||
* substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "esp_common.h"
|
||||
|
||||
#define US_TO_RTC_TIMER_TICKS(t) \
|
||||
((t) ? \
|
||||
(((t) > 0x35A) ? \
|
||||
(((t) >> 2) * ((APB_CLK_FREQ >> 4) / 250000) + ((t)&0x3) * ((APB_CLK_FREQ >> 4) / 1000000)) : \
|
||||
(((t) *(APB_CLK_FREQ>>4)) / 1000000)) : \
|
||||
0)
|
||||
|
||||
#define FRC1_ENABLE_TIMER BIT7
|
||||
#define FRC1_AUTO_LOAD BIT6
|
||||
|
||||
typedef enum { // timer provided mode
|
||||
DIVDED_BY_1 = 0, // timer clock
|
||||
DIVDED_BY_16 = 4, // divided by 16
|
||||
DIVDED_BY_256 = 8, // divided by 256
|
||||
} TIMER_PREDIVED_MODE;
|
||||
|
||||
typedef enum { // timer interrupt mode
|
||||
TM_LEVEL_INT = 1, // level interrupt
|
||||
TM_EDGE_INT = 0, // edge interrupt
|
||||
} TIMER_INT_MODE;
|
||||
|
||||
#define RTC_REG_WRITE(addr, val) WRITE_PERI_REG(addr, val)
|
||||
|
||||
static void (* user_hw_timer_cb)(void) = NULL;
|
||||
|
||||
bool frc1_auto_load = false;
|
||||
|
||||
static void hw_timer_isr_cb(void *arg)
|
||||
{
|
||||
if(frc1_auto_load == false ) {
|
||||
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
|
||||
DIVDED_BY_16 | TM_EDGE_INT);
|
||||
}
|
||||
|
||||
if (user_hw_timer_cb != NULL) {
|
||||
(*(user_hw_timer_cb))();
|
||||
}
|
||||
}
|
||||
|
||||
void hw_timer_disarm(void)
|
||||
{
|
||||
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,0);
|
||||
}
|
||||
|
||||
void hw_timer_arm(uint32 val ,bool req)
|
||||
{
|
||||
frc1_auto_load = req;
|
||||
if (frc1_auto_load == true) {
|
||||
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
|
||||
FRC1_AUTO_LOAD | DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
|
||||
} else {
|
||||
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
|
||||
DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
|
||||
}
|
||||
|
||||
RTC_REG_WRITE(FRC1_LOAD_ADDRESS, US_TO_RTC_TIMER_TICKS(val));
|
||||
}
|
||||
|
||||
void hw_timer_set_func(void (* user_hw_timer_cb_set)(void))
|
||||
{
|
||||
user_hw_timer_cb = user_hw_timer_cb_set;
|
||||
}
|
||||
|
||||
void hw_timer_init(void)
|
||||
{
|
||||
#if 0
|
||||
if (req == 1) {
|
||||
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
|
||||
FRC1_AUTO_LOAD | DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
|
||||
} else {
|
||||
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
|
||||
DIVDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
|
||||
}
|
||||
|
||||
#endif
|
||||
_xt_isr_attach(ETS_FRC_TIMER1_INUM, hw_timer_isr_cb, NULL);
|
||||
|
||||
TM1_EDGE_INT_ENABLE();
|
||||
_xt_isr_unmask(1 << ETS_FRC_TIMER1_INUM);
|
||||
}
|
||||
|
||||
//-------------------------------Test Code Below--------------------------------------
|
||||
#if 0
|
||||
#include "hw_timer.h"
|
||||
|
||||
#define REG_WRITE(_r,_v) (*(volatile uint32 *)(_r)) = (_v)
|
||||
#define REG_READ(_r) (*(volatile uint32 *)(_r))
|
||||
#define WDEV_NOW() REG_READ(0x3ff20c00)
|
||||
|
||||
uint32 tick_now2 = 0;
|
||||
void hw_test_timer_cb(void)
|
||||
{
|
||||
static uint16 j = 0;
|
||||
j++;
|
||||
|
||||
if ((WDEV_NOW() - tick_now2) >= 1000000) {
|
||||
static uint32 idx = 1;
|
||||
tick_now2 = WDEV_NOW();
|
||||
os_printf("b%u:%d\n", idx++, j);
|
||||
j = 0;
|
||||
}
|
||||
|
||||
//hw_timer_arm(50);
|
||||
}
|
||||
|
||||
void user_init(void)
|
||||
{
|
||||
hw_timer_init();
|
||||
hw_timer_set_func(hw_test_timer_cb,1);
|
||||
hw_timer_arm(100);
|
||||
}
|
||||
#endif
|
||||
|
||||
319
components/esp8266/driver/i2c_master.c
Normal file
319
components/esp8266/driver/i2c_master.c
Normal file
@ -0,0 +1,319 @@
|
||||
/******************************************************************************
|
||||
* Copyright 2013-2014 Espressif Systems (Wuxi)
|
||||
*
|
||||
* FileName: i2c_master.c
|
||||
*
|
||||
* Description: i2c master API
|
||||
*
|
||||
* Modification history:
|
||||
* 2014/3/12, v1.0 create this file.
|
||||
*******************************************************************************/
|
||||
#include "c_types.h"
|
||||
#include "esp8266/ets_sys.h"
|
||||
#include "gpio.h"
|
||||
|
||||
#include "i2c_master.h"
|
||||
|
||||
LOCAL uint8 m_nLastSDA;
|
||||
LOCAL uint8 m_nLastSCL;
|
||||
|
||||
/******************************************************************************
|
||||
* FunctionName : i2c_master_setDC
|
||||
* Description : Internal used function -
|
||||
* set i2c SDA and SCL bit value for half clk cycle
|
||||
* Parameters : uint8 SDA
|
||||
* uint8 SCL
|
||||
* Returns : NONE
|
||||
*******************************************************************************/
|
||||
LOCAL void ICACHE_FLASH_ATTR
|
||||
i2c_master_setDC(uint8 SDA, uint8 SCL)
|
||||
{
|
||||
SDA &= 0x01;
|
||||
SCL &= 0x01;
|
||||
m_nLastSDA = SDA;
|
||||
m_nLastSCL = SCL;
|
||||
ETS_INTR_LOCK();
|
||||
if ((0 == SDA) && (0 == SCL)) {
|
||||
I2C_MASTER_SDA_LOW_SCL_LOW();
|
||||
} else if ((0 == SDA) && (1 == SCL)) {
|
||||
I2C_MASTER_SDA_LOW_SCL_HIGH();
|
||||
} else if ((1 == SDA) && (0 == SCL)) {
|
||||
I2C_MASTER_SDA_HIGH_SCL_LOW();
|
||||
} else {
|
||||
I2C_MASTER_SDA_HIGH_SCL_HIGH();
|
||||
}
|
||||
ETS_INTR_UNLOCK();
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* FunctionName : i2c_master_getDC
|
||||
* Description : Internal used function -
|
||||
* get i2c SDA bit value
|
||||
* Parameters : NONE
|
||||
* Returns : uint8 - SDA bit value
|
||||
*******************************************************************************/
|
||||
LOCAL uint8 ICACHE_FLASH_ATTR
|
||||
i2c_master_getDC(void)
|
||||
{
|
||||
uint8 sda_out;
|
||||
ETS_INTR_LOCK();
|
||||
sda_out = GPIO_INPUT_GET(GPIO_ID_PIN(I2C_MASTER_SDA_GPIO));
|
||||
ETS_INTR_UNLOCK();
|
||||
return sda_out;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* FunctionName : i2c_master_init
|
||||
* Description : initilize I2C bus to enable i2c operations
|
||||
* Parameters : NONE
|
||||
* Returns : NONE
|
||||
*******************************************************************************/
|
||||
void ICACHE_FLASH_ATTR
|
||||
i2c_master_init(void)
|
||||
{
|
||||
uint8 i;
|
||||
|
||||
i2c_master_setDC(1, 0);
|
||||
i2c_master_wait(5);
|
||||
|
||||
// when SCL = 0, toggle SDA to clear up
|
||||
i2c_master_setDC(0, 0) ;
|
||||
i2c_master_wait(5);
|
||||
i2c_master_setDC(1, 0) ;
|
||||
i2c_master_wait(5);
|
||||
|
||||
// set data_cnt to max value
|
||||
for (i = 0; i < 28; i++) {
|
||||
i2c_master_setDC(1, 0);
|
||||
i2c_master_wait(5); // sda 1, scl 0
|
||||
i2c_master_setDC(1, 1);
|
||||
i2c_master_wait(5); // sda 1, scl 1
|
||||
}
|
||||
|
||||
// reset all
|
||||
i2c_master_stop();
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* FunctionName : i2c_master_gpio_init
|
||||
* Description : config SDA and SCL gpio to open-drain output mode,
|
||||
* mux and gpio num defined in i2c_master.h
|
||||
* Parameters : NONE
|
||||
* Returns : NONE
|
||||
*******************************************************************************/
|
||||
void ICACHE_FLASH_ATTR
|
||||
i2c_master_gpio_init(void)
|
||||
{
|
||||
ETS_GPIO_INTR_DISABLE() ;
|
||||
// ETS_INTR_LOCK();
|
||||
|
||||
PIN_FUNC_SELECT(I2C_MASTER_SDA_MUX, I2C_MASTER_SDA_FUNC);
|
||||
PIN_FUNC_SELECT(I2C_MASTER_SCL_MUX, I2C_MASTER_SCL_FUNC);
|
||||
|
||||
GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(I2C_MASTER_SDA_GPIO)), GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(I2C_MASTER_SDA_GPIO))) | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); //open drain;
|
||||
GPIO_REG_WRITE(GPIO_ENABLE_ADDRESS, GPIO_REG_READ(GPIO_ENABLE_ADDRESS) | (1 << I2C_MASTER_SDA_GPIO));
|
||||
GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(I2C_MASTER_SCL_GPIO)), GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(I2C_MASTER_SCL_GPIO))) | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); //open drain;
|
||||
GPIO_REG_WRITE(GPIO_ENABLE_ADDRESS, GPIO_REG_READ(GPIO_ENABLE_ADDRESS) | (1 << I2C_MASTER_SCL_GPIO));
|
||||
|
||||
I2C_MASTER_SDA_HIGH_SCL_HIGH();
|
||||
|
||||
ETS_GPIO_INTR_ENABLE() ;
|
||||
// ETS_INTR_UNLOCK();
|
||||
|
||||
i2c_master_init();
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* FunctionName : i2c_master_start
|
||||
* Description : set i2c to send state
|
||||
* Parameters : NONE
|
||||
* Returns : NONE
|
||||
*******************************************************************************/
|
||||
void ICACHE_FLASH_ATTR
|
||||
i2c_master_start(void)
|
||||
{
|
||||
i2c_master_setDC(1, m_nLastSCL);
|
||||
i2c_master_wait(5);
|
||||
i2c_master_setDC(1, 1);
|
||||
i2c_master_wait(5); // sda 1, scl 1
|
||||
i2c_master_setDC(0, 1);
|
||||
i2c_master_wait(5); // sda 0, scl 1
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* FunctionName : i2c_master_stop
|
||||
* Description : set i2c to stop sending state
|
||||
* Parameters : NONE
|
||||
* Returns : NONE
|
||||
*******************************************************************************/
|
||||
void ICACHE_FLASH_ATTR
|
||||
i2c_master_stop(void)
|
||||
{
|
||||
i2c_master_wait(5);
|
||||
|
||||
i2c_master_setDC(0, m_nLastSCL);
|
||||
i2c_master_wait(5); // sda 0
|
||||
i2c_master_setDC(0, 1);
|
||||
i2c_master_wait(5); // sda 0, scl 1
|
||||
i2c_master_setDC(1, 1);
|
||||
i2c_master_wait(5); // sda 1, scl 1
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* FunctionName : i2c_master_setAck
|
||||
* Description : set ack to i2c bus as level value
|
||||
* Parameters : uint8 level - 0 or 1
|
||||
* Returns : NONE
|
||||
*******************************************************************************/
|
||||
void ICACHE_FLASH_ATTR
|
||||
i2c_master_setAck(uint8 level)
|
||||
{
|
||||
i2c_master_setDC(m_nLastSDA, 0);
|
||||
i2c_master_wait(5);
|
||||
i2c_master_setDC(level, 0);
|
||||
i2c_master_wait(5); // sda level, scl 0
|
||||
i2c_master_setDC(level, 1);
|
||||
i2c_master_wait(8); // sda level, scl 1
|
||||
i2c_master_setDC(level, 0);
|
||||
i2c_master_wait(5); // sda level, scl 0
|
||||
i2c_master_setDC(1, 0);
|
||||
i2c_master_wait(5);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* FunctionName : i2c_master_getAck
|
||||
* Description : confirm if peer send ack
|
||||
* Parameters : NONE
|
||||
* Returns : uint8 - ack value, 0 or 1
|
||||
*******************************************************************************/
|
||||
uint8 ICACHE_FLASH_ATTR
|
||||
i2c_master_getAck(void)
|
||||
{
|
||||
uint8 retVal;
|
||||
i2c_master_setDC(m_nLastSDA, 0);
|
||||
i2c_master_wait(5);
|
||||
i2c_master_setDC(1, 0);
|
||||
i2c_master_wait(5);
|
||||
i2c_master_setDC(1, 1);
|
||||
i2c_master_wait(5);
|
||||
|
||||
retVal = i2c_master_getDC();
|
||||
i2c_master_wait(5);
|
||||
i2c_master_setDC(1, 0);
|
||||
i2c_master_wait(5);
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* FunctionName : i2c_master_checkAck
|
||||
* Description : get dev response
|
||||
* Parameters : NONE
|
||||
* Returns : true : get ack ; false : get nack
|
||||
*******************************************************************************/
|
||||
bool ICACHE_FLASH_ATTR
|
||||
i2c_master_checkAck(void)
|
||||
{
|
||||
if(i2c_master_getAck()){
|
||||
return FALSE;
|
||||
}else{
|
||||
return TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* FunctionName : i2c_master_send_ack
|
||||
* Description : response ack
|
||||
* Parameters : NONE
|
||||
* Returns : NONE
|
||||
*******************************************************************************/
|
||||
void ICACHE_FLASH_ATTR
|
||||
i2c_master_send_ack(void)
|
||||
{
|
||||
i2c_master_setAck(0x0);
|
||||
}
|
||||
/******************************************************************************
|
||||
* FunctionName : i2c_master_send_nack
|
||||
* Description : response nack
|
||||
* Parameters : NONE
|
||||
* Returns : NONE
|
||||
*******************************************************************************/
|
||||
void ICACHE_FLASH_ATTR
|
||||
i2c_master_send_nack(void)
|
||||
{
|
||||
i2c_master_setAck(0x1);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* FunctionName : i2c_master_readByte
|
||||
* Description : read Byte from i2c bus
|
||||
* Parameters : NONE
|
||||
* Returns : uint8 - readed value
|
||||
*******************************************************************************/
|
||||
uint8 ICACHE_FLASH_ATTR
|
||||
i2c_master_readByte(void)
|
||||
{
|
||||
uint8 retVal = 0;
|
||||
uint8 k, i;
|
||||
|
||||
i2c_master_wait(5);
|
||||
i2c_master_setDC(m_nLastSDA, 0);
|
||||
i2c_master_wait(5); // sda 1, scl 0
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
i2c_master_wait(5);
|
||||
i2c_master_setDC(1, 0);
|
||||
i2c_master_wait(5); // sda 1, scl 0
|
||||
i2c_master_setDC(1, 1);
|
||||
i2c_master_wait(5); // sda 1, scl 1
|
||||
|
||||
k = i2c_master_getDC();
|
||||
i2c_master_wait(5);
|
||||
|
||||
if (i == 7) {
|
||||
i2c_master_wait(3); ////
|
||||
}
|
||||
|
||||
k <<= (7 - i);
|
||||
retVal |= k;
|
||||
}
|
||||
|
||||
i2c_master_setDC(1, 0);
|
||||
i2c_master_wait(5); // sda 1, scl 0
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* FunctionName : i2c_master_writeByte
|
||||
* Description : write wrdata value(one byte) into i2c
|
||||
* Parameters : uint8 wrdata - write value
|
||||
* Returns : NONE
|
||||
*******************************************************************************/
|
||||
void ICACHE_FLASH_ATTR
|
||||
i2c_master_writeByte(uint8 wrdata)
|
||||
{
|
||||
uint8 dat;
|
||||
sint8 i;
|
||||
|
||||
i2c_master_wait(5);
|
||||
|
||||
i2c_master_setDC(m_nLastSDA, 0);
|
||||
i2c_master_wait(5);
|
||||
|
||||
for (i = 7; i >= 0; i--) {
|
||||
dat = wrdata >> i;
|
||||
i2c_master_setDC(dat, 0);
|
||||
i2c_master_wait(5);
|
||||
i2c_master_setDC(dat, 1);
|
||||
i2c_master_wait(5);
|
||||
|
||||
if (i == 0) {
|
||||
i2c_master_wait(3); ////
|
||||
}
|
||||
|
||||
i2c_master_setDC(dat, 0);
|
||||
i2c_master_wait(5);
|
||||
}
|
||||
}
|
||||
523
components/esp8266/driver/spi_interface.c
Normal file
523
components/esp8266/driver/spi_interface.c
Normal file
@ -0,0 +1,523 @@
|
||||
/**
|
||||
* spi_interface.c
|
||||
*
|
||||
* Defines and Macros for the SPI.
|
||||
*
|
||||
* Copyright @ 2015 Espressif System Co., Ltd.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are NOT permitted except as agreed by
|
||||
* Espressif System Co., Ltd.
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
*/
|
||||
/**
|
||||
* @file spi_interface.c
|
||||
* @brief Defines and Macros for the SPI.
|
||||
*/
|
||||
|
||||
#include "spi_interface.h"
|
||||
#include "esp8266/eagle_soc.h"
|
||||
#include "esp8266/ets_sys.h"
|
||||
#include "esp8266/pin_mux_register.h"
|
||||
#include "esp_libc.h"
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Make sure all of the definitions in this header have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
// Show the spi registers.
|
||||
#define SHOWDEBUG
|
||||
|
||||
void __ShowRegValue(const char * func, uint32_t line)
|
||||
{
|
||||
#ifndef SHOWDEBUG
|
||||
int i;
|
||||
uint32_t regAddr = 0x60000140; // SPI--0x60000240, HSPI--0x60000140;
|
||||
printf("\r\n FUNC[%s],line[%d]\r\n", func, line);
|
||||
printf(" SPI_ADDR [0x%08x]\r\n", READ_PERI_REG(SPI_ADDR(SpiNum_HSPI)));
|
||||
printf(" SPI_CMD [0x%08x]\r\n", READ_PERI_REG(SPI_CMD(SpiNum_HSPI)));
|
||||
printf(" SPI_CTRL [0x%08x]\r\n", READ_PERI_REG(SPI_CTRL(SpiNum_HSPI)));
|
||||
printf(" SPI_CTRL2 [0x%08x]\r\n", READ_PERI_REG(SPI_CTRL2(SpiNum_HSPI)));
|
||||
printf(" SPI_CLOCK [0x%08x]\r\n", READ_PERI_REG(SPI_CLOCK(SpiNum_HSPI)));
|
||||
printf(" SPI_RD_STATUS [0x%08x]\r\n", READ_PERI_REG(SPI_RD_STATUS(SpiNum_HSPI)));
|
||||
printf(" SPI_WR_STATUS [0x%08x]\r\n", READ_PERI_REG(SPI_WR_STATUS(SpiNum_HSPI)));
|
||||
printf(" SPI_USER [0x%08x]\r\n", READ_PERI_REG(SPI_USER(SpiNum_HSPI)));
|
||||
printf(" SPI_USER1 [0x%08x]\r\n", READ_PERI_REG(SPI_USER1(SpiNum_HSPI)));
|
||||
printf(" SPI_USER2 [0x%08x]\r\n", READ_PERI_REG(SPI_USER2(SpiNum_HSPI)));
|
||||
printf(" SPI_PIN [0x%08x]\r\n", READ_PERI_REG(SPI_PIN(SpiNum_HSPI)));
|
||||
printf(" SPI_SLAVE [0x%08x]\r\n", READ_PERI_REG(SPI_SLAVE(SpiNum_HSPI)));
|
||||
printf(" SPI_SLAVE1 [0x%08x]\r\n", READ_PERI_REG(SPI_SLAVE1(SpiNum_HSPI)));
|
||||
printf(" SPI_SLAVE2 [0x%08x]\r\n", READ_PERI_REG(SPI_SLAVE2(SpiNum_HSPI)));
|
||||
|
||||
for (i = 0; i < 16; ++i) {
|
||||
printf(" ADDR[0x%08x],Value[0x%08x]\r\n", regAddr, READ_PERI_REG(regAddr));
|
||||
regAddr += 4;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
// Define SPI interrupt enable macro
|
||||
#define ETS_SPI_INTR_ENABLE() _xt_isr_unmask(1 << ETS_SPI_INUM)
|
||||
|
||||
/**
|
||||
* @brief Based on pAttr initialize SPI module.
|
||||
*
|
||||
*/
|
||||
void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
|
||||
{
|
||||
if ((spiNum > SpiNum_HSPI)
|
||||
|| (NULL == pAttr)) {
|
||||
return;
|
||||
}
|
||||
// SPI_CPOL & SPI_CPHA
|
||||
switch (pAttr->subMode) {
|
||||
case SpiSubMode_1:
|
||||
CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
|
||||
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
|
||||
break;
|
||||
case SpiSubMode_2:
|
||||
SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
|
||||
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
|
||||
break;
|
||||
case SpiSubMode_3:
|
||||
SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE);
|
||||
break;
|
||||
case SpiSubMode_0:
|
||||
default:
|
||||
CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE);
|
||||
// To do nothing
|
||||
break;
|
||||
}
|
||||
|
||||
// SPI bit order
|
||||
if (SpiBitOrder_MSBFirst == pAttr->bitOrder) {
|
||||
CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_WR_BIT_ORDER);
|
||||
CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_RD_BIT_ORDER);
|
||||
} else if (SpiBitOrder_LSBFirst == pAttr->bitOrder) {
|
||||
SET_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_WR_BIT_ORDER);
|
||||
SET_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_RD_BIT_ORDER);
|
||||
} else {
|
||||
// To do nothing
|
||||
}
|
||||
|
||||
// Disable flash operation mode
|
||||
// As earlier as better, if not SPI_CTRL2 can not to be set delay cycles.
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_FLASH_MODE);
|
||||
|
||||
// SPI mode type
|
||||
if (SpiMode_Master == pAttr->mode) {
|
||||
// SPI mode type
|
||||
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE);
|
||||
// SPI Send buffer
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART );// By default slave send buffer C0-C7
|
||||
// SPI Speed
|
||||
if (1 < (pAttr->speed)) {
|
||||
CLEAR_PERI_REG_MASK(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK);
|
||||
if (spiNum == SpiNum_HSPI) {
|
||||
CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI1_CLK_EQU_SYS_CLK);
|
||||
}
|
||||
|
||||
WRITE_PERI_REG(SPI_CLOCK(spiNum),
|
||||
((pAttr->speed & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) |
|
||||
((((pAttr->speed + 1) / 2 - 1) & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) |
|
||||
((pAttr->speed & SPI_CLKCNT_L) << SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div
|
||||
} else {
|
||||
WRITE_PERI_REG(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK); // 80Mhz speed
|
||||
}
|
||||
// By default format:CMD+ADDR+DATA
|
||||
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI );
|
||||
|
||||
//delay num
|
||||
SET_PERI_REG_MASK(SPI_CTRL2(spiNum), ((0x1 & SPI_MISO_DELAY_NUM) << SPI_MISO_DELAY_NUM_S));
|
||||
} else if (SpiMode_Slave == pAttr->mode) {
|
||||
// BIT19 must do
|
||||
SET_PERI_REG_MASK(SPI_PIN(spiNum), BIT19);
|
||||
|
||||
// SPI mode type
|
||||
SET_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE);
|
||||
// SPI Send buffer
|
||||
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART);// By default slave send buffer C8-C15
|
||||
|
||||
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
|
||||
|
||||
// If do not set delay cycles, slave not working,master cann't get the data.
|
||||
SET_PERI_REG_MASK(SPI_CTRL2(spiNum), ((0x1 & SPI_MOSI_DELAY_NUM) << SPI_MOSI_DELAY_NUM_S)); //delay num
|
||||
// SPI Speed
|
||||
WRITE_PERI_REG(SPI_CLOCK(spiNum), 0);
|
||||
|
||||
// By default format::CMD(8bits)+ADDR(8bits)+DATA(32bytes).
|
||||
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
|
||||
7, SPI_USR_COMMAND_BITLEN_S);
|
||||
SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_WR_ADDR_BITLEN,
|
||||
7, SPI_SLV_WR_ADDR_BITLEN_S);
|
||||
SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_RD_ADDR_BITLEN,
|
||||
7, SPI_SLV_RD_ADDR_BITLEN_S);
|
||||
SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_BUF_BITLEN,
|
||||
(32 * 8 - 1), SPI_SLV_BUF_BITLEN_S);
|
||||
// For 8266 work on slave mode.
|
||||
SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_STATUS_BITLEN,
|
||||
7, SPI_SLV_STATUS_BITLEN_S);
|
||||
} else {
|
||||
// To do nothing
|
||||
}
|
||||
|
||||
//clear Daul or Quad lines transmission mode
|
||||
CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_QIO_MODE | SPI_DIO_MODE | SPI_DOUT_MODE | SPI_QOUT_MODE);
|
||||
SET_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_FASTRD_MODE);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set address value by master mode.
|
||||
*
|
||||
*/
|
||||
void ICACHE_FLASH_ATTR SPIMasterCfgAddr(SpiNum spiNum, uint32_t addr)
|
||||
{
|
||||
if (spiNum > SpiNum_HSPI) {
|
||||
return;
|
||||
}
|
||||
// Set address
|
||||
WRITE_PERI_REG(SPI_ADDR(spiNum), addr);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set command value by master mode.
|
||||
*
|
||||
*/
|
||||
void ICACHE_FLASH_ATTR SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd)
|
||||
{
|
||||
if (spiNum > SpiNum_HSPI) {
|
||||
return;
|
||||
}
|
||||
// SPI_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1,
|
||||
// bit15-0 is cmd value.
|
||||
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_VALUE, cmd, SPI_USR_COMMAND_VALUE_S);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Send data to slave.
|
||||
*
|
||||
*/
|
||||
int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
|
||||
{
|
||||
char idx = 0;
|
||||
if ((spiNum > SpiNum_HSPI)
|
||||
|| (NULL == pInData)
|
||||
|| (64 < pInData->dataLen)) {
|
||||
return -1;
|
||||
}
|
||||
uint32_t *value = pInData->data;
|
||||
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
|
||||
// Set command by user.
|
||||
if (pInData->cmdLen != 0) {
|
||||
// Max command length 16 bits.
|
||||
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
|
||||
((pInData->cmdLen << 3) - 1), SPI_USR_COMMAND_BITLEN_S);
|
||||
// Enable command
|
||||
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND);
|
||||
// Load command
|
||||
SPIMasterCfgCmd(spiNum, pInData->cmd);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND);
|
||||
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
|
||||
0, SPI_USR_COMMAND_BITLEN_S);
|
||||
}
|
||||
// Set Address by user.
|
||||
if (pInData->addrLen == 0) {
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
|
||||
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
|
||||
0, SPI_USR_ADDR_BITLEN_S);
|
||||
} else {
|
||||
if (NULL == pInData->addr) {
|
||||
return -1;
|
||||
}
|
||||
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
|
||||
((pInData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S);
|
||||
// Enable address
|
||||
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
|
||||
// Load address
|
||||
SPIMasterCfgAddr(spiNum, *pInData->addr);
|
||||
}
|
||||
// Set data by user.
|
||||
if (pInData->dataLen != 0) {
|
||||
if (NULL == value) {
|
||||
return -1;
|
||||
}
|
||||
// Enable MOSI
|
||||
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
|
||||
// Load send buffer
|
||||
do {
|
||||
WRITE_PERI_REG((SPI_W0(spiNum) + (idx << 2)), *value++);
|
||||
} while (++idx < (pInData->dataLen / 4));
|
||||
// Set data send buffer length.Max data length 64 bytes.
|
||||
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN, ((pInData->dataLen << 3) - 1), SPI_USR_MOSI_BITLEN_S);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
|
||||
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN,
|
||||
0, SPI_USR_MOSI_BITLEN_S);
|
||||
}
|
||||
// Start send data
|
||||
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
|
||||
|
||||
SHOWREG();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Receive data from slave.
|
||||
*
|
||||
*/
|
||||
int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
|
||||
{
|
||||
char idx = 0;
|
||||
if ((spiNum > SpiNum_HSPI)
|
||||
|| (NULL == pOutData)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
uint32_t *value = pOutData->data;
|
||||
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
|
||||
// Set command by user.
|
||||
if (pOutData->cmdLen != 0) {
|
||||
// Max command length 16 bits.
|
||||
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
|
||||
((pOutData->cmdLen << 3) - 1), SPI_USR_COMMAND_BITLEN_S);
|
||||
// Enable command
|
||||
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND);
|
||||
// Load command
|
||||
SPIMasterCfgCmd(spiNum, pOutData->cmd);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND);
|
||||
SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
|
||||
0, SPI_USR_COMMAND_BITLEN_S);
|
||||
}
|
||||
// Set Address by user.
|
||||
if (pOutData->addrLen == 0) {
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
|
||||
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
|
||||
0, SPI_USR_ADDR_BITLEN_S);
|
||||
} else {
|
||||
if (NULL == pOutData->addr) {
|
||||
return -1;
|
||||
}
|
||||
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
|
||||
((pOutData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S);
|
||||
// Enable address
|
||||
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
|
||||
// Load address
|
||||
SPIMasterCfgAddr(spiNum, *pOutData->addr);
|
||||
}
|
||||
// Set data by user.
|
||||
if (pOutData->dataLen != 0) {
|
||||
if (NULL == value) {
|
||||
return -1;
|
||||
}
|
||||
// Clear MOSI enable
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
|
||||
// Enable MOSI
|
||||
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
|
||||
// Set data send buffer length.Max data length 64 bytes.
|
||||
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MISO_BITLEN, ((pOutData->dataLen << 3) - 1), SPI_USR_MISO_BITLEN_S);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
|
||||
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MISO_BITLEN,
|
||||
0, SPI_USR_MISO_BITLEN_S);
|
||||
}
|
||||
|
||||
//CLEAR FIFO DATA
|
||||
int fifo_idx = 0;
|
||||
do {
|
||||
WRITE_PERI_REG(SPI_W0(spiNum) + (fifo_idx << 2), 0);
|
||||
} while (++fifo_idx < (pOutData->dataLen / 4));
|
||||
|
||||
// Start send data
|
||||
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
|
||||
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
|
||||
// Read data out
|
||||
do {
|
||||
*pOutData->data++ = READ_PERI_REG(SPI_W0(spiNum) + (idx << 2));
|
||||
} while (++idx < (pOutData->dataLen / 4));
|
||||
|
||||
SHOWREG();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Load data to send buffer by slave mode.
|
||||
*
|
||||
*/
|
||||
int ICACHE_FLASH_ATTR SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uint8_t outLen)
|
||||
{
|
||||
if (NULL == pInData) {
|
||||
return -1;
|
||||
}
|
||||
char i;
|
||||
for (i = 0; i < outLen; ++i) {
|
||||
WRITE_PERI_REG((SPI_W8(spiNum) + (i << 2)), *pInData++);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configurate slave prepare for receive data.
|
||||
*
|
||||
*/
|
||||
int ICACHE_FLASH_ATTR SPISlaveRecvData(SpiNum spiNum, void(*isrFunc)(void*))
|
||||
{
|
||||
if ((spiNum > SpiNum_HSPI)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
SPIIntEnable(SpiNum_HSPI, SpiIntSrc_WrStaDoneEn
|
||||
| SpiIntSrc_RdStaDoneEn | SpiIntSrc_WrBufDoneEn | SpiIntSrc_RdBufDoneEn);
|
||||
SPIIntDisable(SpiNum_HSPI, SpiIntSrc_TransDoneEn);
|
||||
|
||||
// Maybe enable slave transmission liston
|
||||
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
|
||||
//
|
||||
_xt_isr_attach(ETS_SPI_INUM, isrFunc, NULL);
|
||||
// ETS_SPI_INTR_ATTACH(isrFunc, NULL);
|
||||
// Enable isr
|
||||
ETS_SPI_INTR_ENABLE();
|
||||
|
||||
|
||||
SHOWREG();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Send data to slave(ESP8266 register of RD_STATUS or WR_STATUS).
|
||||
*
|
||||
*/
|
||||
void ICACHE_FLASH_ATTR SPIMasterSendStatus(SpiNum spiNum, uint8_t data)
|
||||
{
|
||||
if (spiNum > SpiNum_HSPI) {
|
||||
return;
|
||||
}
|
||||
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
|
||||
// Enable MOSI
|
||||
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
|
||||
|
||||
// 8bits cmd, 0x04 is eps8266 slave write cmd value
|
||||
WRITE_PERI_REG(SPI_USER2(spiNum),
|
||||
((7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S)
|
||||
| MASTER_WRITE_STATUS_TO_SLAVE_CMD);
|
||||
// Set data send buffer length.
|
||||
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN,
|
||||
((sizeof(data) << 3) - 1), SPI_USR_MOSI_BITLEN_S);
|
||||
|
||||
WRITE_PERI_REG(SPI_W0(spiNum), (uint32)(data));
|
||||
// Start SPI
|
||||
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
|
||||
|
||||
SHOWREG();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Receive status register from slave(ESP8266).
|
||||
*
|
||||
*/
|
||||
int ICACHE_FLASH_ATTR SPIMasterRecvStatus(SpiNum spiNum)
|
||||
{
|
||||
if (spiNum > SpiNum_HSPI) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
|
||||
// Enable MISO
|
||||
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI | SPI_USR_DUMMY | SPI_USR_ADDR);
|
||||
|
||||
// 8bits cmd, 0x06 is eps8266 slave read status cmd value
|
||||
WRITE_PERI_REG(SPI_USER2(spiNum),
|
||||
((7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S)
|
||||
| MASTER_READ_STATUS_FROM_SLAVE_CMD);
|
||||
// Set revcive buffer length.
|
||||
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MISO_BITLEN,
|
||||
7, SPI_USR_MISO_BITLEN_S);
|
||||
|
||||
// start spi module.
|
||||
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
|
||||
|
||||
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
|
||||
|
||||
uint8_t data = (uint8)(READ_PERI_REG(SPI_W0(spiNum)) & 0xff);
|
||||
SHOWREG();
|
||||
|
||||
return (uint8)(READ_PERI_REG(SPI_W0(spiNum)) & 0xff);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select SPI CS pin.
|
||||
*
|
||||
*/
|
||||
void ICACHE_FLASH_ATTR SPICsPinSelect(SpiNum spiNum, SpiPinCS pinCs)
|
||||
{
|
||||
if (spiNum > SpiNum_HSPI) {
|
||||
return;
|
||||
}
|
||||
// clear select
|
||||
SET_PERI_REG_BITS(SPI_PIN(spiNum), 3, 0, 0);
|
||||
SET_PERI_REG_MASK(SPI_PIN(spiNum), pinCs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable SPI interrupt source.
|
||||
*
|
||||
*/
|
||||
void ICACHE_FLASH_ATTR SPIIntEnable(SpiNum spiNum, SpiIntSrc intSrc)
|
||||
{
|
||||
if (spiNum > SpiNum_HSPI) {
|
||||
return;
|
||||
}
|
||||
SET_PERI_REG_MASK(SPI_SLAVE(spiNum), intSrc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SPI interrupt source.
|
||||
*
|
||||
*/
|
||||
void ICACHE_FLASH_ATTR SPIIntDisable(SpiNum spiNum, SpiIntSrc intSrc)
|
||||
{
|
||||
if (spiNum > SpiNum_HSPI) {
|
||||
return;
|
||||
}
|
||||
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), intSrc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear all of SPI interrupt source.
|
||||
*
|
||||
*/
|
||||
void ICACHE_FLASH_ATTR SPIIntClear(SpiNum spiNum)
|
||||
{
|
||||
if (spiNum > SpiNum_HSPI) {
|
||||
return;
|
||||
}
|
||||
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SpiIntSrc_TransDoneEn
|
||||
| SpiIntSrc_WrStaDoneEn
|
||||
| SpiIntSrc_RdStaDoneEn
|
||||
| SpiIntSrc_WrBufDoneEn
|
||||
| SpiIntSrc_RdBufDoneEn);
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
435
components/esp8266/driver/uart.c
Normal file
435
components/esp8266/driver/uart.c
Normal file
@ -0,0 +1,435 @@
|
||||
/*
|
||||
* ESPRSSIF MIT License
|
||||
*
|
||||
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
|
||||
*
|
||||
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
|
||||
* it is free of charge, to any person obtaining a copy of this software and associated
|
||||
* documentation files (the "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
|
||||
* to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all copies or
|
||||
* substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "esp_common.h"
|
||||
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "freertos/queue.h"
|
||||
|
||||
#include "uart.h"
|
||||
|
||||
enum {
|
||||
UART_EVENT_RX_CHAR,
|
||||
UART_EVENT_MAX
|
||||
};
|
||||
|
||||
typedef struct _os_event_ {
|
||||
uint32 event;
|
||||
uint32 param;
|
||||
} os_event_t;
|
||||
|
||||
xTaskHandle xUartTaskHandle;
|
||||
xQueueHandle xQueueUart;
|
||||
|
||||
LOCAL STATUS
|
||||
uart_tx_one_char(uint8 uart, uint8 TxChar)
|
||||
{
|
||||
while (true) {
|
||||
uint32 fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S);
|
||||
|
||||
if ((fifo_cnt >> UART_TXFIFO_CNT_S & UART_TXFIFO_CNT) < 126) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_PERI_REG(UART_FIFO(uart) , TxChar);
|
||||
return OK;
|
||||
}
|
||||
|
||||
LOCAL void
|
||||
uart1_write_char(char c)
|
||||
{
|
||||
if (c == '\n') {
|
||||
uart_tx_one_char(UART1, '\r');
|
||||
uart_tx_one_char(UART1, '\n');
|
||||
} else if (c == '\r') {
|
||||
} else {
|
||||
uart_tx_one_char(UART1, c);
|
||||
}
|
||||
}
|
||||
|
||||
LOCAL void
|
||||
uart0_write_char(char c)
|
||||
{
|
||||
if (c == '\n') {
|
||||
uart_tx_one_char(UART0, '\r');
|
||||
uart_tx_one_char(UART0, '\n');
|
||||
} else if (c == '\r') {
|
||||
} else {
|
||||
uart_tx_one_char(UART0, c);
|
||||
}
|
||||
}
|
||||
|
||||
LOCAL void
|
||||
uart_rx_intr_handler_ssc(void *arg)
|
||||
{
|
||||
/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
|
||||
* uart1 and uart0 respectively
|
||||
*/
|
||||
os_event_t e;
|
||||
portBASE_TYPE xHigherPriorityTaskWoken;
|
||||
|
||||
uint8 RcvChar;
|
||||
uint8 uart_no = 0;
|
||||
|
||||
if (UART_RXFIFO_FULL_INT_ST != (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_FULL_INT_ST)) {
|
||||
return;
|
||||
}
|
||||
|
||||
RcvChar = READ_PERI_REG(UART_FIFO(uart_no)) & 0xFF;
|
||||
|
||||
WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_RXFIFO_FULL_INT_CLR);
|
||||
|
||||
e.event = UART_EVENT_RX_CHAR;
|
||||
e.param = RcvChar;
|
||||
|
||||
xQueueSendFromISR(xQueueUart, (void *)&e, &xHigherPriorityTaskWoken);
|
||||
portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
|
||||
}
|
||||
|
||||
#if 0
|
||||
LOCAL void
|
||||
uart_config(uint8 uart_no, UartDevice *uart)
|
||||
{
|
||||
if (uart_no == UART1) {
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
|
||||
} else {
|
||||
/* rcv_buff size if 0x100 */
|
||||
_xt_isr_attach(ETS_UART_INUM, uart_rx_intr_handler_ssc, NULL);
|
||||
PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
|
||||
}
|
||||
|
||||
uart_div_modify(uart_no, UART_CLK_FREQ / (uart->baut_rate));
|
||||
|
||||
WRITE_PERI_REG(UART_CONF0(uart_no), uart->exist_parity
|
||||
| uart->parity
|
||||
| (uart->stop_bits << UART_STOP_BIT_NUM_S)
|
||||
| (uart->data_bits << UART_BIT_NUM_S));
|
||||
|
||||
//clear rx and tx fifo,not ready
|
||||
SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
|
||||
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
|
||||
|
||||
if (uart_no == UART0) {
|
||||
//set rx fifo trigger
|
||||
WRITE_PERI_REG(UART_CONF1(uart_no),
|
||||
((0x01 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S));
|
||||
} else {
|
||||
WRITE_PERI_REG(UART_CONF1(uart_no),
|
||||
((0x01 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S));
|
||||
}
|
||||
|
||||
//clear all interrupt
|
||||
WRITE_PERI_REG(UART_INT_CLR(uart_no), 0xffff);
|
||||
//enable rx_interrupt
|
||||
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA);
|
||||
}
|
||||
#endif
|
||||
|
||||
LOCAL void
|
||||
uart_task(void *pvParameters)
|
||||
{
|
||||
os_event_t e;
|
||||
|
||||
for (;;) {
|
||||
if (xQueueReceive(xQueueUart, (void *)&e, (portTickType)portMAX_DELAY)) {
|
||||
switch (e.event) {
|
||||
case UART_EVENT_RX_CHAR:
|
||||
printf("%c", e.param);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
#if 0
|
||||
void
|
||||
uart_init(void)
|
||||
{
|
||||
while (READ_PERI_REG(UART_STATUS(0)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S));
|
||||
|
||||
while (READ_PERI_REG(UART_STATUS(1)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S));
|
||||
|
||||
UART_ConfigTypeDef uart;
|
||||
|
||||
uart.baut_rate = BIT_RATE_74880;
|
||||
uart.data_bits = UART_WordLength_8b;
|
||||
uart.flow_ctrl = USART_HardwareFlowControl_None;
|
||||
// uart.exist_parity = PARITY_DIS;
|
||||
uart.parity = USART_Parity_None;
|
||||
uart.stop_bits = USART_StopBits_1;
|
||||
|
||||
uart_config(UART0, &uart);
|
||||
uart_config(UART1, &uart);
|
||||
|
||||
os_install_putc1(uart1_write_char);
|
||||
|
||||
_xt_isr_unmask(1 << ETS_UART_INUM);
|
||||
|
||||
xQueueUart = xQueueCreate(32, sizeof(os_event_t));
|
||||
|
||||
xTaskCreate(uart_task, (uint8 const *)"uTask", 512, NULL, tskIDLE_PRIORITY + 2, &xUartTaskHandle);
|
||||
}
|
||||
#endif
|
||||
|
||||
//=================================================================
|
||||
|
||||
void
|
||||
UART_SetWordLength(UART_Port uart_no, UART_WordLength len)
|
||||
{
|
||||
SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_BIT_NUM, len, UART_BIT_NUM_S);
|
||||
}
|
||||
|
||||
void
|
||||
UART_SetStopBits(UART_Port uart_no, UART_StopBits bit_num)
|
||||
{
|
||||
SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_STOP_BIT_NUM, bit_num, UART_STOP_BIT_NUM_S);
|
||||
}
|
||||
|
||||
void
|
||||
UART_SetLineInverse(UART_Port uart_no, UART_LineLevelInverse inverse_mask)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_LINE_INV_MASK);
|
||||
SET_PERI_REG_MASK(UART_CONF0(uart_no), inverse_mask);
|
||||
}
|
||||
|
||||
void
|
||||
UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_PARITY | UART_PARITY_EN);
|
||||
|
||||
if (Parity_mode == USART_Parity_None) {
|
||||
} else {
|
||||
SET_PERI_REG_MASK(UART_CONF0(uart_no), Parity_mode | UART_PARITY_EN);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
UART_SetBaudrate(UART_Port uart_no, uint32 baud_rate)
|
||||
{
|
||||
uart_div_modify(uart_no, UART_CLK_FREQ / baud_rate);
|
||||
}
|
||||
|
||||
//only when USART_HardwareFlowControl_RTS is set , will the rx_thresh value be set.
|
||||
void
|
||||
UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8 rx_thresh)
|
||||
{
|
||||
if (flow_ctrl & USART_HardwareFlowControl_RTS) {
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
|
||||
SET_PERI_REG_BITS(UART_CONF1(uart_no), UART_RX_FLOW_THRHD, rx_thresh, UART_RX_FLOW_THRHD_S);
|
||||
SET_PERI_REG_MASK(UART_CONF1(uart_no), UART_RX_FLOW_EN);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(UART_CONF1(uart_no), UART_RX_FLOW_EN);
|
||||
}
|
||||
|
||||
if (flow_ctrl & USART_HardwareFlowControl_CTS) {
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_UART0_CTS);
|
||||
SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
UART_WaitTxFifoEmpty(UART_Port uart_no) //do not use if tx flow control enabled
|
||||
{
|
||||
while (READ_PERI_REG(UART_STATUS(uart_no)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S));
|
||||
}
|
||||
|
||||
void
|
||||
UART_ResetFifo(UART_Port uart_no)
|
||||
{
|
||||
SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
|
||||
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
|
||||
}
|
||||
|
||||
void
|
||||
UART_ClearIntrStatus(UART_Port uart_no, uint32 clr_mask)
|
||||
{
|
||||
WRITE_PERI_REG(UART_INT_CLR(uart_no), clr_mask);
|
||||
}
|
||||
|
||||
void
|
||||
UART_SetIntrEna(UART_Port uart_no, uint32 ena_mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), ena_mask);
|
||||
}
|
||||
|
||||
void
|
||||
UART_intr_handler_register(void *fn, void *arg)
|
||||
{
|
||||
_xt_isr_attach(ETS_UART_INUM, fn, arg);
|
||||
}
|
||||
|
||||
void
|
||||
UART_SetPrintPort(UART_Port uart_no)
|
||||
{
|
||||
if (uart_no == 1) {
|
||||
os_install_putc1(uart1_write_char);
|
||||
} else {
|
||||
os_install_putc1(uart0_write_char);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef *pUARTConfig)
|
||||
{
|
||||
if (uart_no == UART1) {
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
|
||||
} else {
|
||||
PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
|
||||
}
|
||||
|
||||
UART_SetFlowCtrl(uart_no, pUARTConfig->flow_ctrl, pUARTConfig->UART_RxFlowThresh);
|
||||
UART_SetBaudrate(uart_no, pUARTConfig->baud_rate);
|
||||
|
||||
WRITE_PERI_REG(UART_CONF0(uart_no),
|
||||
((pUARTConfig->parity == USART_Parity_None) ? 0x0 : (UART_PARITY_EN | pUARTConfig->parity))
|
||||
| (pUARTConfig->stop_bits << UART_STOP_BIT_NUM_S)
|
||||
| (pUARTConfig->data_bits << UART_BIT_NUM_S)
|
||||
| ((pUARTConfig->flow_ctrl & USART_HardwareFlowControl_CTS) ? UART_TX_FLOW_EN : 0x0)
|
||||
| pUARTConfig->UART_InverseMask);
|
||||
|
||||
UART_ResetFifo(uart_no);
|
||||
}
|
||||
|
||||
void
|
||||
UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef *pUARTIntrConf)
|
||||
{
|
||||
|
||||
uint32 reg_val = 0;
|
||||
UART_ClearIntrStatus(uart_no, UART_INTR_MASK);
|
||||
reg_val = READ_PERI_REG(UART_CONF1(uart_no)) & ((UART_RX_FLOW_THRHD << UART_RX_FLOW_THRHD_S) | UART_RX_FLOW_EN) ;
|
||||
|
||||
reg_val |= ((pUARTIntrConf->UART_IntrEnMask & UART_RXFIFO_TOUT_INT_ENA) ?
|
||||
((((pUARTIntrConf->UART_RX_TimeOutIntrThresh)&UART_RX_TOUT_THRHD) << UART_RX_TOUT_THRHD_S) | UART_RX_TOUT_EN) : 0);
|
||||
|
||||
reg_val |= ((pUARTIntrConf->UART_IntrEnMask & UART_RXFIFO_FULL_INT_ENA) ?
|
||||
(((pUARTIntrConf->UART_RX_FifoFullIntrThresh)&UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) : 0);
|
||||
|
||||
reg_val |= ((pUARTIntrConf->UART_IntrEnMask & UART_TXFIFO_EMPTY_INT_ENA) ?
|
||||
(((pUARTIntrConf->UART_TX_FifoEmptyIntrThresh)&UART_TXFIFO_EMPTY_THRHD) << UART_TXFIFO_EMPTY_THRHD_S) : 0);
|
||||
|
||||
WRITE_PERI_REG(UART_CONF1(uart_no), reg_val);
|
||||
CLEAR_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_INTR_MASK);
|
||||
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), pUARTIntrConf->UART_IntrEnMask);
|
||||
}
|
||||
|
||||
LOCAL void
|
||||
uart0_rx_intr_handler(void *para)
|
||||
{
|
||||
/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
|
||||
* uart1 and uart0 respectively
|
||||
*/
|
||||
uint8 RcvChar;
|
||||
uint8 uart_no = UART0;//UartDev.buff_uart_no;
|
||||
uint8 fifo_len = 0;
|
||||
uint8 buf_idx = 0;
|
||||
uint8 fifo_tmp[128] = {0};
|
||||
|
||||
uint32 uart_intr_status = READ_PERI_REG(UART_INT_ST(uart_no)) ;
|
||||
|
||||
while (uart_intr_status != 0x0) {
|
||||
if (UART_FRM_ERR_INT_ST == (uart_intr_status & UART_FRM_ERR_INT_ST)) {
|
||||
//printf("FRM_ERR\r\n");
|
||||
WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_FRM_ERR_INT_CLR);
|
||||
} else if (UART_RXFIFO_FULL_INT_ST == (uart_intr_status & UART_RXFIFO_FULL_INT_ST)) {
|
||||
printf("full\r\n");
|
||||
fifo_len = (READ_PERI_REG(UART_STATUS(UART0)) >> UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT;
|
||||
buf_idx = 0;
|
||||
|
||||
while (buf_idx < fifo_len) {
|
||||
uart_tx_one_char(UART0, READ_PERI_REG(UART_FIFO(UART0)) & 0xFF);
|
||||
buf_idx++;
|
||||
}
|
||||
|
||||
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR);
|
||||
} else if (UART_RXFIFO_TOUT_INT_ST == (uart_intr_status & UART_RXFIFO_TOUT_INT_ST)) {
|
||||
printf("tout\r\n");
|
||||
fifo_len = (READ_PERI_REG(UART_STATUS(UART0)) >> UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT;
|
||||
buf_idx = 0;
|
||||
|
||||
while (buf_idx < fifo_len) {
|
||||
uart_tx_one_char(UART0, READ_PERI_REG(UART_FIFO(UART0)) & 0xFF);
|
||||
buf_idx++;
|
||||
}
|
||||
|
||||
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_TOUT_INT_CLR);
|
||||
} else if (UART_TXFIFO_EMPTY_INT_ST == (uart_intr_status & UART_TXFIFO_EMPTY_INT_ST)) {
|
||||
printf("empty\n\r");
|
||||
WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_TXFIFO_EMPTY_INT_CLR);
|
||||
CLEAR_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA);
|
||||
} else {
|
||||
//skip
|
||||
}
|
||||
|
||||
uart_intr_status = READ_PERI_REG(UART_INT_ST(uart_no)) ;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
uart_init_new(void)
|
||||
{
|
||||
UART_WaitTxFifoEmpty(UART0);
|
||||
UART_WaitTxFifoEmpty(UART1);
|
||||
|
||||
UART_ConfigTypeDef uart_config;
|
||||
uart_config.baud_rate = BIT_RATE_74880;
|
||||
uart_config.data_bits = UART_WordLength_8b;
|
||||
uart_config.parity = USART_Parity_None;
|
||||
uart_config.stop_bits = USART_StopBits_1;
|
||||
uart_config.flow_ctrl = USART_HardwareFlowControl_None;
|
||||
uart_config.UART_RxFlowThresh = 120;
|
||||
uart_config.UART_InverseMask = UART_None_Inverse;
|
||||
UART_ParamConfig(UART0, &uart_config);
|
||||
|
||||
UART_IntrConfTypeDef uart_intr;
|
||||
uart_intr.UART_IntrEnMask = UART_RXFIFO_TOUT_INT_ENA | UART_FRM_ERR_INT_ENA | UART_RXFIFO_FULL_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA;
|
||||
uart_intr.UART_RX_FifoFullIntrThresh = 10;
|
||||
uart_intr.UART_RX_TimeOutIntrThresh = 2;
|
||||
uart_intr.UART_TX_FifoEmptyIntrThresh = 20;
|
||||
UART_IntrConfig(UART0, &uart_intr);
|
||||
|
||||
UART_SetPrintPort(UART0);
|
||||
UART_intr_handler_register(uart0_rx_intr_handler, NULL);
|
||||
ETS_UART_INTR_ENABLE();
|
||||
|
||||
/*
|
||||
UART_SetWordLength(UART0,UART_WordLength_8b);
|
||||
UART_SetStopBits(UART0,USART_StopBits_1);
|
||||
UART_SetParity(UART0,USART_Parity_None);
|
||||
UART_SetBaudrate(UART0,74880);
|
||||
UART_SetFlowCtrl(UART0,USART_HardwareFlowControl_None,0);
|
||||
*/
|
||||
|
||||
}
|
||||
307
components/esp8266/include/driver/gpio.h
Normal file
307
components/esp8266/include/driver/gpio.h
Normal file
@ -0,0 +1,307 @@
|
||||
/*
|
||||
* ESPRSSIF MIT License
|
||||
*
|
||||
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
|
||||
*
|
||||
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
|
||||
* it is free of charge, to any person obtaining a copy of this software and associated
|
||||
* documentation files (the "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
|
||||
* to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all copies or
|
||||
* substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __GPIO_H__
|
||||
#define __GPIO_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "esp8266/gpio_register.h"
|
||||
#define GPIO_Pin_0 (BIT(0)) /* Pin 0 selected */
|
||||
#define GPIO_Pin_1 (BIT(1)) /* Pin 1 selected */
|
||||
#define GPIO_Pin_2 (BIT(2)) /* Pin 2 selected */
|
||||
#define GPIO_Pin_3 (BIT(3)) /* Pin 3 selected */
|
||||
#define GPIO_Pin_4 (BIT(4)) /* Pin 4 selected */
|
||||
#define GPIO_Pin_5 (BIT(5)) /* Pin 5 selected */
|
||||
#define GPIO_Pin_6 (BIT(6)) /* Pin 6 selected */
|
||||
#define GPIO_Pin_7 (BIT(7)) /* Pin 7 selected */
|
||||
#define GPIO_Pin_8 (BIT(8)) /* Pin 8 selected */
|
||||
#define GPIO_Pin_9 (BIT(9)) /* Pin 9 selected */
|
||||
#define GPIO_Pin_10 (BIT(10)) /* Pin 10 selected */
|
||||
#define GPIO_Pin_11 (BIT(11)) /* Pin 11 selected */
|
||||
#define GPIO_Pin_12 (BIT(12)) /* Pin 12 selected */
|
||||
#define GPIO_Pin_13 (BIT(13)) /* Pin 13 selected */
|
||||
#define GPIO_Pin_14 (BIT(14)) /* Pin 14 selected */
|
||||
#define GPIO_Pin_15 (BIT(15)) /* Pin 15 selected */
|
||||
#define GPIO_Pin_All (0xFFFF) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_REG_0 PERIPHS_IO_MUX_GPIO0_U
|
||||
#define GPIO_PIN_REG_1 PERIPHS_IO_MUX_U0TXD_U
|
||||
#define GPIO_PIN_REG_2 PERIPHS_IO_MUX_GPIO2_U
|
||||
#define GPIO_PIN_REG_3 PERIPHS_IO_MUX_U0RXD_U
|
||||
#define GPIO_PIN_REG_4 PERIPHS_IO_MUX_GPIO4_U
|
||||
#define GPIO_PIN_REG_5 PERIPHS_IO_MUX_GPIO5_U
|
||||
#define GPIO_PIN_REG_6 PERIPHS_IO_MUX_SD_CLK_U
|
||||
#define GPIO_PIN_REG_7 PERIPHS_IO_MUX_SD_DATA0_U
|
||||
#define GPIO_PIN_REG_8 PERIPHS_IO_MUX_SD_DATA1_U
|
||||
#define GPIO_PIN_REG_9 PERIPHS_IO_MUX_SD_DATA2_U
|
||||
#define GPIO_PIN_REG_10 PERIPHS_IO_MUX_SD_DATA3_U
|
||||
#define GPIO_PIN_REG_11 PERIPHS_IO_MUX_SD_CMD_U
|
||||
#define GPIO_PIN_REG_12 PERIPHS_IO_MUX_MTDI_U
|
||||
#define GPIO_PIN_REG_13 PERIPHS_IO_MUX_MTCK_U
|
||||
#define GPIO_PIN_REG_14 PERIPHS_IO_MUX_MTMS_U
|
||||
#define GPIO_PIN_REG_15 PERIPHS_IO_MUX_MTDO_U
|
||||
|
||||
#define GPIO_PIN_REG(i) \
|
||||
(i==0) ? GPIO_PIN_REG_0: \
|
||||
(i==1) ? GPIO_PIN_REG_1: \
|
||||
(i==2) ? GPIO_PIN_REG_2: \
|
||||
(i==3) ? GPIO_PIN_REG_3: \
|
||||
(i==4) ? GPIO_PIN_REG_4: \
|
||||
(i==5) ? GPIO_PIN_REG_5: \
|
||||
(i==6) ? GPIO_PIN_REG_6: \
|
||||
(i==7) ? GPIO_PIN_REG_7: \
|
||||
(i==8) ? GPIO_PIN_REG_8: \
|
||||
(i==9) ? GPIO_PIN_REG_9: \
|
||||
(i==10)? GPIO_PIN_REG_10: \
|
||||
(i==11)? GPIO_PIN_REG_11: \
|
||||
(i==12)? GPIO_PIN_REG_12: \
|
||||
(i==13)? GPIO_PIN_REG_13: \
|
||||
(i==14)? GPIO_PIN_REG_14: \
|
||||
GPIO_PIN_REG_15
|
||||
|
||||
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_ADDRESS + i*4)
|
||||
|
||||
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
|
||||
((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
|
||||
|
||||
#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
|
||||
|
||||
typedef enum {
|
||||
GPIO_PIN_INTR_DISABLE = 0, /**< disable GPIO interrupt */
|
||||
GPIO_PIN_INTR_POSEDGE = 1, /**< GPIO interrupt type : rising edge */
|
||||
GPIO_PIN_INTR_NEGEDGE = 2, /**< GPIO interrupt type : falling edge */
|
||||
GPIO_PIN_INTR_ANYEDGE = 3, /**< GPIO interrupt type : bothe rising and falling edge */
|
||||
GPIO_PIN_INTR_LOLEVEL = 4, /**< GPIO interrupt type : low level */
|
||||
GPIO_PIN_INTR_HILEVEL = 5 /**< GPIO interrupt type : high level */
|
||||
} GPIO_INT_TYPE;
|
||||
|
||||
typedef enum {
|
||||
GPIO_Mode_Input = 0x0, /**< GPIO mode : Input */
|
||||
GPIO_Mode_Out_OD, /**< GPIO mode : Output_OD */
|
||||
GPIO_Mode_Output , /**< GPIO mode : Output */
|
||||
GPIO_Mode_Sigma_Delta , /**< GPIO mode : Sigma_Delta */
|
||||
} GPIOMode_TypeDef;
|
||||
|
||||
typedef enum {
|
||||
GPIO_PullUp_DIS = 0x0, /**< disable GPIO pullup */
|
||||
GPIO_PullUp_EN = 0x1, /**< enable GPIO pullup */
|
||||
} GPIO_Pullup_IF;
|
||||
|
||||
typedef struct {
|
||||
uint16 GPIO_Pin; /**< GPIO pin */
|
||||
GPIOMode_TypeDef GPIO_Mode; /**< GPIO mode */
|
||||
GPIO_Pullup_IF GPIO_Pullup; /**< GPIO pullup */
|
||||
GPIO_INT_TYPE GPIO_IntrType; /**< GPIO interrupt type */
|
||||
} GPIO_ConfigTypeDef;
|
||||
|
||||
/** \defgroup Driver_APIs Driver APIs
|
||||
* @brief Driver APIs
|
||||
*/
|
||||
|
||||
/** @addtogroup Driver_APIs
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** \defgroup GPIO_Driver_APIs GPIO Driver APIs
|
||||
* @brief GPIO APIs
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Driver_APIs
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set GPIO pin output level.
|
||||
*
|
||||
* @param gpio_no : The GPIO sequence number.
|
||||
* @param bit_value : GPIO pin output level.
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
|
||||
gpio_output_conf(bit_value<<gpio_no, ((~bit_value)&0x01)<<gpio_no, 1<<gpio_no, 0)
|
||||
|
||||
/**
|
||||
* @brief Set GPIO pin output level.
|
||||
*
|
||||
* @param gpio_bits : The GPIO bit number.
|
||||
* @param bit_value : GPIO pin output level.
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
#define GPIO_OUTPUT(gpio_bits, bit_value) \
|
||||
if(bit_value) gpio_output_conf(gpio_bits, 0, gpio_bits, 0);\
|
||||
else gpio_output_conf(0, gpio_bits, gpio_bits, 0)
|
||||
|
||||
/**
|
||||
* @brief Disable GPIO pin output.
|
||||
*
|
||||
* @param gpio_no : The GPIO sequence number.
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
#define GPIO_DIS_OUTPUT(gpio_no) gpio_output_conf(0, 0, 0, 1<<gpio_no)
|
||||
|
||||
/**
|
||||
* @brief Enable GPIO pin intput.
|
||||
*
|
||||
* @param gpio_bits : The GPIO bit number.
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
#define GPIO_AS_INPUT(gpio_bits) gpio_output_conf(0, 0, 0, gpio_bits)
|
||||
|
||||
/**
|
||||
* @brief Enable GPIO pin output.
|
||||
*
|
||||
* @param gpio_bits : The GPIO bit number.
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
#define GPIO_AS_OUTPUT(gpio_bits) gpio_output_conf(0, 0, gpio_bits, 0)
|
||||
|
||||
/**
|
||||
* @brief Sample the level of GPIO input.
|
||||
*
|
||||
* @param gpio_no : The GPIO sequence number.
|
||||
*
|
||||
* @return the level of GPIO input
|
||||
*/
|
||||
#define GPIO_INPUT_GET(gpio_no) ((gpio_input_get()>>gpio_no)&BIT(0))
|
||||
|
||||
/**
|
||||
* @brief Enable GPIO16 output.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void gpio16_output_conf(void);
|
||||
|
||||
/**
|
||||
* @brief Set GPIO16 output level.
|
||||
*
|
||||
* @param uint8 value : GPIO16 output level.
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void gpio16_output_set(uint8 value);
|
||||
|
||||
/**
|
||||
* @brief Enable GPIO pin intput.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void gpio16_input_conf(void);
|
||||
|
||||
/**
|
||||
* @brief Sample the value of GPIO16 input.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return the level of GPIO16 input.
|
||||
*/
|
||||
uint8 gpio16_input_get(void);
|
||||
|
||||
/**
|
||||
* @brief Configure Gpio pins out or input.
|
||||
*
|
||||
* @param uint32 set_mask : Set the output for the high bit, the
|
||||
* corresponding bit is 1, the output of high,
|
||||
* the corresponding bit is 0, do not change the state.
|
||||
* @param uint32 set_mask : Set the output for the high bit, the
|
||||
* corresponding bit is 1, the output of low,
|
||||
* the corresponding bit is 0, do not change the state.
|
||||
* @param uint32 enable_mask : Enable Output
|
||||
* @param uint32 disable_mask : Enable Input
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void gpio_output_conf(uint32 set_mask, uint32 clear_mask, uint32 enable_mask, uint32 disable_mask);
|
||||
|
||||
/**
|
||||
* @brief Register an application-specific interrupt handler for GPIO pin interrupts.
|
||||
*
|
||||
* @param void *fn:interrupt handler for GPIO pin interrupts.
|
||||
* @param void *arg:interrupt handler's arg
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void gpio_intr_handler_register(void *fn, void *arg);
|
||||
|
||||
/**
|
||||
* @brief Configure GPIO wake up to light sleep,Only level way is effective.
|
||||
*
|
||||
* @param uint32 i : Gpio sequence number
|
||||
* @param GPIO_INT_TYPE intr_state : the level of wake up to light sleep
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state);
|
||||
|
||||
/**
|
||||
* @brief Disable GPIO wake up to light sleep.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void gpio_pin_wakeup_disable();
|
||||
|
||||
/**
|
||||
* @brief Config interrupt types of GPIO pin.
|
||||
*
|
||||
* @param uint32 i : The GPIO sequence number.
|
||||
* @param GPIO_INT_TYPE intr_state : GPIO interrupt types.
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state);
|
||||
|
||||
/**
|
||||
* @brief Sample the value of GPIO input pins and returns a bitmask.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return bitmask of GPIO pins input
|
||||
*/
|
||||
uint32 gpio_input_get(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
96
components/esp8266/include/driver/hw_timer.h
Normal file
96
components/esp8266/include/driver/hw_timer.h
Normal file
@ -0,0 +1,96 @@
|
||||
/*
|
||||
* ESPRSSIF MIT License
|
||||
*
|
||||
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
|
||||
*
|
||||
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
|
||||
* it is free of charge, to any person obtaining a copy of this software and associated
|
||||
* documentation files (the "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
|
||||
* to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all copies or
|
||||
* substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __HW_TIMER_H__
|
||||
#define __HW_TIMER_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup HW_Timer_APIs Hardware timer APIs
|
||||
* @brief Hardware timer APIs
|
||||
*
|
||||
* @attention Hardware timer can not interrupt other ISRs.
|
||||
*
|
||||
*/
|
||||
|
||||
/** @addtogroup HW_Timer_APIs
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialize the hardware ISR timer.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void hw_timer_init(void);
|
||||
|
||||
/**
|
||||
* @brief Set a trigger timer delay to enable this timer.
|
||||
*
|
||||
* @param uint32 val : Timing
|
||||
* - In autoload mode, range : 50 ~ 0x7fffff
|
||||
* - In non-autoload mode, range : 10 ~ 0x7fffff
|
||||
*
|
||||
* @param uint8 req : 0, not autoload; 1, autoload mode.
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void hw_timer_arm(uint32 val, bool req);
|
||||
|
||||
/**
|
||||
* @brief disable this timer.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void hw_timer_disarm(void);
|
||||
|
||||
/**
|
||||
* @brief Set timer callback function.
|
||||
*
|
||||
* For enabled timer, timer callback has to be set.
|
||||
*
|
||||
* @param uint32 val : Timing
|
||||
* - In autoload mode, range : 50 ~ 0x7fffff
|
||||
* - In non-autoload mode, range : 10 ~ 0x7fffff
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void hw_timer_set_func(void (* user_hw_timer_cb_set)(void));
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
169
components/esp8266/include/driver/i2c_master.h
Normal file
169
components/esp8266/include/driver/i2c_master.h
Normal file
@ -0,0 +1,169 @@
|
||||
#ifndef __I2C_MASTER_H__
|
||||
#define __I2C_MASTER_H__
|
||||
|
||||
#include "esp8266/pin_mux_register.h"
|
||||
#define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_GPIO2_U
|
||||
#define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_GPIO4_U
|
||||
#define I2C_MASTER_SDA_GPIO 2
|
||||
#define I2C_MASTER_SCL_GPIO 4
|
||||
#define I2C_MASTER_SDA_FUNC FUNC_GPIO2
|
||||
#define I2C_MASTER_SCL_FUNC FUNC_GPIO4
|
||||
|
||||
//#define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_GPIO2_U
|
||||
//#define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_GPIO0_U
|
||||
//#define I2C_MASTER_SDA_GPIO 2
|
||||
//#define I2C_MASTER_SCL_GPIO 0
|
||||
//#define I2C_MASTER_SDA_FUNC FUNC_GPIO2
|
||||
//#define I2C_MASTER_SCL_FUNC FUNC_GPIO0
|
||||
|
||||
#if 0
|
||||
#define I2C_MASTER_GPIO_SET(pin) \
|
||||
gpio_output_set(1<<pin,0,1<<pin,0)
|
||||
|
||||
#define I2C_MASTER_GPIO_CLR(pin) \
|
||||
gpio_output_set(0,1<<pin,1<<pin,0)
|
||||
|
||||
#define I2C_MASTER_GPIO_OUT(pin,val) \
|
||||
if(val) I2C_MASTER_GPIO_SET(pin);\
|
||||
else I2C_MASTER_GPIO_CLR(pin)
|
||||
#endif
|
||||
|
||||
#define I2C_MASTER_SDA_HIGH_SCL_HIGH() \
|
||||
gpio_output_set(1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0)
|
||||
|
||||
#define I2C_MASTER_SDA_HIGH_SCL_LOW() \
|
||||
gpio_output_set(1<<I2C_MASTER_SDA_GPIO, 1<<I2C_MASTER_SCL_GPIO, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0)
|
||||
|
||||
#define I2C_MASTER_SDA_LOW_SCL_HIGH() \
|
||||
gpio_output_set(1<<I2C_MASTER_SCL_GPIO, 1<<I2C_MASTER_SDA_GPIO, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0)
|
||||
|
||||
#define I2C_MASTER_SDA_LOW_SCL_LOW() \
|
||||
gpio_output_set(0, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0)
|
||||
|
||||
/** \defgroup Driver_APIs Driver APIs
|
||||
* @brief Driver APIs
|
||||
*/
|
||||
|
||||
/** @addtogroup Driver_APIs
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** \defgroup I2C_Driver_APIs I2C_MASTER Driver APIs
|
||||
* @brief UART driver APIs
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_MASTER_Driver_APIs
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void i2c_master_gpio_init(void);
|
||||
|
||||
/**
|
||||
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
|
||||
*
|
||||
* @param initilize I2C bus to enable i2c operations.
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void i2c_master_init(void);
|
||||
|
||||
#define i2c_master_wait os_delay_us
|
||||
|
||||
|
||||
/**
|
||||
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
|
||||
*
|
||||
* @param set i2c to stop sending state.
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void i2c_master_stop(void);
|
||||
|
||||
/**
|
||||
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
|
||||
*
|
||||
* @param set i2c to start sending state.
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void i2c_master_start(void);
|
||||
|
||||
/**
|
||||
* @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.
|
||||
*
|
||||
* @param set ack to i2c bus as level value.
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void i2c_master_setAck(uint8 level);
|
||||
|
||||
/**
|
||||
* @brief confirm if peer send ack.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
uint8 i2c_master_getAck(void);
|
||||
|
||||
/**
|
||||
* @brief read Byte from i2c bus.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return the byte which read from i2c bus.
|
||||
*/
|
||||
uint8 i2c_master_readByte(void);
|
||||
|
||||
/**
|
||||
* @brief write wrdata value(one byte) into i2c.
|
||||
*
|
||||
* @param uint8 wrdata:write value
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void i2c_master_writeByte(uint8 wrdata);
|
||||
|
||||
/**
|
||||
* @brief i2c_master_checkAck.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return the result of check ack
|
||||
*/
|
||||
bool i2c_master_checkAck(void);
|
||||
|
||||
/**
|
||||
* @brief i2c master send Ack.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void i2c_master_send_ack(void);
|
||||
|
||||
/**
|
||||
* @brief i2c master send Nack.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void i2c_master_send_nack(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
328
components/esp8266/include/driver/spi_interface.h
Normal file
328
components/esp8266/include/driver/spi_interface.h
Normal file
@ -0,0 +1,328 @@
|
||||
/**
|
||||
* spi_interface.h
|
||||
*
|
||||
* Defines and Macros for the SPI.
|
||||
*
|
||||
* Copyright @ 2015 Espressif System Co., Ltd.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are NOT permitted except as agreed by
|
||||
* Espressif System Co., Ltd.
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
*/
|
||||
/**
|
||||
* @file spi_interface.h
|
||||
* @brief Defines and Macros for the SPI.
|
||||
*/
|
||||
#ifndef __SPI_INTERFACE_H__
|
||||
#define __SPI_INTERFACE_H__
|
||||
|
||||
#include "spi_register.h"
|
||||
#include "c_types.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Make sure all of the definitions in this header have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Defines slave commands. Default value based on slave ESP8266.
|
||||
*/
|
||||
#define MASTER_WRITE_DATA_TO_SLAVE_CMD 2
|
||||
#define MASTER_READ_DATA_FROM_SLAVE_CMD 3
|
||||
|
||||
#define MASTER_WRITE_STATUS_TO_SLAVE_CMD 1
|
||||
#define MASTER_READ_STATUS_FROM_SLAVE_CMD 4
|
||||
|
||||
/**
|
||||
* @brief Support HSPI and SPI module.
|
||||
*
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SpiNum_SPI = 0,
|
||||
SpiNum_HSPI = 1,
|
||||
} SpiNum;
|
||||
|
||||
/**
|
||||
* @brief The SPI module can work in either master or slave mode.
|
||||
*
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SpiMode_Master = 0,
|
||||
SpiMode_Slave = 1,
|
||||
} SpiMode;
|
||||
|
||||
/**
|
||||
* @brief SPI sub mode
|
||||
*
|
||||
* Support 4 sub modes based on SPI clock polarity and phase.
|
||||
* SPI_CPOL SPI_CPHA SubMode
|
||||
* 0 0 0
|
||||
* 0 1 1
|
||||
* 1 0 2
|
||||
* 1 1 3
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SpiSubMode_0 = 0,
|
||||
SpiSubMode_1 = 1,
|
||||
SpiSubMode_2 = 2,
|
||||
SpiSubMode_3 = 3,
|
||||
} SpiSubMode;
|
||||
|
||||
/**
|
||||
* @brief The SPI module working speed.
|
||||
*
|
||||
* @attention Max speed 80MHz
|
||||
*
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SpiSpeed_2MHz = 40 - 1,
|
||||
SpiSpeed_5MHz = 16 - 1,
|
||||
SpiSpeed_10MHz = 8 - 1,
|
||||
SpiSpeed_16MHz = 5 - 1,
|
||||
SpiSpeed_20MHz = 4 - 1,
|
||||
} SpiSpeed;
|
||||
|
||||
/**
|
||||
* @brief The SPI mode working speed.
|
||||
*
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SpiBitOrder_MSBFirst = 0,
|
||||
SpiBitOrder_LSBFirst = 1,
|
||||
} SpiBitOrder;
|
||||
|
||||
// @brief SPI interrupt soource defined.
|
||||
typedef enum
|
||||
{
|
||||
SpiIntSrc_TransDoneEn = SPI_TRANS_DONE_EN,
|
||||
SpiIntSrc_WrStaDoneEn = SPI_SLV_WR_STA_DONE_EN,
|
||||
SpiIntSrc_RdStaDoneEn = SPI_SLV_RD_STA_DONE_EN,
|
||||
SpiIntSrc_WrBufDoneEn = SPI_SLV_WR_BUF_DONE_EN,
|
||||
SpiIntSrc_RdBufDoneEn = SPI_SLV_RD_BUF_DONE_EN,
|
||||
} SpiIntSrc;
|
||||
|
||||
// @brief SPI CS pin.
|
||||
typedef enum
|
||||
{
|
||||
SpiPinCS_0 = 0,
|
||||
SpiPinCS_1 = 1,
|
||||
SpiPinCS_2 = 2,
|
||||
} SpiPinCS;
|
||||
|
||||
#pragma pack (1)
|
||||
|
||||
/**
|
||||
* @brief SPI attribute
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
SpiMode mode; ///< Master or slave mode
|
||||
SpiSubMode subMode; ///< SPI SPI_CPOL SPI_CPHA mode
|
||||
SpiSpeed speed; ///< SPI Clock
|
||||
SpiBitOrder bitOrder; ///< SPI bit order
|
||||
} SpiAttr;
|
||||
|
||||
/**
|
||||
* @brief SPI attribute
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t cmd; ///< Command value
|
||||
uint8_t cmdLen; ///< Command byte length
|
||||
uint32_t *addr; ///< Point to address value
|
||||
uint8_t addrLen; ///< Address byte length
|
||||
uint32_t *data; ///< Point to data buffer
|
||||
uint8_t dataLen; ///< Data byte length.
|
||||
} SpiData;
|
||||
|
||||
#pragma upack (1)
|
||||
|
||||
#define SHOWREG() __ShowRegValue(__func__, __LINE__);
|
||||
|
||||
/**
|
||||
* @brief Print debug information.
|
||||
*
|
||||
*/
|
||||
void __ShowRegValue(const char * func, uint32_t line);
|
||||
|
||||
/**
|
||||
* @brief Initialize SPI module.
|
||||
*
|
||||
* @param [in] spiNum
|
||||
* Indicates which submode to be used, SPI or HSPI.
|
||||
* @param [in] pAttr
|
||||
* Pointer to a struct SpiAttr that indicates SPI working attribution.
|
||||
*
|
||||
* @return void.
|
||||
*/
|
||||
void SPIInit(SpiNum spiNum, SpiAttr* pAttr);
|
||||
|
||||
/**
|
||||
* @brief Set slave address value by master.
|
||||
*
|
||||
* @param [in] spiNum
|
||||
* Indicates which submode to be used, SPI or HSPI.
|
||||
* @param [in] addr
|
||||
* Slave address to be set.
|
||||
*
|
||||
* @return void.
|
||||
*/
|
||||
void SPIMasterCfgAddr(SpiNum spiNum, uint32_t addr);
|
||||
|
||||
/**
|
||||
* @brief Set command value by master.
|
||||
*
|
||||
* @param [in] spiNum
|
||||
* Indicates which submode to be used, SPI or HSPI.
|
||||
* @param [in] cmd
|
||||
* Command will be send to slave.
|
||||
*
|
||||
* @return void.
|
||||
*/
|
||||
void SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd);
|
||||
|
||||
/**
|
||||
* @brief Send data to slave from master.
|
||||
*
|
||||
* @param [in] spiNum
|
||||
* Indicates which submode to be used, SPI or HSPI.
|
||||
* @param [in] pInData
|
||||
* Pointer to a strcuture that will be send.
|
||||
*
|
||||
* @return int, -1:indicates failure,others indicates success.
|
||||
*/
|
||||
int SPIMasterSendData(SpiNum spiNum, SpiData* pInData);
|
||||
|
||||
/**
|
||||
* @brief Receive data from slave by master.
|
||||
*
|
||||
* @param [in] spiNum
|
||||
* Indicates which submode to be used, SPI or HSPI.
|
||||
* @param [in] pOutData
|
||||
* Point to data buffer.
|
||||
*
|
||||
* @return int, -1:indicates failure,others indicates success.
|
||||
*
|
||||
*/
|
||||
int SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData);
|
||||
|
||||
/**
|
||||
* @brief Load data to slave send buffer.
|
||||
*
|
||||
* @param [in] spiNum
|
||||
* Indicates which submode to be used, SPI or HSPI.
|
||||
* @param [in] pInData
|
||||
* Point to data buffer.
|
||||
* @param [in] outLen
|
||||
* The number of bytes to be set.
|
||||
*
|
||||
* @return int, -1:indicates failure,others indicates success.
|
||||
*/
|
||||
int SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uint8_t outLen);
|
||||
|
||||
/**
|
||||
* @brief Receive data by slave.
|
||||
*
|
||||
* @param [in] spiNum
|
||||
* Indicates which submode to be used, SPI or HSPI.
|
||||
* @param [in] isrFunc
|
||||
* isrFunc is a pointer to the function to be called when the SPI interrupt occurs.
|
||||
*
|
||||
* @return int, -1:indicates failure,others indicates success.
|
||||
*/
|
||||
int SPISlaveRecvData(SpiNum spiNum, void(*isrFunc)(void*));
|
||||
|
||||
/**
|
||||
* @brief Set slave status by master.
|
||||
*
|
||||
* @param [in] spiNum
|
||||
* Indicates which submode to be used, SPI or HSPI.
|
||||
* @param [in] data
|
||||
* Data will be write to slave SPI_WR_STATUS.
|
||||
*
|
||||
* @return void.
|
||||
*
|
||||
* @attention Just for ESP8266(slave) register of RD_STATUS or WR_STATUS.
|
||||
*/
|
||||
void SPIMasterSendStatus(SpiNum spiNum, uint8_t data);
|
||||
|
||||
/**
|
||||
* @brief Get salve status by master.
|
||||
*
|
||||
* @param [in] spiNum
|
||||
* Indicates which submode to be used, SPI or HSPI.
|
||||
*
|
||||
* @return int, -1: indicates failure; other value in slave status.
|
||||
*
|
||||
* @attention Just for ESP8266(slave) register of RD_STATUS or WR_STATUS.
|
||||
*/
|
||||
int SPIMasterRecvStatus(SpiNum spiNum);
|
||||
|
||||
/**
|
||||
* @brief Select SPI CS pin.
|
||||
*
|
||||
* @param [in] spiNum
|
||||
* Indicates which submode to be used, SPI or HSPI.
|
||||
* @param [in] pinCs
|
||||
* Indicates which SPI pin to choose.
|
||||
*
|
||||
* @return void.
|
||||
*/
|
||||
void SPICsPinSelect(SpiNum spiNum, SpiPinCS pinCs);
|
||||
|
||||
/**
|
||||
* @brief Enable SPI module interrupt source.
|
||||
*
|
||||
* @param [in] spiNum
|
||||
* Indicates which submode to be used, SPI or HSPI.
|
||||
* @param [in] intSrc
|
||||
* Indicates which interrupt source to enable.
|
||||
*
|
||||
* @return void.
|
||||
*/
|
||||
void SPIIntEnable(SpiNum spiNum, SpiIntSrc intSrc);
|
||||
|
||||
/**
|
||||
* @brief Disable SPI module interrupt source.
|
||||
*
|
||||
* @param [in] spiNum
|
||||
* Indicates which submode to be used, SPI or HSPI.
|
||||
* @param [in] intSrc
|
||||
* Indicates which interrupt source to disable.
|
||||
*
|
||||
* @return void.
|
||||
*/
|
||||
void SPIIntDisable(SpiNum spiNum, SpiIntSrc intSrc);
|
||||
|
||||
/**
|
||||
* @brief Clear all of spi interrupt.
|
||||
*
|
||||
* @param [in] spiNum
|
||||
* Indicates which submode to be used, SPI or HSPI.
|
||||
*
|
||||
* @return void.
|
||||
*/
|
||||
void SPIIntClear(SpiNum spiNum);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __SPI_INTERFACE_H__
|
||||
203
components/esp8266/include/driver/spi_register.h
Normal file
203
components/esp8266/include/driver/spi_register.h
Normal file
@ -0,0 +1,203 @@
|
||||
/*
|
||||
* Copyright (c) 2010 - 2011 Espressif System
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SPI_REGISTER_H_INCLUDED
|
||||
#define SPI_REGISTER_H_INCLUDED
|
||||
|
||||
#define REG_SPI_BASE(i) (0x60000200-i*0x100)
|
||||
#define SPI_CMD(i) (REG_SPI_BASE(i) + 0x0)
|
||||
|
||||
#define SPI_FLASH_READ BIT31
|
||||
#define SPI_FLASH_WREN BIT30
|
||||
#define SPI_FLASH_WRDI BIT29
|
||||
#define SPI_FLASH_RDID BIT28
|
||||
#define SPI_FLASH_RDSR BIT27
|
||||
#define SPI_FLASH_WRSR BIT26
|
||||
#define SPI_FLASH_PP BIT25
|
||||
#define SPI_FLASH_SE BIT24
|
||||
#define SPI_FLASH_BE BIT23
|
||||
#define SPI_FLASH_CE BIT22
|
||||
#define SPI_FLASH_RES BIT20
|
||||
|
||||
#define SPI_USR (BIT(18))
|
||||
|
||||
#define SPI_ADDR(i) (REG_SPI_BASE(i) + 0x4)
|
||||
|
||||
#define SPI_CTRL(i) (REG_SPI_BASE(i) + 0x8)
|
||||
#define SPI_WR_BIT_ORDER (BIT(26))
|
||||
#define SPI_RD_BIT_ORDER (BIT(25))
|
||||
#define SPI_QIO_MODE (BIT(24))
|
||||
#define SPI_DIO_MODE (BIT(23))
|
||||
#define SPI_QOUT_MODE (BIT(20))
|
||||
#define SPI_DOUT_MODE (BIT(14))
|
||||
#define SPI_FASTRD_MODE (BIT(13))
|
||||
|
||||
#define SPI_CTRL1(i) (REG_SPI_BASE(i) + 0xc)
|
||||
#define SPI_CS_HOLD_DELAY 0xf
|
||||
#define SPI_CS_HOLD_DELAY_S 28
|
||||
#define SPI_CS_HOLD_DELAY_RES 0xfff
|
||||
#define SPI_CS_HOLD_DELAY_RES_S 16
|
||||
|
||||
|
||||
#define SPI_RD_STATUS(i) (REG_SPI_BASE(i) + 0x10)
|
||||
|
||||
#define SPI_CTRL2(i) (REG_SPI_BASE(i) + 0x14)
|
||||
|
||||
#define SPI_CS_DELAY_NUM 0x0000000F
|
||||
#define SPI_CS_DELAY_NUM_S 28
|
||||
#define SPI_CS_DELAY_MODE 0x00000003
|
||||
#define SPI_CS_DELAY_MODE_S 26
|
||||
#define SPI_MOSI_DELAY_NUM 0x00000007
|
||||
#define SPI_MOSI_DELAY_NUM_S 23
|
||||
#define SPI_MOSI_DELAY_MODE 0x00000003
|
||||
#define SPI_MOSI_DELAY_MODE_S 21
|
||||
#define SPI_MISO_DELAY_NUM 0x00000007
|
||||
#define SPI_MISO_DELAY_NUM_S 18
|
||||
#define SPI_MISO_DELAY_MODE 0x00000003
|
||||
#define SPI_MISO_DELAY_MODE_S 16
|
||||
#define SPI_CLOCK(i) (REG_SPI_BASE(i) + 0x18)
|
||||
#define SPI_CLK_EQU_SYSCLK (BIT(31))
|
||||
#define SPI_CLKDIV_PRE 0x00001FFF
|
||||
#define SPI_CLKDIV_PRE_S 18
|
||||
#define SPI_CLKCNT_N 0x0000003F
|
||||
#define SPI_CLKCNT_N_S 12
|
||||
#define SPI_CLKCNT_H 0x0000003F
|
||||
#define SPI_CLKCNT_H_S 6
|
||||
#define SPI_CLKCNT_L 0x0000003F
|
||||
#define SPI_CLKCNT_L_S 0
|
||||
|
||||
#define SPI_USER(i) (REG_SPI_BASE(i) + 0x1C)
|
||||
#define SPI_USR_COMMAND (BIT(31))
|
||||
#define SPI_USR_ADDR (BIT(30))
|
||||
#define SPI_USR_DUMMY (BIT(29))
|
||||
#define SPI_USR_MISO (BIT(28))
|
||||
#define SPI_USR_MOSI (BIT(27))
|
||||
|
||||
#define SPI_USR_MOSI_HIGHPART (BIT(25))
|
||||
#define SPI_USR_MISO_HIGHPART (BIT(24))
|
||||
|
||||
|
||||
#define SPI_SIO (BIT(16))
|
||||
#define SPI_FWRITE_QIO (BIT(15))
|
||||
#define SPI_FWRITE_DIO (BIT(14))
|
||||
#define SPI_FWRITE_QUAD (BIT(13))
|
||||
#define SPI_FWRITE_DUAL (BIT(12))
|
||||
#define SPI_WR_BYTE_ORDER (BIT(11))
|
||||
#define SPI_RD_BYTE_ORDER (BIT(10))
|
||||
#define SPI_CK_OUT_EDGE (BIT(7))
|
||||
#define SPI_CK_I_EDGE (BIT(6))
|
||||
#define SPI_CS_SETUP (BIT(5))
|
||||
#define SPI_CS_HOLD (BIT(4))
|
||||
#define SPI_FLASH_MODE (BIT(2))
|
||||
|
||||
#define SPI_USER1(i) (REG_SPI_BASE(i) + 0x20)
|
||||
#define SPI_USR_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_USR_ADDR_BITLEN_S 26
|
||||
#define SPI_USR_MOSI_BITLEN 0x000001FF
|
||||
#define SPI_USR_MOSI_BITLEN_S 17
|
||||
#define SPI_USR_MISO_BITLEN 0x000001FF
|
||||
#define SPI_USR_MISO_BITLEN_S 8
|
||||
|
||||
#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_USR_DUMMY_CYCLELEN_S 0
|
||||
|
||||
#define SPI_USER2(i) (REG_SPI_BASE(i) + 0x24)
|
||||
#define SPI_USR_COMMAND_BITLEN 0x0000000F
|
||||
#define SPI_USR_COMMAND_BITLEN_S 28
|
||||
#define SPI_USR_COMMAND_VALUE 0x0000FFFF
|
||||
#define SPI_USR_COMMAND_VALUE_S 0
|
||||
|
||||
#define SPI_WR_STATUS(i) (REG_SPI_BASE(i) + 0x28)
|
||||
#define SPI_PIN(i) (REG_SPI_BASE(i) + 0x2C)
|
||||
#define SPI_IDLE_EDGE (BIT(29))
|
||||
#define SPI_CS2_DIS (BIT(2))
|
||||
#define SPI_CS1_DIS (BIT(1))
|
||||
#define SPI_CS0_DIS (BIT(0))
|
||||
|
||||
#define SPI_SLAVE(i) (REG_SPI_BASE(i) + 0x30)
|
||||
#define SPI_SYNC_RESET (BIT(31))
|
||||
#define SPI_SLAVE_MODE (BIT(30))
|
||||
#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
|
||||
#define SPI_SLV_WR_RD_STA_EN (BIT(28))
|
||||
#define SPI_SLV_CMD_DEFINE (BIT(27))
|
||||
#define SPI_TRANS_CNT 0x0000000F
|
||||
#define SPI_TRANS_CNT_S 23
|
||||
#define SPI_TRANS_DONE_EN (BIT(9))
|
||||
#define SPI_SLV_WR_STA_DONE_EN (BIT(8))
|
||||
#define SPI_SLV_RD_STA_DONE_EN (BIT(7))
|
||||
#define SPI_SLV_WR_BUF_DONE_EN (BIT(6))
|
||||
#define SPI_SLV_RD_BUF_DONE_EN (BIT(5))
|
||||
|
||||
|
||||
|
||||
#define SLV_SPI_INT_EN 0x0000001f
|
||||
#define SLV_SPI_INT_EN_S 5
|
||||
|
||||
#define SPI_TRANS_DONE (BIT(4))
|
||||
#define SPI_SLV_WR_STA_DONE (BIT(3))
|
||||
#define SPI_SLV_RD_STA_DONE (BIT(2))
|
||||
#define SPI_SLV_WR_BUF_DONE (BIT(1))
|
||||
#define SPI_SLV_RD_BUF_DONE (BIT(0))
|
||||
|
||||
#define SPI_SLAVE1(i) (REG_SPI_BASE(i) + 0x34)
|
||||
#define SPI_SLV_STATUS_BITLEN 0x0000001F
|
||||
#define SPI_SLV_STATUS_BITLEN_S 27
|
||||
#define SPI_SLV_BUF_BITLEN 0x000001FF
|
||||
#define SPI_SLV_BUF_BITLEN_S 16
|
||||
#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_SLV_RD_ADDR_BITLEN_S 10
|
||||
#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_SLV_WR_ADDR_BITLEN_S 4
|
||||
|
||||
#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
|
||||
#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
|
||||
#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
|
||||
#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
|
||||
|
||||
|
||||
|
||||
#define SPI_SLAVE2(i) (REG_SPI_BASE(i) + 0x38)
|
||||
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0X000000FF
|
||||
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
|
||||
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0X000000FF
|
||||
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
|
||||
#define SPI_SLV_WRSTR_DUMMY_CYCLELEN 0X000000FF
|
||||
#define SPI_SLV_WRSTR_DUMMY_CYCLELEN_S 8
|
||||
#define SPI_SLV_RDSTR_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_SLV_RDSTR_DUMMY_CYCLELEN_S 0
|
||||
|
||||
#define SPI_SLAVE3(i) (REG_SPI_BASE(i) + 0x3C)
|
||||
#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_WRSTA_CMD_VALUE_S 24
|
||||
#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_RDSTA_CMD_VALUE_S 16
|
||||
#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_WRBUF_CMD_VALUE_S 8
|
||||
#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_RDBUF_CMD_VALUE_S 0
|
||||
|
||||
#define SPI_W0(i) (REG_SPI_BASE(i) +0x40)
|
||||
#define SPI_W1(i) (REG_SPI_BASE(i) +0x44)
|
||||
#define SPI_W2(i) (REG_SPI_BASE(i) +0x48)
|
||||
#define SPI_W3(i) (REG_SPI_BASE(i) +0x4C)
|
||||
#define SPI_W4(i) (REG_SPI_BASE(i) +0x50)
|
||||
#define SPI_W5(i) (REG_SPI_BASE(i) +0x54)
|
||||
#define SPI_W6(i) (REG_SPI_BASE(i) +0x58)
|
||||
#define SPI_W7(i) (REG_SPI_BASE(i) +0x5C)
|
||||
#define SPI_W8(i) (REG_SPI_BASE(i) +0x60)
|
||||
#define SPI_W9(i) (REG_SPI_BASE(i) +0x64)
|
||||
#define SPI_W10(i) (REG_SPI_BASE(i) +0x68)
|
||||
#define SPI_W11(i) (REG_SPI_BASE(i) +0x6C)
|
||||
#define SPI_W12(i) (REG_SPI_BASE(i) +0x70)
|
||||
#define SPI_W13(i) (REG_SPI_BASE(i) +0x74)
|
||||
#define SPI_W14(i) (REG_SPI_BASE(i) +0x78)
|
||||
#define SPI_W15(i) (REG_SPI_BASE(i) +0x7C)
|
||||
|
||||
#define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
|
||||
|
||||
#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
|
||||
#define SPI_INT_HOLD_ENA 0x00000003
|
||||
#define SPI_INT_HOLD_ENA_S 0
|
||||
#endif // SPI_REGISTER_H_INCLUDED
|
||||
294
components/esp8266/include/driver/uart.h
Normal file
294
components/esp8266/include/driver/uart.h
Normal file
@ -0,0 +1,294 @@
|
||||
/*
|
||||
* ESPRSSIF MIT License
|
||||
*
|
||||
* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
|
||||
*
|
||||
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
|
||||
* it is free of charge, to any person obtaining a copy of this software and associated
|
||||
* documentation files (the "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
|
||||
* to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all copies or
|
||||
* substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __UART_H__
|
||||
#define __UART_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define ETS_UART_INTR_ENABLE() _xt_isr_unmask(1 << ETS_UART_INUM)
|
||||
#define ETS_UART_INTR_DISABLE() _xt_isr_mask(1 << ETS_UART_INUM)
|
||||
#define UART_INTR_MASK 0x1ff
|
||||
#define UART_LINE_INV_MASK (0x3f<<19)
|
||||
|
||||
typedef enum {
|
||||
UART_WordLength_5b = 0x0,
|
||||
UART_WordLength_6b = 0x1,
|
||||
UART_WordLength_7b = 0x2,
|
||||
UART_WordLength_8b = 0x3
|
||||
} UART_WordLength;
|
||||
|
||||
typedef enum {
|
||||
USART_StopBits_1 = 0x1,
|
||||
USART_StopBits_1_5 = 0x2,
|
||||
USART_StopBits_2 = 0x3,
|
||||
} UART_StopBits;
|
||||
|
||||
typedef enum {
|
||||
UART0 = 0x0,
|
||||
UART1 = 0x1,
|
||||
} UART_Port;
|
||||
|
||||
typedef enum {
|
||||
USART_Parity_None = 0x2,
|
||||
USART_Parity_Even = 0x0,
|
||||
USART_Parity_Odd = 0x1
|
||||
} UART_ParityMode;
|
||||
|
||||
typedef enum {
|
||||
PARITY_DIS = 0x0,
|
||||
PARITY_EN = 0x2
|
||||
} UartExistParity;
|
||||
|
||||
typedef enum {
|
||||
BIT_RATE_300 = 300,
|
||||
BIT_RATE_600 = 600,
|
||||
BIT_RATE_1200 = 1200,
|
||||
BIT_RATE_2400 = 2400,
|
||||
BIT_RATE_4800 = 4800,
|
||||
BIT_RATE_9600 = 9600,
|
||||
BIT_RATE_19200 = 19200,
|
||||
BIT_RATE_38400 = 38400,
|
||||
BIT_RATE_57600 = 57600,
|
||||
BIT_RATE_74880 = 74880,
|
||||
BIT_RATE_115200 = 115200,
|
||||
BIT_RATE_230400 = 230400,
|
||||
BIT_RATE_460800 = 460800,
|
||||
BIT_RATE_921600 = 921600,
|
||||
BIT_RATE_1843200 = 1843200,
|
||||
BIT_RATE_3686400 = 3686400,
|
||||
} UART_BautRate; //you can add any rate you need in this range
|
||||
|
||||
typedef enum {
|
||||
USART_HardwareFlowControl_None = 0x0,
|
||||
USART_HardwareFlowControl_RTS = 0x1,
|
||||
USART_HardwareFlowControl_CTS = 0x2,
|
||||
USART_HardwareFlowControl_CTS_RTS = 0x3
|
||||
} UART_HwFlowCtrl;
|
||||
|
||||
typedef enum {
|
||||
UART_None_Inverse = 0x0,
|
||||
UART_Rxd_Inverse = UART_RXD_INV,
|
||||
UART_CTS_Inverse = UART_CTS_INV,
|
||||
UART_Txd_Inverse = UART_TXD_INV,
|
||||
UART_RTS_Inverse = UART_RTS_INV,
|
||||
} UART_LineLevelInverse;
|
||||
|
||||
typedef struct {
|
||||
UART_BautRate baud_rate;
|
||||
UART_WordLength data_bits;
|
||||
UART_ParityMode parity; // chip size in byte
|
||||
UART_StopBits stop_bits;
|
||||
UART_HwFlowCtrl flow_ctrl;
|
||||
uint8 UART_RxFlowThresh ;
|
||||
uint32 UART_InverseMask;
|
||||
} UART_ConfigTypeDef;
|
||||
|
||||
typedef struct {
|
||||
uint32 UART_IntrEnMask;
|
||||
uint8 UART_RX_TimeOutIntrThresh;
|
||||
uint8 UART_TX_FifoEmptyIntrThresh;
|
||||
uint8 UART_RX_FifoFullIntrThresh;
|
||||
} UART_IntrConfTypeDef;
|
||||
|
||||
//=======================================
|
||||
|
||||
/** \defgroup Driver_APIs Driver APIs
|
||||
* @brief Driver APIs
|
||||
*/
|
||||
|
||||
/** @addtogroup Driver_APIs
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** \defgroup UART_Driver_APIs UART Driver APIs
|
||||
* @brief UART driver APIs
|
||||
*/
|
||||
|
||||
/** @addtogroup UART_Driver_APIs
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Wait uart tx fifo empty, do not use it if tx flow control enabled.
|
||||
*
|
||||
* @param UART_Port uart_no:UART0 or UART1
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_WaitTxFifoEmpty(UART_Port uart_no); //do not use if tx flow control enabled
|
||||
|
||||
/**
|
||||
* @brief Clear uart tx fifo and rx fifo.
|
||||
*
|
||||
* @param UART_Port uart_no : UART0 or UART1
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_ResetFifo(UART_Port uart_no);
|
||||
|
||||
/**
|
||||
* @brief Clear uart interrupt flags.
|
||||
*
|
||||
* @param UART_Port uart_no : UART0 or UART1
|
||||
* @param uint32 clr_mask : To clear the interrupt bits
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_ClearIntrStatus(UART_Port uart_no, uint32 clr_mask);
|
||||
|
||||
/**
|
||||
* @brief Enable uart interrupts .
|
||||
*
|
||||
* @param UART_Port uart_no : UART0 or UART1
|
||||
* @param uint32 ena_mask : To enable the interrupt bits
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_SetIntrEna(UART_Port uart_no, uint32 ena_mask);
|
||||
|
||||
/**
|
||||
* @brief Register an application-specific interrupt handler for Uarts interrupts.
|
||||
*
|
||||
* @param void *fn : interrupt handler for Uart interrupts.
|
||||
* @param void *arg : interrupt handler's arg.
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_intr_handler_register(void *fn, void *arg);
|
||||
|
||||
/**
|
||||
* @brief Config from which serial output printf function.
|
||||
*
|
||||
* @param UART_Port uart_no : UART0 or UART1
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_SetPrintPort(UART_Port uart_no);
|
||||
|
||||
/**
|
||||
* @brief Config Common parameters of serial ports.
|
||||
*
|
||||
* @param UART_Port uart_no : UART0 or UART1
|
||||
* @param UART_ConfigTypeDef *pUARTConfig : parameters structure
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef *pUARTConfig);
|
||||
|
||||
/**
|
||||
* @brief Config types of uarts.
|
||||
*
|
||||
* @param UART_Port uart_no : UART0 or UART1
|
||||
* @param UART_IntrConfTypeDef *pUARTIntrConf : parameters structure
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef *pUARTIntrConf);
|
||||
|
||||
/**
|
||||
* @brief Config the length of the uart communication data bits.
|
||||
*
|
||||
* @param UART_Port uart_no : UART0 or UART1
|
||||
* @param UART_WordLength len : the length of the uart communication data bits
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_SetWordLength(UART_Port uart_no, UART_WordLength len);
|
||||
|
||||
/**
|
||||
* @brief Config the length of the uart communication stop bits.
|
||||
*
|
||||
* @param UART_Port uart_no : UART0 or UART1
|
||||
* @param UART_StopBits bit_num : the length uart communication stop bits
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_SetStopBits(UART_Port uart_no, UART_StopBits bit_num);
|
||||
|
||||
/**
|
||||
* @brief Configure whether to open the parity.
|
||||
*
|
||||
* @param UART_Port uart_no : UART0 or UART1
|
||||
* @param UART_ParityMode Parity_mode : the enum of uart parity configuration
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode) ;
|
||||
|
||||
/**
|
||||
* @brief Configure the Baud rate.
|
||||
*
|
||||
* @param UART_Port uart_no : UART0 or UART1
|
||||
* @param uint32 baud_rate : the Baud rate
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_SetBaudrate(UART_Port uart_no, uint32 baud_rate);
|
||||
|
||||
/**
|
||||
* @brief Configure Hardware flow control.
|
||||
*
|
||||
* @param UART_Port uart_no : UART0 or UART1
|
||||
* @param UART_HwFlowCtrl flow_ctrl : Hardware flow control mode
|
||||
* @param uint8 rx_thresh : threshold of Hardware flow control
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8 rx_thresh);
|
||||
|
||||
/**
|
||||
* @brief Configure trigging signal of uarts.
|
||||
*
|
||||
* @param UART_Port uart_no : UART0 or UART1
|
||||
* @param UART_LineLevelInverse inverse_mask : Choose need to flip the IO
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void UART_SetLineInverse(UART_Port uart_no, UART_LineLevelInverse inverse_mask) ;
|
||||
|
||||
/**
|
||||
* @brief An example illustrates how to configure the serial port.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void uart_init_new(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user