mirror of
https://github.com/espressif/ESP8266_RTOS_SDK.git
synced 2025-08-05 22:11:04 +08:00
feat(bootloader): Support v2 firmware updates to v3 by OTA
This commit is contained in:
Dong Heng
@ -9,3 +9,10 @@ COMPONENT_OBJS := src/spi_flash.o src/spi_flash_raw.o
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endif
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CFLAGS += -DPARTITION_QUEUE_HEADER=\"sys/queue.h\"
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ifdef CONFIG_ESP8266_OTA_FROM_OLD
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ifdef IS_BOOTLOADER_BUILD
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COMPONENT_SRCDIRS += port
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COMPONENT_OBJS += port/port.o
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endif
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endif
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@ -32,6 +32,8 @@ extern "C" {
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#define SPI_READ_BUF_MAX 64
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#define SPI_FLASH_CACHE2PHYS_FAIL UINT32_MAX /*<! Result from spi_flash_cache2phys() if flash cache address is invalid */
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#ifdef CONFIG_ENABLE_FLASH_MMAP
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/**
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* @brief Enumeration which specifies memory space requested in an mmap call
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@ -149,6 +151,50 @@ void spi_flash_munmap(spi_flash_mmap_handle_t handle);
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#endif /* CONFIG_ENABLE_FLASH_MMAP */
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/**
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* @brief Given a memory address where flash is mapped, return the corresponding physical flash offset.
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*
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* Cache address does not have have been assigned via spi_flash_mmap(), any address in memory mapped flash space can be looked up.
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*
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* @param cached Pointer to flashed cached memory.
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*
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* @return
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* - SPI_FLASH_CACHE2PHYS_FAIL If cache address is outside flash cache region, or the address is not mapped.
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* - Otherwise, returns physical offset in flash
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*/
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uintptr_t spi_flash_cache2phys(const void *cached);
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#ifdef CONFIG_ESP8266_OTA_FROM_OLD
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/**
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* @brief Check if current firmware updates from V2 firmware and its location is at "APP2", if so, then V3 bootloader
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* will copy patition table from "APP2" location to "APP1" location of V2 partition map.
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*
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* @return 0 if success or others if failed
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*/
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int esp_patition_table_init_location(void);
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/**
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* @brief Check if current firmware updates from V2 firmware and its location is at "APP2", if so, then V3 bootloader
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* will copy firmware from "APP2" location to "APP1" location.
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*
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* @note All data which is copied is "ota0" application and all data whose location is before "ota0".
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*
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* @return 0 if success or others if failed
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*/
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int esp_patition_table_init_data(void *partition_info);
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#endif
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#ifdef CONFIG_ESP8266_BOOT_COPY_APP
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/**
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* @brief Check if current application which is to run is at "ota1" location, if so, bootloader will copy it to "ota0" location,
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* and clear OTA data partition.
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*
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* @return 0 if success or others if failed
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*/
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int esp_patition_copy_ota1_to_ota0(const void *partition_info);
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#endif
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#ifdef __cplusplus
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}
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#endif
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385
components/spi_flash/port/port.c
Normal file
385
components/spi_flash/port/port.c
Normal file
@ -0,0 +1,385 @@
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "sdkconfig.h"
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#if defined(CONFIG_ESP8266_OTA_FROM_OLD) && defined(BOOTLOADER_BUILD)
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#include <string.h>
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#include <stdint.h>
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#include "esp_flash_data_types.h"
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#include "esp_spi_flash.h"
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#include "esp_log.h"
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#include "esp_image_format.h"
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#include "bootloader_config.h"
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#include "esp_libc.h"
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#include "esp8266/rom_functions.h"
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#include "esp8266/eagle_soc.h"
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#define PARTITION_DATA_OFFSET (CONFIG_SPI_FLASH_SIZE / 2)
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typedef struct s_sys_param {
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uint8_t flag;
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uint8_t reserved1[3];
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uint32_t reserved2[7];
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} sys_param_t;
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typedef union s_boot_param {
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struct {
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uint8_t usr_bin : 4;
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uint8_t flag : 4;
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} boot_1;
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struct {
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uint8_t usr_bin : 4;
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uint8_t flag : 4;
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uint8_t version;
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} boot_2;
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struct {
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uint8_t usr_bin : 2;
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uint8_t boot_statue : 1;
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uint8_t to_qio : 1;
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uint8_t reserved1 : 4;
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uint8_t version : 5;
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uint8_t test_pass_flag : 1;
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uint8_t test_start_flag : 1;
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uint8_t enhance_boot_flag : 1;
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} boot_base;
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uint8_t data[4096];
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} boot_param_t;
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static const char *TAG = "partition_port";
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static uint32_t s_partition_offset;
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static uint8_t s_cache_buf[SPI_FLASH_SEC_SIZE];
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static sys_param_t s_sys_param;
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static boot_param_t s_boot_param;
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static esp_spi_flash_chip_t s_flash_chip = {
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0x1640ef,
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CONFIG_SPI_FLASH_SIZE,
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64 * 1024,
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4 * 1024,
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256,
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0xffff
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};
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static inline void esp_hw_reset(void)
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{
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CLEAR_WDT_REG_MASK(WDT_CTL_ADDRESS, BIT0);
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WDT_REG_WRITE(WDT_OP_ADDRESS, 8);
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WDT_REG_WRITE(WDT_OP_ND_ADDRESS, 8);
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SET_PERI_REG_BITS(PERIPHS_WDT_BASEADDR + WDT_CTL_ADDRESS, WDT_CTL_RSTLEN_MASK, 7 << WDT_CTL_RSTLEN_LSB, 0);
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// interrupt then reset
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SET_PERI_REG_BITS(PERIPHS_WDT_BASEADDR + WDT_CTL_ADDRESS, WDT_CTL_RSPMOD_MASK, 0 << WDT_CTL_RSPMOD_LSB, 0);
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// start task watch dog1
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SET_PERI_REG_BITS(PERIPHS_WDT_BASEADDR + WDT_CTL_ADDRESS, WDT_CTL_EN_MASK, 1 << WDT_CTL_EN_LSB, 0);
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while (1);
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}
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static inline int spi_flash_read_data(uint32_t addr, void *buf, size_t n)
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{
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int ret;
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ESP_LOGD(TAG, "read buffer %p total %d from 0x%x", buf, n ,addr);
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ret = SPI_read_data(&s_flash_chip, addr, buf, n);
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return ret;
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}
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static inline int spi_flash_write_data(uint32_t addr, const void *buf, uint32_t n)
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{
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int ret;
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ESP_LOGD(TAG, "write buffer %p total %d to 0x%x", buf, n ,addr);
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ret = SPIWrite(addr, (void *)buf, n);
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return ret;
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}
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static inline int spi_flash_erase(uint32_t addr)
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{
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int ret;
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ESP_LOGD(TAG, "erase addr is 0x%x", addr);
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ret = SPIEraseSector(addr / SPI_FLASH_SEC_SIZE);
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return ret;
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}
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static inline uint32_t esp_get_updated_partition_table_addr(void)
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{
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int ret;
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size_t offset;
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uint8_t user_bin;
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const uint32_t sect = CONFIG_SPI_FLASH_SIZE / SPI_FLASH_SEC_SIZE - 3;
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if (s_partition_offset)
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return s_partition_offset;
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ret = spi_flash_read_data((sect + 2) * SPI_FLASH_SEC_SIZE, &s_sys_param, sizeof(sys_param_t));
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if (ret) {
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ESP_LOGE(TAG, "read V2 system param error %d", ret);
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return -1UL;
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}
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ESP_LOGD(TAG, "V2 system flag is %x", s_sys_param.flag);
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offset = s_sys_param.flag ? 1 : 0;
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ret = spi_flash_read_data((sect + offset) * SPI_FLASH_SEC_SIZE, &s_boot_param, sizeof(boot_param_t));
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if (ret) {
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ESP_LOGE(TAG, "read V2 boot param error %d", ret);
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return -1UL;
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}
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if (s_boot_param.boot_base.usr_bin == 1) {
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if (s_boot_param.boot_base.boot_statue == 1)
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user_bin = 1;
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else
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user_bin = 0;
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} else {
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if (s_boot_param.boot_base.boot_statue == 1)
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user_bin = 0;
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else {
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if (s_boot_param.boot_base.version == 4)
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user_bin = 0;
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else
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user_bin = 1;
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}
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}
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if (user_bin)
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s_partition_offset = CONFIG_PARTITION_TABLE_OFFSET + PARTITION_DATA_OFFSET;
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else
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s_partition_offset = CONFIG_PARTITION_TABLE_OFFSET;
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ESP_LOGD(TAG, "Boot info %x %x %x %x %x", s_boot_param.boot_base.usr_bin, s_boot_param.boot_base.boot_statue,
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s_boot_param.boot_base.version, user_bin, s_partition_offset);
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return s_partition_offset;
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}
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static inline int spi_flash_write_data_safe(uint32_t addr, const void *buf, size_t n)
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{
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int ret;
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static uint8_t check_buf[SPI_FLASH_SEC_SIZE];
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ret = spi_flash_erase(addr);
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if (ret) {
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ESP_LOGE(TAG, "erase flash 0x%x error", addr);
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return -1;
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}
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ret = spi_flash_write_data(addr, buf, n);
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if (ret) {
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ESP_LOGE(TAG, "write flash %d bytes to 0x%x error", n, addr);
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return 0;
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}
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ret = spi_flash_read_data(addr, check_buf, n);
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if (ret) {
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ESP_LOGE(TAG, "read flash %d bytes from 0x%x error", n, addr);
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return -1;
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}
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if (memcmp(buf, check_buf, n)) {
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ESP_LOGE(TAG, "check write flash %d bytes to 0x%x error", n, addr);
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return -1;
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}
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return 0;
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}
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static int esp_flash_sector_copy(uint32_t dest, uint32_t src, uint32_t total_size)
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{
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ESP_LOGD(TAG, "Start to copy data from 0x%x to 0x%x total %d", src, dest, total_size);
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for (uint32_t offset = 0; offset < total_size; offset += SPI_FLASH_SEC_SIZE) {
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int ret;
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ret = spi_flash_read_data(src + offset, s_cache_buf, SPI_FLASH_SEC_SIZE);
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if (ret) {
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ESP_LOGE(TAG, "read flash %d bytes from 0x%x error", SPI_FLASH_SEC_SIZE, src + offset);
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return -1;
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}
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ret = spi_flash_write_data_safe(dest + offset, s_cache_buf, SPI_FLASH_SEC_SIZE);
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if (ret) {
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ESP_LOGE(TAG, "write flash %d bytes to 0x%x error", SPI_FLASH_SEC_SIZE, dest + offset);
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return -1;
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}
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}
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return 0;
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}
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static inline int esp_set_v2boot_app1(void)
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{
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int ret;
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size_t offset = s_sys_param.flag ? 1 : 0;
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const uint32_t base_addr = CONFIG_SPI_FLASH_SIZE / SPI_FLASH_SEC_SIZE - 3;
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const uint32_t sys_addr = (base_addr + 2) * SPI_FLASH_SEC_SIZE;
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const uint32_t to_addr = (base_addr + 1 - offset) * SPI_FLASH_SEC_SIZE;
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if (s_boot_param.boot_base.version == 0x2
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|| s_boot_param.boot_base.version == 0x1f) {
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if (s_boot_param.boot_base.usr_bin == 1)
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s_boot_param.boot_base.usr_bin = 0;
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else
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s_boot_param.boot_base.usr_bin = 1;
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} else {
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s_boot_param.boot_base.enhance_boot_flag = 1;
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if (s_boot_param.boot_base.boot_statue != 0) {
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if (s_boot_param.boot_base.usr_bin == 1)
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s_boot_param.boot_base.usr_bin = 0;
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else
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s_boot_param.boot_base.usr_bin = 1;
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}
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s_boot_param.boot_base.boot_statue = 1;
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}
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ESP_LOGD(TAG, "Boot info %x %x %x", s_boot_param.boot_base.usr_bin, s_boot_param.boot_base.boot_statue, s_boot_param.boot_base.version);
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ret = spi_flash_write_data_safe(to_addr, &s_boot_param, sizeof(boot_param_t));
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if (ret) {
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ESP_LOGE(TAG, "write flash %d bytes to 0x%x error", sizeof(boot_param_t), to_addr);
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return -1;
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}
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if (s_sys_param.flag)
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s_sys_param.flag = 0;
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else
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s_sys_param.flag = 1;
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ret = spi_flash_write_data_safe(sys_addr, &s_sys_param, sizeof(sys_param_t));
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if (ret) {
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ESP_LOGE(TAG, "write flash %d bytes to 0x%x error", SPI_FLASH_SEC_SIZE, sys_addr);
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return -1;
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}
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return 0;
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}
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static inline int esp_sdk_update_from_v2(void)
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{
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const int segment_cnt = 3;
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const size_t v2_max_size = 4096;
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uint32_t segment_base = sizeof(esp_image_header_t);
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uint32_t segment_size = 0;
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if (s_partition_offset)
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return 1;
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for (int i = 0 ; i < segment_cnt; i++) {
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int ret;
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esp_image_segment_header_t segment;
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ret = spi_flash_read_data(segment_base, &segment, sizeof(esp_image_segment_header_t));
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if (ret) {
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ESP_LOGE(TAG, "%d read segment @0x%x is %d", i, segment_base, ret);
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return -1UL;
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}
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ESP_LOGD(TAG, "data is %x len is %d", segment.load_addr, segment.data_len);
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segment_size += segment.data_len;
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segment_base += sizeof(esp_image_segment_header_t) + segment.data_len;
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}
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ESP_LOGD(TAG, "boot total segment size is %u", segment_size);
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return segment_size <= v2_max_size;
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}
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int esp_patition_table_init_location(void)
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{
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uint32_t addr;
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if (!esp_sdk_update_from_v2())
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return 0;
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addr = esp_get_updated_partition_table_addr();
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if (addr == CONFIG_PARTITION_TABLE_OFFSET)
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return 0;
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return esp_flash_sector_copy(CONFIG_PARTITION_TABLE_OFFSET, addr, SPI_FLASH_SEC_SIZE);
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}
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int esp_patition_copy_ota1_to_ota0(const void *partition_info)
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{
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int ret;
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bootloader_state_t *bs = (bootloader_state_t *)partition_info;
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ret = esp_flash_sector_copy(bs->ota[0].offset, bs->ota[1].offset, bs->ota[1].size);
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if (ret) {
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ESP_LOGE(TAG, "Fail to copy OTA from 0x%x to 0x%x total %d", bs->ota[1].offset,
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bs->ota[0].offset, bs->ota[1].size);
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return -1;
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}
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for (uint32_t offset = 0; offset < bs->ota_info.size; offset += SPI_FLASH_SEC_SIZE) {
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ret = spi_flash_erase(bs->ota_info.offset + offset);
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if (ret) {
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ESP_LOGE(TAG, "Fail to erase OTA data from 0x%x", bs->ota_info.offset + offset);
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return -1;
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}
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}
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return 0;
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}
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int esp_patition_table_init_data(void *partition_info)
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{
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int ret;
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const uint32_t boot_base = 0x1000;
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const uint32_t boot_size = CONFIG_SPI_FLASH_SIZE / 2 - boot_base - 4 * SPI_FLASH_SEC_SIZE;
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if (!esp_sdk_update_from_v2())
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return 0;
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if (esp_get_updated_partition_table_addr() == CONFIG_PARTITION_TABLE_OFFSET)
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return 0;
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ESP_LOGD(TAG, "Copy firmware1 from %d total %d", boot_base + PARTITION_DATA_OFFSET, boot_size);
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||||
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ret = esp_flash_sector_copy(boot_base, boot_base + PARTITION_DATA_OFFSET, boot_size);
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if (ret) {
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ESP_LOGE(TAG, "Fail to copy V3 bootloader from 0x%x to 0x%x total %d", boot_base + PARTITION_DATA_OFFSET,
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boot_base, boot_size);
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return -1;
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}
|
||||
|
||||
ret = esp_set_v2boot_app1();
|
||||
if (ret) {
|
||||
ESP_LOGE(TAG, "Fail to update V2 bootloader data");
|
||||
return -1;
|
||||
}
|
||||
|
||||
esp_hw_reset();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ESP8266_OTA_FROM_OLD */
|
||||
@ -751,3 +751,29 @@ void esp_spi_flash_init(uint32_t spi_speed, uint32_t spi_mode)
|
||||
ESP_EARLY_LOGI("qio_mode", "Enabling default flash chip QIO");
|
||||
}
|
||||
}
|
||||
|
||||
uintptr_t spi_flash_cache2phys(const void *cached)
|
||||
{
|
||||
uint32_t map_size;
|
||||
uintptr_t addr_offset;
|
||||
uintptr_t addr = (uintptr_t)cached;
|
||||
|
||||
const uint32_t reg = REG_READ(CACHE_FLASH_CTRL_REG);
|
||||
const uint32_t segment = (reg >> CACHE_MAP_SEGMENT_S) & CACHE_MAP_SEGMENT_MASK;
|
||||
|
||||
if (reg & CACHE_MAP_2M) {
|
||||
map_size = CACHE_2M_SIZE;
|
||||
addr_offset = 0;
|
||||
} else {
|
||||
map_size = CACHE_1M_SIZE;
|
||||
if (reg & CACHE_MAP_1M_HIGH)
|
||||
addr_offset = CACHE_1M_SIZE;
|
||||
else
|
||||
addr_offset = 0;
|
||||
}
|
||||
|
||||
if (addr <= CACHE_BASE_ADDR || addr >= CACHE_BASE_ADDR + map_size)
|
||||
return SPI_FLASH_CACHE2PHYS_FAIL;
|
||||
|
||||
return segment * CACHE_2M_SIZE + (addr + addr_offset - CACHE_BASE_ADDR);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user