feat(bootloader): Support v2 firmware updates to v3 by OTA

This commit is contained in:
Dong Heng
2018-11-09 19:54:17 +08:00
parent ef79175caf
commit 11db1b0daf
18 changed files with 752 additions and 15 deletions

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@ -140,6 +140,12 @@
#define WDT_CTL_EN_LSB 0
#define WDT_FEED_VALUE 0x73
#define WDT_REG_READ(_reg) REG_READ(PERIPHS_WDT_BASEADDR + _reg)
#define WDT_REG_WRITE(_reg, _val) REG_WRITE(PERIPHS_WDT_BASEADDR + _reg, _val)
#define CLEAR_WDT_REG_MASK(_reg, _mask) WDT_REG_WRITE(_reg, WDT_REG_READ(_reg) & (~_mask))
#define WDT_FEED() WDT_REG_WRITE(WDT_RST_ADDRESS, WDT_FEED_VALUE)
//}}
//RTC reg {{

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@ -33,6 +33,10 @@ int SPI_write_status(esp_spi_flash_chip_t *chip, uint32_t status);
int SPI_read_status(esp_spi_flash_chip_t *chip, uint32_t *status);
int Enable_QMode(esp_spi_flash_chip_t *chip);
int SPIWrite(uint32_t addr, const uint8_t *src, uint32_t size);
int SPIRead(uint32_t addr, void *dst, uint32_t size);
int SPIEraseSector(uint32_t sector_num);
void Cache_Read_Disable();
void Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v);

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@ -263,6 +263,14 @@ extern "C" {
#define PERIPHS_SPI_FLASH_USRREG (0x60000200 + 0x1c)
#define CACHE_MAP_1M_HIGH BIT25
#define CACHE_MAP_2M BIT24
#define CACHE_MAP_SEGMENT_S 16
#define CACHE_MAP_SEGMENT_MASK 0x3
#define CACHE_BASE_ADDR 0x40200000
#define CACHE_2M_SIZE 0x00200000
#define CACHE_1M_SIZE 0x00100000
#ifdef __cplusplus
}
#endif